From 061cd78a1aba4a31ee61dc6f6bafc3a35537cf3e Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Sat, 23 May 2020 15:54:43 +0200 Subject: soc/intel/cannonlake: Add RP configuration settings Add RP configuration settings like Advanced Error Reporting(AER), Latency Tolerence Reporting (LTR), Max Payload and Active State Power Management (ASPM). Tested on CFL platform Change-Id: Ifaf0cc86ea412ce246723613f99908946d89ccb0 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/41679 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/chip.h | 23 +++++++++++++++++++++++ src/soc/intel/cannonlake/fsp_params.c | 14 +++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index a30f732ce3..4b48a2184a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -181,6 +181,29 @@ struct soc_intel_cannonlake_config { /* Enable/Disable HotPlug support for Root Port */ uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* + * Enable/Disable AER (Advanced Error Reporting) for Root Port + * 0: Disable AER + * 1: Enable AER + */ + uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; + + /* PCIE RP ASPM, ASPM support for the root port */ + enum { + AspmDefault, + AspmDisabled, + AspmL0s, + AspmL1, + AspmL0sL1, + AspmAutoConfig, + } PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; + + /* PCIE RP Max Payload, Max Payload Size supported */ + enum { + RpMaxPayload_128, + RpMaxPayload_256, + } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; + /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; /* Need to update DLL setting to get Emmc running at HS400 speed */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 8788838c3f..a3b5588b77 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -319,10 +319,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(config->PcieClkSrcUsage)); memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, sizeof(config->PcieClkSrcClkReq)); + + memcpy(params->PcieRpAdvancedErrorReporting, + config->PcieRpAdvancedErrorReporting, + sizeof(params->PcieRpAdvancedErrorReporting)); + memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(config->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(config->PcieRpHotPlug)); + sizeof(params->PcieRpHotPlug)); + + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; + if (config->PcieRpAspm[i]) + params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; + }; + /* eMMC and SD */ dev = pcidev_path_on_root(PCH_DEVFN_EMMC); -- cgit v1.2.3