From 05a2b1aacdc9f8c47d6e0f857a0429b54816ca48 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 18 Jul 2017 15:19:18 +0200 Subject: siemens/mc_apl1: Activate ECC for DRAM This mainboard is equipped with DDR3L modules which support ECC. The BWG says that for activating ECC the FSP-M parameter MemoryDown must be set to 5. Change-Id: Idc68df1e2bae2396c9b9788d4a026a75b7d9119b Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/20634 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_apl1/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index 3347f23450..3462c76c13 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -57,7 +57,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* DRAM Config settings */ memupd->FspmConfig.Package = 0x1; memupd->FspmConfig.Profile = 0x19; - memupd->FspmConfig.MemoryDown = 0x1; + memupd->FspmConfig.MemoryDown = 0x5; memupd->FspmConfig.DDR3LPageSize = 0x2; memupd->FspmConfig.DDR3LASR = 0x0; memupd->FspmConfig.ScramblerSupport = 0x0; -- cgit v1.2.3