From 04b02069e26484caf2737a863404daf4a438714b Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Tue, 3 Mar 2020 18:33:00 +0100 Subject: soc/intel/common/block/tco: clear TCO1_STS register, too MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The register TCO1_STS is never cleared, which will cause SMIs to either retrigger over and over again (e.g. TIMEOUT) or prevent concurrent interrupt events, depending on which event triggered. Clear both TCO2_STS and TCO1_STS. This also fixes the issue where SECOND_TO_STS will always end up set in the SMI handler by unconditionally (re)setting it. Tested on X11SSM-F, where enabling TCO caused the terminal to get flooded with SMI debug messages. With this patch, a message gets written every ~1 second. Signed-off-by: Michael Niewöhner Change-Id: Ia57c203a672fdd0095355a7e2a0e01aaa6657968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39259 Reviewed-by: Patrick Rudolph Reviewed-by: Andrey Petrov Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/smbus/tco.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1a215eb69d..bd8790aa6e 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -74,13 +74,13 @@ uint32_t tco_reset_status(void) uint16_t tco1_sts; uint16_t tco2_sts; - /* TCO Status 2 register */ - tco2_sts = tco_read_reg(TCO2_STS); - tco2_sts |= TCO_STS_SECOND_TO; - tco_write_reg(TCO2_STS, tco2_sts); - /* TCO Status 1 register */ tco1_sts = tco_read_reg(TCO1_STS); + tco_write_reg(TCO1_STS, tco1_sts); + + /* TCO Status 2 register */ + tco2_sts = tco_read_reg(TCO2_STS); + tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO); return (tco2_sts << 16) | tco1_sts; } -- cgit v1.2.3