From 042772a6bd66cd09add08da40785406e34e92d0a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 30 Nov 2018 00:06:51 +0100 Subject: mb/emulation/spike-riscv: Implement mtime_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch lets spike boot to "Payload not loaded" again. Because soc/ucb/riscv/ does not represent a real SoC, but is a dummy directory for emulators, and different emulators might have different memory maps, I moved mtime_init to the mainboard-specific directories for Spike and QEMU. Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/c/28873 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Hug --- src/mainboard/emulation/qemu-riscv/Makefile.inc | 4 ++++ src/mainboard/emulation/qemu-riscv/mtime.c | 22 ++++++++++++++++++++ src/mainboard/emulation/spike-riscv/Makefile.inc | 2 ++ src/mainboard/emulation/spike-riscv/clint.c | 26 ++++++++++++++++++++++++ src/soc/ucb/riscv/Makefile.inc | 2 -- src/soc/ucb/riscv/mtime.c | 22 -------------------- 6 files changed, 54 insertions(+), 24 deletions(-) create mode 100644 src/mainboard/emulation/qemu-riscv/mtime.c create mode 100644 src/mainboard/emulation/spike-riscv/clint.c delete mode 100644 src/soc/ucb/riscv/mtime.c (limited to 'src') diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 36f1fca58c..1d882acc63 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -14,11 +14,15 @@ bootblock-y += uart.c bootblock-y += rom_media.c +bootblock-y += mtime.c + romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c + ramstage-y += uart.c ramstage-y += rom_media.c +ramstage-y += mtime.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/mainboard/emulation/qemu-riscv/mtime.c b/src/mainboard/emulation/qemu-riscv/mtime.c new file mode 100644 index 0000000000..f8c2717563 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/mtime.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* FIXME: This is an empty implementation, please improve */ +/* This function is used to initialize HLS()->time/HLS()->timecmp */ +void mtime_init(void) +{ +} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index 36f1fca58c..38977b6345 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -14,11 +14,13 @@ bootblock-y += uart.c bootblock-y += rom_media.c +bootblock-y += clint.c romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c ramstage-y += uart.c ramstage-y += rom_media.c +ramstage-y += clint.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c new file mode 100644 index 0000000000..7ad3f5a7af --- /dev/null +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define SPIKE_CLINT_BASE 0x02000000 + +/* This function is used to initialize HLS()->time/HLS()->timecmp */ +void mtime_init(void) +{ + long hart_id = read_csr(mhartid); + HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8); + HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id); +} diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index c96e3637b7..ef03642d89 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -1,13 +1,11 @@ ifeq ($(CONFIG_SOC_UCB_RISCV),y) -bootblock-y += mtime.c bootblock-y += ipi.c romstage-y += cbmem.c romstage-y += ipi.c ramstage-y += cbmem.c -ramstage-y += mtime.c ramstage-y += ipi.c endif diff --git a/src/soc/ucb/riscv/mtime.c b/src/soc/ucb/riscv/mtime.c deleted file mode 100644 index f8c2717563..0000000000 --- a/src/soc/ucb/riscv/mtime.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* FIXME: This is an empty implementation, please improve */ -/* This function is used to initialize HLS()->time/HLS()->timecmp */ -void mtime_init(void) -{ -} -- cgit v1.2.3