From 03f0e43a3c4172941f2eadf30f89413632b90cb4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Jul 2020 13:51:15 +0200 Subject: haswell: Drop GPIO indirection layers This simplifies things and makes type checking possible. Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103 Tested-by: build bot (Jenkins) Reviewed-by: Tristan Corrick --- src/mainboard/asrock/b85m_pro4/romstage.c | 1 - src/mainboard/asrock/h81m-hds/romstage.c | 1 - src/mainboard/google/beltino/romstage.c | 3 --- src/mainboard/google/slippy/romstage.c | 3 --- src/mainboard/intel/baskingridge/romstage.c | 1 - src/mainboard/lenovo/t440p/romstage.c | 1 - src/mainboard/supermicro/x10slm-f/romstage.c | 1 - src/northbridge/intel/haswell/haswell.h | 1 - src/northbridge/intel/haswell/romstage.c | 2 +- src/southbridge/intel/lynxpoint/early_pch.c | 7 ++++--- src/southbridge/intel/lynxpoint/pch.h | 2 +- 11 files changed, 6 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index c29e219ec1..a72418a8e9 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -72,7 +72,6 @@ void mainboard_romstage_entry(void) struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, }; romstage_common(&romstage_params); diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 078e87c850..73c38e7c4b 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -72,7 +72,6 @@ void mainboard_romstage_entry(void) struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, }; romstage_common(&romstage_params); diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index c49d94fe3e..5d9c37c016 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -11,8 +11,6 @@ #include #include "onboard.h" -extern const struct pch_lp_gpio_map mainboard_gpio_map[]; - void mainboard_config_rcba(void) { /* @@ -107,7 +105,6 @@ void mainboard_romstage_entry(void) struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, }; /* Early SuperIO setup */ diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index bc14ee029c..5261ddc377 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -8,8 +8,6 @@ #include #include "variant.h" -extern const struct pch_lp_gpio_map mainboard_gpio_map[]; - void mainboard_config_rcba(void) { /* @@ -77,7 +75,6 @@ void mainboard_romstage_entry(void) struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, }; variant_romstage_entry(&romstage_params); diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 58c684d98b..abbd8521cb 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -114,7 +114,6 @@ void mainboard_romstage_entry(void) struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .copy_spd = NULL, }; diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index 70fc2024e6..bd1020deb8 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -74,7 +74,6 @@ void mainboard_romstage_entry(void) struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, }; romstage_common(&romstage_params); diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 05725ffc66..8bcabd911c 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -70,7 +70,6 @@ void mainboard_romstage_entry(void) struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, }; romstage_common(&romstage_params); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 1ec4cd1cb9..fa32ecad7c 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -192,7 +192,6 @@ void intel_northbridge_haswell_finalize_smm(void); struct pei_data; struct romstage_params { struct pei_data *pei_data; - const void *gpio_map; void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index c3d9a1088a..8cf2e7ca71 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -19,7 +19,7 @@ void romstage_common(const struct romstage_params *params) enable_lapic(); - wake_from_s3 = early_pch_init(params->gpio_map); + wake_from_s3 = early_pch_init(); /* Perform some early chipset initialization required * before RAM initialization can work diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 4d29564f3d..92cbf0176f 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -13,6 +13,7 @@ #if CONFIG(INTEL_LYNXPOINT_LP) #include "lp_gpio.h" +extern const struct pch_lp_gpio_map mainboard_gpio_map[]; #else #include #endif @@ -77,16 +78,16 @@ void __weak mainboard_config_superio(void) { } -int early_pch_init(const void *gpio_map) +int early_pch_init(void) { int wake_from_s3; pch_enable_bars(); #if CONFIG(INTEL_LYNXPOINT_LP) - setup_pch_lp_gpios(gpio_map); + setup_pch_lp_gpios(mainboard_gpio_map); #else - setup_pch_gpios(gpio_map); + setup_pch_gpios(&mainboard_gpio_map); #endif pch_generic_setup(); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7987486673..c59878e48e 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -121,7 +121,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void enable_usb_bar(void); -int early_pch_init(const void *gpio_map); +int early_pch_init(void); void pch_enable_lpc(void); void mainboard_config_superio(void); void mainboard_config_rcba(void); -- cgit v1.2.3