From 033aa0dfc3e6c2478b6e21a75c751293ddeb6d35 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 14:26:37 -0700 Subject: soc/amd/picasso: Add support for using common SoC configuration This change adds support for using common SoC configuration by adding soc_amd_common_config to soc_amd_picasso_config and helper function to return pointer to the structure to amd common block code. Change-Id: I8bd4eac3b19c9ded2d9a3e95ac077f014730f9d1 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41249 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin --- src/soc/amd/picasso/Makefile.inc | 5 +++++ src/soc/amd/picasso/chip.h | 2 ++ src/soc/amd/picasso/config.c | 12 ++++++++++++ 3 files changed, 19 insertions(+) create mode 100644 src/soc/amd/picasso/config.c (limited to 'src') diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 0e5466161b..43bb32e7f0 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -18,6 +18,7 @@ bootblock-$(CONFIG_PICASSO_UART) += uart.c bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += smi_util.c +bootblock-y += config.c romstage-y += i2c.c romstage-y += romstage.c @@ -31,10 +32,12 @@ romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += soc_util.c romstage-y += psp.c romstage-y += mtrr.c +romstage-y += config.c verstage-y += gpio.c verstage-y += i2c.c verstage-y += pmutil.c +verstage-y += config.c verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c @@ -59,6 +62,7 @@ ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += psp.c ramstage-y += fsp_params.c +ramstage-y += config.c all-y += reset.c @@ -68,6 +72,7 @@ smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c smm-y += psp.c +smm-y += config.c CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 9b77e84736..2b9ef3c37a 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -13,6 +14,7 @@ #include struct soc_amd_picasso_config { + struct soc_amd_common_config common_config; /* * If sb_reset_i2c_slaves() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. diff --git a/src/soc/amd/picasso/config.c b/src/soc/amd/picasso/config.c new file mode 100644 index 0000000000..5d52e7affa --- /dev/null +++ b/src/soc/amd/picasso/config.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include "chip.h" + +const struct soc_amd_common_config *soc_get_common_config() +{ + const struct soc_amd_picasso_config *cfg = config_of_soc(); + return &cfg->common_config; +} -- cgit v1.2.3