From 02db6b40499a1c970f32074bcff5b7b65bec4fa3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 8 Apr 2022 17:12:13 +0200 Subject: mb/msi/ms7d25: Add correct memory init configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with 4x KINGSTON KF3600C17D4/8GX DIMMs. TEST=Include the microcode from vendor firmware and FSP blob from Intel R&DC. Boot the platform and see ramstage is executing. Signed-off-by: Michał Żygowski Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63503 Tested-by: build bot (Jenkins) Reviewed-by: Krystian Hebel --- src/mainboard/msi/ms7d25/romstage_fsp_params.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index 210af0576c..60f2371dfb 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -9,18 +9,13 @@ static const struct mb_cfg ddr4_mem_config = { .type = MEM_TYPE_DDR4, - .rcomp = { - /* Baseboard uses only 100ohm Rcomp resistor FIXME */ - .resistor = 100, - - /* Baseboard Rcomp target values FIXME */ - .targets = { 50, 20, 25, 25, 25 }, - }, + /* According to DOC #573387 rcomp values no longer have to be provided */ + /* DDR DIMM configuration does not need to set DQ/DQS maps */ .UserBd = BOARD_TYPE_DESKTOP_2DPC, /* FIXME */ .ddr_config = { - .dq_pins_interleaved = false, /* FIXME */ + .dq_pins_interleaved = true, }, }; -- cgit v1.2.3