From 01c190e382ae35c990e5668b20014a626681c9ce Mon Sep 17 00:00:00 2001 From: Subrata Banik <subratabanik@google.com> Date: Tue, 6 Dec 2022 20:44:25 +0530 Subject: mb/google/rex: Update USB2-C1 mapping This patch updates the USB2-C1 mapping from USB2 Port 4 to USB2 Port 1 as per latest Rex schematics dated 12/06/2022. TEST=Hardward awaited. Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70426 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> --- src/mainboard/google/rex/variants/rex0/overridetree.cb | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 4724605314..0c83341acb 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -31,8 +31,8 @@ end chip soc/intel/meteorlake + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 @@ -172,18 +172,18 @@ chip soc/intel/meteorlake chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" - device ref usb2_port2 on end + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref usb2_port4 on end + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 WWAN"" @@ -536,7 +536,7 @@ chip soc/intel/meteorlake device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - use usb2_port4 as usb2_port + use usb2_port1 as usb2_port use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end -- cgit v1.2.3