From 018a9af4d5867f21ec4a16d606098812ffb8d0b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Tue, 11 Dec 2018 15:16:30 +0100 Subject: arch/riscv: Don't hardcode CSR numbers anymore MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They are hopefully stable enough by now. TEST=Building with for emulation/spike-riscv with BUILD_TIMELESS, with and without this patch, results in the same coreboot.rom. Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/c/30164 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Philipp Hug --- src/arch/riscv/virtual_memory.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index d9bae2aac3..0061847c01 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -59,11 +59,6 @@ void mstatus_init(void) set_csr(medeleg, delegate); } - // Enable all user/supervisor-mode counters using - // v1.10 register addresses. - // They moved from the earlier spec. - // Until we trust our toolchain use the hardcoded constants. - // These were in flux and people who get the older toolchain - // will have difficult-to-debug failures. - write_csr(/*mcounteren*/0x306, 7); + // Enable all user/supervisor-mode counters + write_csr(mcounteren, 7); } -- cgit v1.2.3