From 015b3dc124a448e20ea3b3f98decfae5dac26827 Mon Sep 17 00:00:00 2001 From: Praveen hodagatta pranesh Date: Fri, 23 Nov 2018 17:41:46 +0800 Subject: soc/intel/skylake: Add device settings for PL4 power limit PL4 is a preemptive CPU package peak power limit,it will never be exceeded. Power is preemptively lowered before limit is reached. This change provides option in devicetree and feeds FSP PowerLimit4 UPD for power limit purpose. Signed-off-by: Praveen hodagatta pranesh Change-Id: I64b5a029104a102e5741e8b37c7992f2693180e8 Reviewed-on: https://review.coreboot.org/c/29808 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/chip.h | 3 +++ src/soc/intel/skylake/chip_fsp20.c | 1 + 2 files changed, 4 insertions(+) (limited to 'src') diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b1ffcb2fe8..7014a2e60b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -97,6 +97,9 @@ struct soc_intel_skylake_config { /* TCC activation offset */ int tcc_offset; + /* Package PL4 power limit in Watts */ + u32 PowerLimit4; + /* PL2 Override value in Watts */ u32 tdp_pl2_override; /* PL1 Override value in Watts */ diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 8a78348794..18c2aef676 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -369,6 +369,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; + tconfig->PowerLimit4 = config->PowerLimit4; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree -- cgit v1.2.3