From f226a4d41db5ab314200206e7cb8731f022a14a6 Mon Sep 17 00:00:00 2001 From: York Yang Date: Tue, 7 Jul 2015 11:09:02 -0700 Subject: intel/fsp_baytrail: Support Baytrail FSP Gold4 release Baytrail FSP Gold4 release added 5 PCD options. Update UPD_DATA_REGION structure to include these new PCD options and initialized the setting when given in devicetree.cb. Change-Id: Ic343e79479464972455e42f9352b3bb116c6f80f Signed-off-by: York Yang Reviewed-on: http://review.coreboot.org/10838 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/vendorcode') diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h index 02de3cbd1c..76f7ce7b8a 100755 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h @@ -97,7 +97,12 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdSccEnablePciMode; /* Offset 0x004D */ UINT8 IgdRenderStandby; /* Offset 0x004E */ UINT8 TxeUmaEnable; /* Offset 0x004F */ - UINT8 UnusedUpdSpace1[160]; /* Offset 0x0050 */ + UINT8 PcdOsSelection; /* Offset 0x0050 */ + UINT8 PcdEMMC45DDR50Enabled; /* Offset 0x0051 */ + UINT8 PcdEMMC45HS200Enabled; /* Offset 0x0052 */ + UINT8 PcdEMMC45RetuneTimerValue; /* Offset 0x0053 */ + UINT8 PcdEnableIgd; /* Offset 0x0054 */ + UINT8 UnusedUpdSpace1[155]; /* Offset 0x0055 */ MEMORY_DOWN_DATA PcdMemoryParameters; /* Offset 0x00F0 */ UINT16 PcdRegionTerminator; /* Offset 0x0100 */ } UPD_DATA_REGION; -- cgit v1.2.3