From cbc609957fb8feedc7eb7795a3324cf364c178f1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 8 Sep 2021 07:45:23 +0200 Subject: soc/intel/xeon_sp/cpx: Rename FSP UPDs using CPP coreboot expects different names for FSP UPDs so use some CPP to make it happy. Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'src/vendorcode') diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 8abff098ae..8533c364c7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -35,14 +35,6 @@ are permitted provided that the following conditions are met: #include -/* - * Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG. - * Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel - * is that they will converge to use FSPM_CONFIG over time. So both will - * co-exist for some time. Today coreboot common code expects FSP_M_CONFIG. - */ -#define FSP_M_CONFIG FSPM_CONFIG - #define SPEED_REC_96GT 0 #define SPEED_REC_104GT 1 #define ADAPTIVE_CTLE 0x3f -- cgit v1.2.3