From c2059fa72a654f8927f05bcecb4d98ef856c9b64 Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Wed, 26 Apr 2023 19:27:54 +0800 Subject: soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_ms Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to match the eDP sequence timing in milliseconds. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787 Reviewed-by: Matt DeVillier Reviewed-by: Jason Glenesk Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/vendorcode/amd/fsp/mendocino/FspmUpd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/vendorcode') diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h index 391c64b822..b3d6dc39d9 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h @@ -101,8 +101,8 @@ typedef struct __packed { /** Offset 0x04E1**/ uint32_t vrm_maximum_current_limit_mA; /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; /** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1; - /** Offset 0x04E9**/ uint8_t pwr_on_vary_bl_to_blon; - /** Offset 0x04EA**/ uint8_t UnusedUpdSpace2[277]; + /** Offset 0x04EA**/ uint8_t edp_panel_t8_ms; + /** Offset 0x04EB**/ uint8_t UnusedUpdSpace2[277]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; -- cgit v1.2.3