From ad12b4f4404f7c3473dcf85960efe3f8a016f22b Mon Sep 17 00:00:00 2001 From: "Chris.Wang" Date: Wed, 28 Dec 2022 17:07:48 +0800 Subject: soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimization Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger Reviewed-by: Jason Glenesk Tested-by: build bot (Jenkins) --- src/vendorcode/amd/fsp/mendocino/FspmUpd.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/vendorcode') diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h index 7639ab1967..9f68101c4d 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h @@ -96,7 +96,8 @@ typedef struct __packed { /** Offset 0x04D7**/ uint8_t UnusedUpdSpace1; /* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */ /** Offset 0x04D8**/ uint32_t usb_phy_ptr; - /** Offset 0x04DC**/ uint8_t UnusedUpdSpace2[292]; + /** Offset 0x04DC**/ uint8_t dxio_tx_vboost_enable; + /** Offset 0x04DD**/ uint8_t UnusedUpdSpace2[291]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; -- cgit v1.2.3