From 95d4ee8168a67648e0b4a6ff855865db8c0a5420 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 19 Jun 2021 00:00:10 +0200 Subject: vc/amd/fsp/cezanne/FspmUpd: add hda_enable UPD This UPD to enable/disable the non-graphics HD audio controller was added in FSP build version 1.0.3.1, so sync the header file in coreboot with this. Signed-off-by: Felix Held Change-Id: I15eee45dc5d12a420eb688eaa5879c92b6d1b2c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55679 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/vendorcode') diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index efb516f5e0..7cb788e175 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -74,7 +74,8 @@ typedef struct __packed { /** Offset 0x041E**/ uint8_t enable_nb_azalia; /** Offset 0x041F**/ uint8_t audio_io_ctl; /** Offset 0x0420**/ uint8_t pdm_mic_selection; - /** Offset 0x0421**/ uint8_t nbio_reserved[32]; + /** Offset 0x0421**/ uint8_t hda_enable; + /** Offset 0x0422**/ uint8_t nbio_reserved[31]; /** Offset 0x0441**/ uint32_t emmc0_mode; /** Offset 0x0445**/ uint16_t emmc0_init_khz_preset; /** Offset 0x0447**/ uint8_t emmc0_sdr104_hs400_driver_strength; -- cgit v1.2.3