From 8c0cb8ae3b3945a1f61a8eab3b9f41af9a0bb10b Mon Sep 17 00:00:00 2001
From: Idwer Vollering <vidwer@gmail.com>
Date: Fri, 6 Dec 2013 22:02:47 +0000
Subject: Correct file permissions.

Some files have incorrect/odd permissions,
correct them: remove unnecessary +x flags.

Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4490
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
---
 src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc       | 0
 src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm                     | 0
 src/vendorcode/amd/agesa/f10/Legacy/agesa.inc                             | 0
 src/vendorcode/amd/agesa/f10/Legacy/amd.inc                               | 0
 src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc                          | 0
 src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm                        | 0
 src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm                        | 0
 src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm                        | 0
 src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm                         | 0
 src/vendorcode/amd/agesa/f10/Makefile.inc                                 | 0
 src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm      | 0
 src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm      | 0
 src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm                          | 0
 src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm                | 0
 src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm                | 0
 src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm                         | 0
 src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm                    | 0
 src/vendorcode/amd/agesa/f10/cpcar.inc                                    | 0
 src/vendorcode/amd/agesa/f10/cpcarmac.inc                                 | 0
 src/vendorcode/amd/agesa/f10/gcccar.inc                                   | 0
 src/vendorcode/amd/agesa/f12/Legacy/PlatformMemoryConfiguration.inc       | 0
 src/vendorcode/amd/agesa/f12/Legacy/Proc/arch2008.asm                     | 0
 src/vendorcode/amd/agesa/f12/Legacy/agesa.inc                             | 0
 src/vendorcode/amd/agesa/f12/Legacy/amd.inc                               | 0
 src/vendorcode/amd/agesa/f12/Legacy/bridge32.inc                          | 0
 src/vendorcode/amd/agesa/f12/Makefile.inc                                 | 0
 .../amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl       | 0
 .../amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl         | 0
 .../amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl      | 0
 .../amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl         | 0
 .../amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl        | 0
 src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl      | 0
 src/vendorcode/amd/agesa/f12/cpcar.inc                                    | 0
 src/vendorcode/amd/agesa/f12/cpcarmac.inc                                 | 0
 src/vendorcode/amd/agesa/f12/gcccar.inc                                   | 0
 src/vendorcode/amd/cimx/sb900/Makefile.inc                                | 0
 src/vendorcode/amd/cimx/sb900/OEM.h                                       | 0
 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspapi.h               | 0
 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspffs.h               | 0
 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspfv.h                | 0
 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fsphob.h               | 0
 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspinfoheader.h        | 0
 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspplatform.h          | 0
 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fsptypes.h             | 0
 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/mem_config.h           | 0
 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/peifsp.h               | 0
 46 files changed, 0 insertions(+), 0 deletions(-)
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Legacy/agesa.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Legacy/amd.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Makefile.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/cpcar.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/cpcarmac.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f10/gcccar.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Legacy/PlatformMemoryConfiguration.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Legacy/Proc/arch2008.asm
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Legacy/agesa.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Legacy/amd.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Legacy/bridge32.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Makefile.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/cpcar.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/cpcarmac.inc
 mode change 100755 => 100644 src/vendorcode/amd/agesa/f12/gcccar.inc
 mode change 100755 => 100644 src/vendorcode/amd/cimx/sb900/Makefile.inc
 mode change 100755 => 100644 src/vendorcode/amd/cimx/sb900/OEM.h
 mode change 100755 => 100644 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspapi.h
 mode change 100755 => 100644 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspffs.h
 mode change 100755 => 100644 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspfv.h
 mode change 100755 => 100644 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fsphob.h
 mode change 100755 => 100644 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspinfoheader.h
 mode change 100755 => 100644 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspplatform.h
 mode change 100755 => 100644 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fsptypes.h
 mode change 100755 => 100644 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/mem_config.h
 mode change 100755 => 100644 src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/peifsp.h

(limited to 'src/vendorcode')

diff --git a/src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f10/Legacy/agesa.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/amd.inc b/src/vendorcode/amd/agesa/f10/Legacy/amd.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm b/src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm b/src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm b/src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm b/src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Makefile.inc b/src/vendorcode/amd/agesa/f10/Makefile.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/cpcar.inc b/src/vendorcode/amd/agesa/f10/cpcar.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/cpcarmac.inc b/src/vendorcode/amd/agesa/f10/cpcarmac.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f12/Legacy/PlatformMemoryConfiguration.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f12/Legacy/Proc/arch2008.asm
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f12/Legacy/agesa.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/amd.inc b/src/vendorcode/amd/agesa/f12/Legacy/amd.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/f12/Legacy/bridge32.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/cpcar.inc b/src/vendorcode/amd/agesa/f12/cpcar.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/cpcarmac.inc b/src/vendorcode/amd/agesa/f12/cpcarmac.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/cimx/sb900/Makefile.inc b/src/vendorcode/amd/cimx/sb900/Makefile.inc
old mode 100755
new mode 100644
diff --git a/src/vendorcode/amd/cimx/sb900/OEM.h b/src/vendorcode/amd/cimx/sb900/OEM.h
old mode 100755
new mode 100644
diff --git a/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspapi.h b/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspapi.h
old mode 100755
new mode 100644
diff --git a/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspffs.h b/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspffs.h
old mode 100755
new mode 100644
diff --git a/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspfv.h b/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspfv.h
old mode 100755
new mode 100644
diff --git a/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fsphob.h b/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fsphob.h
old mode 100755
new mode 100644
diff --git a/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspinfoheader.h b/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspinfoheader.h
old mode 100755
new mode 100644
diff --git a/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspplatform.h b/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fspplatform.h
old mode 100755
new mode 100644
diff --git a/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fsptypes.h b/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/fsptypes.h
old mode 100755
new mode 100644
diff --git a/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/mem_config.h b/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/mem_config.h
old mode 100755
new mode 100644
diff --git a/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/peifsp.h b/src/vendorcode/intel/fsp/ivybridge_bd82x6x/include/peifsp.h
old mode 100755
new mode 100644
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