From c8d3b9160a3c33a1bcdd2c417db6fc402ac82c02 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 12 May 2021 16:39:09 +0200 Subject: vc/mediatek: Align code indent with code flow gcc 11 suspects missing braces here, but it seems the line should be executed in all cases, so unindent it. Change-Id: I7b8cacd48e86284c5145c4e8ffb6add75a743108 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/54096 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber Reviewed-by: Angel Pons Reviewed-by: Yu-Ping Wu --- src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/vendorcode/mediatek') diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c index cd897ed917..ffdf3d6850 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c @@ -3097,8 +3097,8 @@ void TXPICGSetting(DRAMC_CTX_T * p) else u2COMB_TX_SEL[1] = (u4DQ_OEN_final > u2Shift_DQ_Div[1])? ((u4DQ_OEN_final - u2Shift_DQ_Div[1]) >> u1Div_ratio): 0; - vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0) - | P_Fld(u2COMB_TX_SEL[1], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0) + | P_Fld(u2COMB_TX_SEL[1], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1)); } vSetRank(p, u1Rank_bak); } -- cgit v1.2.3