From ff9afb3d8ecdfd03933effc583593a7c9b73e48e Mon Sep 17 00:00:00 2001 From: York Yang Date: Tue, 7 Jul 2015 10:07:51 -0700 Subject: intel/fsp_baytrail: Remove PcdEnableLan option Bay Trail SOCs do not integrate LAN controller hence Baytrail FSP has no LAN control function. Remove PcdEnableLan option from UPD_DATA_REGION structure. Change-Id: I9b4ec9d72c8c60b928a6d9755e94203fb90b658f Signed-off-by: York Yang Reviewed-on: http://review.coreboot.org/10837 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) mode change 100644 => 100755 src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h (limited to 'src/vendorcode/intel') diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h old mode 100644 new mode 100755 index b001cdb28c..02de3cbd1c --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h @@ -1,6 +1,6 @@ /** -Copyright (C) 2013-2014 Intel Corporation +Copyright (C) 2013-2015 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -67,7 +67,7 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdEnableHsuart0; /* Offset 0x0029 */ UINT8 PcdEnableHsuart1; /* Offset 0x002A */ UINT8 PcdEnableSpi; /* Offset 0x002B */ - UINT8 PcdEnableLan; /* Offset 0x002C */ + UINT8 ReservedUpdSpace1; /* Offset 0x002C */ UINT8 PcdEnableSata; /* Offset 0x002D */ UINT8 PcdSataMode; /* Offset 0x002E */ UINT8 PcdEnableAzalia; /* Offset 0x002F */ -- cgit v1.2.3