From fe17a7d4d420763ef387e84256eaed0373c25725 Mon Sep 17 00:00:00 2001
From: Jonathan Zhang <jonzhang@fb.com>
Date: Mon, 8 Aug 2022 15:38:54 -0700
Subject: soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions

Intel FSPs of XEON server platforms define FSPX_CONFIG
instead of FSP_X_CONFIG, which is expected by coreboot.

Re-define in the common code.

Update coreboot code to use FSP_X_CONFIG consistently.

Tested=On OCP Delta Lake, boot up OS successfully.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>

Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/vendorcode/intel')

diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
index 0de0fa1ee8..066c2aef24 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
@@ -553,7 +553,7 @@ typedef struct {
 /** Offset 0x01E0
 **/
 	UINT8                     ReservedMemoryInitUpd[16];
-} FSP_M_CONFIG;
+} FSPM_CONFIG;
 
 /** Fsp M UPD Configuration
 **/
-- 
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