From c60fd46420ecc5715e656a28ab1e4e1d234d21b5 Mon Sep 17 00:00:00 2001 From: "Deomid \"rojer\" Ryabkov" Date: Tue, 16 Mar 2021 19:51:11 +0000 Subject: vendorcode/intel/FSP2_0/CPX-SP: Declare struct RC_VERSION non-packed It is a bug acknowledged by Intel (IPS case 00600003) that has been fixed for SRP but won't be fixed for CPX. This fixes field offsets for fields that follow SYSTEM_STATUS.RcVersion Change-Id: I5248734e2f086d39bb75b7b1359e60dfd8704200 Signed-off-by: Deomid "rojer" Ryabkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/51545 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'src/vendorcode/intel') diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 3c6f9a7408..f36b56806d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -56,6 +56,18 @@ are permitted provided that the following conditions are met: #define MAX_LOGIC_IIO_STACK (MAX_IIO_STACK+2) +// RC version number structure. +typedef struct { + uint8_t Major; + uint8_t Minor; + uint8_t Revision; + uint16_t BuildNumber; +} RC_VERSION; +// Note: the struct is not packed for a reason: it is not packed in FSP code. +// It is a bug acknowledged by Intel (IPS case 00600003) that has been fixed for SRP +// but won't be fixed for CPX. +_Static_assert(sizeof(RC_VERSION) == 6, "Incorrect size of struct 'RC_VERSION'"); + #pragma pack(1) //--------------------------------------------------------------------------------------// @@ -77,16 +89,6 @@ typedef enum { TYPE_MAX_MMIO_BAR } MMIO_BARS; -/// -/// RC version number structure. -/// -typedef struct { - uint8_t Major; - uint8_t Minor; - uint8_t Revision; - uint16_t BuildNumber; -} RC_VERSION; - /** IIO PCIe Ports **/ -- cgit v1.2.3