From 87f67bc69912c8725769481d70352eef894baa3a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 22 Sep 2017 00:05:28 -0500 Subject: soc/intel/skylake: add acoustic noise mitigation params for FSP 1.1 Adapted from Chromium commit d6655eb [Skylake: create UPD Interface for acoustic noise tuning] Add FSP 1.1 params needed for acoustic mitigation on google/caroline (to be upstreamed in a subsequent commit). TEST: build/boot google/caroline Change-Id: Ifb36ecef8c1735c63a5322d952929e9c34cddfb9 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/22524 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- .../intel/fsp/fsp1_1/skylake/FspUpdVpd.h | 26 +++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'src/vendorcode/intel/fsp') diff --git a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h index 45f2099a38..32b926a6d4 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -950,14 +950,34 @@ typedef struct { UINT8 Early8254ClockGatingEnable; /** Offset 0x03E5 - Enable VR specific mailbox command - When set, an extra VR mailbox command specifically for the MPS IMPV8 VR will be sent. This for FSP only. 0 - Don't Send, 1 - Send + VR specific mailbox commands, 000b: no VR specific command sent, 001b: A VR mailbox command specifically for the MPS IMPV8 VR will be sent, 010b: VR specific command sent for PS4 exit issue, 011b: VR specific command sent for both MPS IMPV8 & PS4 exit issue. $EN_DIS **/ UINT8 SendVrMbxCmd; /** Offset 0x03E6 **/ - UINT8 ReservedSiliconInitUpd[20]; + UINT8 AcousticNoiseMitigation; + +/** Offset 0x03E7 +**/ + UINT8 SlowSlewRateForIa; + +/** Offset 0x03E8 +**/ + UINT8 SlowSlewRateForGt; + +/** Offset 0x03E9 +**/ + UINT8 SlowSlewRateForSa; + +/** Offset 0x03EA +**/ + UINT8 FastPkgCRampDisable; + +/** Offset 0x03EB +**/ + UINT8 ReservedSiliconInitUpd[15]; } SILICON_INIT_UPD; #define FSP_UPD_SIGNATURE 0x244450554C4B5324 /* '$SKLUPD$' */ -- cgit v1.2.3