From 5f1786fc9cc543845a070c61d4f2dec2ae39c691 Mon Sep 17 00:00:00 2001
From: Ronak Kanabar <ronak.kanabar@intel.com>
Date: Wed, 4 Sep 2019 16:20:26 +0530
Subject: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344
Cq-Depend: chrome-internal:1759167
Change-Id: Ib5784eb8c0f7c6e56950dad5c8254e00aa73cef4
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35245
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
.../intel/fsp/fsp2_0/cometlake/FspmUpd.h | 137 +++++++++--
.../intel/fsp/fsp2_0/cometlake/FspsUpd.h | 251 ++++++++++++++++-----
2 files changed, 308 insertions(+), 80 deletions(-)
(limited to 'src/vendorcode/intel/fsp')
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
index b623ba0b65..962463e425 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
@@ -37,19 +37,19 @@ are permitted provided that the following conditions are met:
#pragma pack(1)
-
-#include <MemInfoHob.h>
-
-///
-/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
-///
-typedef struct {
- UINT8 Revision; ///< Chipset Init Info Revision
- UINT8 Rsvd[3]; ///< Reserved
- UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
- UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
-} CHIPSET_INIT_INFO;
-
+
+#include <MemInfoHob.h>
+
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+ UINT8 Revision; ///< Chipset Init Info Revision
+ UINT8 Rsvd[3]; ///< Reserved
+ UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
+ UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
/** Fsp M Configuration
**/
@@ -1464,11 +1464,96 @@ typedef struct {
**/
UINT8 SerialIoUartDebugDataBits;
-/** Offset 0x0457 - ReservedPchPreMem
+/** Offset 0x0457 - Enable HD Audio DSP
+ Enable/disable HD Audio DSP feature.
+ $EN_DIS
+**/
+ UINT8 PchHdaDspEnable;
+
+/** Offset 0x0458 - VC Type
+ Virtual Channel Type Select: 0: VC0, 1: VC1.
+ 0: VC0, 1: VC1
+**/
+ UINT8 PchHdaVcType;
+
+/** Offset 0x0459 - Universal Audio Architecture compliance for DSP enabled system
+ 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
+ driver or SST driver supported).
+ $EN_DIS
+**/
+ UINT8 PchHdaDspUaaCompliance;
+
+/** Offset 0x045A - Enable HD Audio Link
+ Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkHda;
+
+/** Offset 0x045B - Enable HD Audio DMIC0 Link
+ Deprecated.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkDmic0;
+
+/** Offset 0x045C - Enable HD Audio DMIC1 Link
+ Deprecated.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkDmic1;
+
+/** Offset 0x045D - Enable HD Audio SSP0 Link
+ Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSsp0;
+
+/** Offset 0x045E - Enable HD Audio SSP1 Link
+ Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSsp1;
+
+/** Offset 0x045F - Enable HD Audio SSP2 Link
+ Enable/disable HD Audio SSP2/I2S link.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSsp2;
+
+/** Offset 0x0460 - Enable HD Audio SoundWire#1 Link
+ Enable/disable HD Audio SNDW1 link. Muxed with HDA.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSndw1;
+
+/** Offset 0x0461 - Enable HD Audio SoundWire#2 Link
+ Enable/disable HD Audio SNDW2 link. Muxed with SSP1.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSndw2;
+
+/** Offset 0x0462 - Enable HD Audio SoundWire#3 Link
+ Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSndw3;
+
+/** Offset 0x0463 - Enable HD Audio SoundWire#4 Link
+ Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSndw4;
+
+/** Offset 0x0464 - Soundwire Clock Buffer GPIO RCOMP Setting
+ 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.
+ $EN_DIS
+**/
+ UINT8 PchHdaSndwBufferRcomp;
+
+/** Offset 0x0465 - ReservedPchPreMem
Reserved for Pch Pre-Mem
$EN_DIS
**/
- UINT8 ReservedPchPreMem[16];
+ UINT8 ReservedPchPreMem[2];
/** Offset 0x0467 - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
@@ -2284,7 +2369,7 @@ typedef struct {
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
- Error Warnings and Info, 5:Load Error Warnings Info and Verbose
+ Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
**/
UINT8 PcdSerialDebugLevel;
@@ -2390,13 +2475,27 @@ typedef struct {
**/
UINT8 Ddr4SkipRefreshEn;
-/** Offset 0x0510
+/** Offset 0x0510 - SerialDebugMrcLevel
+ MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 SerialDebugMrcLevel;
+
+/** Offset 0x0511 - Enable HD Audio Sndw Link IO Control
+ deprecated
+**/
+ UINT8 PchHdaSndwLinkIoControlEnabled[4];
+
+/** Offset 0x0515
**/
UINT8 UnusedUpdSpace8[2];
-/** Offset 0x0512
+/** Offset 0x0517
**/
- UINT8 ReservedFspmUpd[6];
+ UINT8 ReservedFspmUpd[1];
} FSP_M_CONFIG;
/** Fsp M Test Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h
index 49da429b47..0df3063e5c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h
@@ -37,49 +37,49 @@ are permitted provided that the following conditions are met:
#pragma pack(1)
-
-///
-/// Azalia Header structure
-///
-typedef struct {
- UINT16 VendorId; ///< Codec Vendor ID
- UINT16 DeviceId; ///< Codec Device ID
- UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
- UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
- UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
- UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
-} AZALIA_HEADER;
-
-///
-/// Audio Azalia Verb Table structure
-///
-typedef struct {
- AZALIA_HEADER Header; ///< AZALIA PCH header
- UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
-} AUDIO_AZALIA_VERB_TABLE;
-
-///
-/// Refer to the definition of PCH_INT_PIN
-///
-typedef enum {
- SiPchNoInt, ///< No Interrupt Pin
- SiPchIntA,
- SiPchIntB,
- SiPchIntC,
- SiPchIntD
-} SI_PCH_INT_PIN;
-///
-/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
-///
-typedef struct {
- UINT8 Device; ///< Device number
- UINT8 Function; ///< Device function
- UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
- UINT8 Irq; ///< IRQ to be set for device.
-} SI_PCH_DEVICE_INTERRUPT_CONFIG;
-
-#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
-
+
+///
+/// Azalia Header structure
+///
+typedef struct {
+ UINT16 VendorId; ///< Codec Vendor ID
+ UINT16 DeviceId; ///< Codec Device ID
+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
+ UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
+ UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
+ UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+ AZALIA_HEADER Header; ///< AZALIA PCH header
+ UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+ SiPchNoInt, ///< No Interrupt Pin
+ SiPchIntA,
+ SiPchIntB,
+ SiPchIntC,
+ SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
+
/** Fsp S Configuration
**/
@@ -1319,8 +1319,8 @@ typedef struct {
UINT8 PmcModPhySusPgEnable;
/** Offset 0x036F - SlpS0WithGbeSupport
- Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping
- CPU and 1 for all other CPUs. 0: Disable, 1: Enable
+ Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping
+ CPU and 1 for PCH-H Series. 0: Disable, 1: Enable
$EN_DIS
**/
UINT8 SlpS0WithGbeSupport;
@@ -2053,23 +2053,23 @@ typedef struct {
UINT8 PchScsEmmcHs400TuningRequired;
/** Offset 0x06A0 - Set HS400 Tuning Data Valid
- Set if HS400 Tuning Data Valid.
+ Deprecated
$EN_DIS
**/
UINT8 PchScsEmmcHs400DllDataValid;
/** Offset 0x06A1 - Rx Strobe Delay Control
- Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
+ Deprecated
**/
UINT8 PchScsEmmcHs400RxStrobeDll1;
/** Offset 0x06A2 - Tx Data Delay Control
- Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
+ Deprecated
**/
UINT8 PchScsEmmcHs400TxDataDll;
/** Offset 0x06A3 - I/O Driver Strength
- Deprecated.
+ Deprecated
0:33 Ohm, 1:40 Ohm, 2:50 Ohm
**/
UINT8 PchScsEmmcHs400DriverStrength;
@@ -2440,11 +2440,30 @@ typedef struct {
**/
UINT8 ScsSdCardWpPinEnabled;
-/** Offset 0x074F - ReservedPchPostMem
+/** Offset 0x074F - Set SATA DEVSLP GPIO Reset Config
+ Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset,
+ 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte
+ for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ UINT8 SataPortsDevSlpResetConfig[8];
+
+/** Offset 0x0757 - Flash Configuration Lock Down
+ Enable/disable flash lock down. If platform decides to skip this programming, it
+ must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post.
+ $EN_DIS
+**/
+ UINT8 SpiFlashCfgLockDown;
+
+/** Offset 0x0758 - Enable HD Audio Sndw Link IO Control
+ 0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled
+**/
+ UINT8 PchHdaSndwLinkIoControlEnabled[4];
+
+/** Offset 0x075C - ReservedPchPostMem
Reserved for Pch Post-Mem
$EN_DIS
**/
- UINT8 ReservedPchPostMem[16];
+ UINT8 ReservedPchPostMem[3];
/** Offset 0x075F
**/
@@ -3326,11 +3345,51 @@ typedef struct {
**/
UINT8 C3StateUnDemotion;
-/** Offset 0x08BF - ReservedCpuPostMemTest
+/** Offset 0x08BF - Ratio Limit Num Core 0
+ Ratio Limit Num Core0: This register defines the active core ranges for each frequency point
+**/
+ UINT8 RatioLimitNumCore0;
+
+/** Offset 0x08C0 - Ratio Limit Num Core 1
+ Ratio Limit Num Core1: This register defines the active core ranges for each frequency point
+**/
+ UINT8 RatioLimitNumCore1;
+
+/** Offset 0x08C1 - Ratio Limit Num Core 2
+ Ratio Limit Num Core2: This register defines the active core ranges for each frequency point
+**/
+ UINT8 RatioLimitNumCore2;
+
+/** Offset 0x08C2 - Ratio Limit Core 3
+ Ratio Limit Num Core3: This register defines the active core ranges for each frequency point
+**/
+ UINT8 RatioLimitNumCore3;
+
+/** Offset 0x08C3 - Ratio Limit Num Core 4
+ Ratio Limit Num Core4: This register defines the active core ranges for each frequency point
+**/
+ UINT8 RatioLimitNumCore4;
+
+/** Offset 0x08C4 - Ratio Limit Num Core 5
+ Ratio Limit Num Core5: This register defines the active core ranges for each frequency point
+**/
+ UINT8 RatioLimitNumCore5;
+
+/** Offset 0x08C5 - Ratio Limit Num Core 6
+ Ratio Limit Num Core6: This register defines the active core ranges for each frequency point
+**/
+ UINT8 RatioLimitNumCore6;
+
+/** Offset 0x08C6 - Ratio Limit Num Core 7
+ Ratio Limit Num Core7: This register defines the active core ranges for each frequency point
+**/
+ UINT8 RatioLimitNumCore7;
+
+/** Offset 0x08C7 - ReservedCpuPostMemTest
Reserved for CPU Post-Mem Test
$EN_DIS
**/
- UINT8 ReservedCpuPostMemTest[19];
+ UINT8 ReservedCpuPostMemTest[11];
/** Offset 0x08D2 - SgxSinitDataFromTpm
SgxSinitDataFromTpm default values
@@ -3338,8 +3397,7 @@ typedef struct {
UINT8 SgxSinitDataFromTpm;
/** Offset 0x08D3 - End of Post message
- Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
- EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI
+ Deprecated
0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
**/
UINT8 EndOfPostMessage;
@@ -3488,11 +3546,82 @@ typedef struct {
**/
UINT8 MctpBroadcastCycle;
-/** Offset 0x0A8A
+/** Offset 0x0A8A - Use DLL values from policy
+ Set if FSP should use HS400 DLL values from policy
+ $EN_DIS
+**/
+ UINT8 EmmcUseCustomDlls;
+
+/** Offset 0x0A8B
+**/
+ UINT8 UnusedUpdSpace29;
+
+/** Offset 0x0A8C - Emmc Tx CMD Delay control register value
+ Please see Tx CMD Delay Control register definition for help
+**/
+ UINT32 EmmcTxCmdDelayRegValue;
+
+/** Offset 0x0A90 - Emmc Tx DATA Delay control 1 register value
+ Please see Tx DATA Delay control 1 register definition for help
+**/
+ UINT32 EmmcTxDataDelay1RegValue;
+
+/** Offset 0x0A94 - Emmc Tx DATA Delay control 2 register value
+ Please see Tx DATA Delay control 2 register definition for help
+**/
+ UINT32 EmmcTxDataDelay2RegValue;
+
+/** Offset 0x0A98 - Emmc Rx CMD + DATA Delay control 1 register value
+ Please see Rx CMD + DATA Delay control 1 register definition for help
+**/
+ UINT32 EmmcRxCmdDataDelay1RegValue;
+
+/** Offset 0x0A9C - Emmc Rx CMD + DATA Delay control 2 register value
+ Please see Rx CMD + DATA Delay control 2 register definition for help
+**/
+ UINT32 EmmcRxCmdDataDelay2RegValue;
+
+/** Offset 0x0AA0 - Emmc Rx Strobe Delay control register value
+ Please see Rx Strobe Delay control register definition for help
+**/
+ UINT32 EmmcRxStrobeDelayRegValue;
+
+/** Offset 0x0AA4 - Use tuned DLL values from policy
+ Set if FSP should use HS400 DLL values from policy
+ $EN_DIS
+**/
+ UINT8 SdCardUseCustomDlls;
+
+/** Offset 0x0AA5
+**/
+ UINT8 UnusedUpdSpace30[3];
+
+/** Offset 0x0AA8 - SdCard Tx CMD Delay control register value
+ Please see Tx CMD Delay Control register definition for help
+**/
+ UINT32 SdCardTxCmdDelayRegValue;
+
+/** Offset 0x0AAC - SdCard Tx DATA Delay control 1 register value
+ Please see Tx DATA Delay control 1 register definition for help
+**/
+ UINT32 SdCardTxDataDelay1RegValue;
+
+/** Offset 0x0AB0 - SdCard Tx DATA Delay control 2 register value
+ Please see Tx DATA Delay control 2 register definition for help
+**/
+ UINT32 SdCardTxDataDelay2RegValue;
+
+/** Offset 0x0AB4 - SdCard Rx CMD + DATA Delay control 1 register value
+ Please see Rx CMD + DATA Delay control 1 register definition for help
+**/
+ UINT32 SdCardRxCmdDataDelay1RegValue;
+
+/** Offset 0x0AB8 - SdCard Rx CMD + DATA Delay control 2 register value
+ Please see Rx CMD + DATA Delay control 2 register definition for help
**/
- UINT8 UnusedUpdSpace29[2];
+ UINT32 SdCardRxCmdDataDelay2RegValue;
-/** Offset 0x0A8C
+/** Offset 0x0ABC
**/
UINT8 ReservedFspsTestUpd[12];
} FSP_S_TEST_CONFIG;
@@ -3513,11 +3642,11 @@ typedef struct {
**/
FSP_S_TEST_CONFIG FspsTestConfig;
-/** Offset 0x0A98
+/** Offset 0x0AC8
**/
- UINT8 UnusedUpdSpace30[6];
+ UINT8 UnusedUpdSpace31[6];
-/** Offset 0x0A9E
+/** Offset 0x0ACE
**/
UINT16 UpdTerminator;
} FSPS_UPD;
--
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