From 5797b2eb05ec46d877a2ae6b5e0c517ae54a6fe8 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Fri, 19 Oct 2018 16:57:27 +0200 Subject: src: Typo fix (cosmetic) Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/29196 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h') diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h index 12c6e4413c..d03a844037 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h @@ -2978,8 +2978,8 @@ typedef struct { **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. +/** Offset 0x0899 - Set HW P-State Interrupts Enabled for MISC_PWR_MGMT + Set HW P-State Interrupts Enabled for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -- cgit v1.2.3