From 954f3882f1ea8512de9a5a6a38569c36bffae405 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 4 Apr 2014 13:23:41 -0600 Subject: Add the Bay Trail FSP include & srx directories MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are the .h and .c files from Intel that support interaction with the FSP. These have been modified from the FSP distribution only to strip trailing whitespace. Intel® Atom™ processor E3800 product family (formerly Bay Trail) "Intel® Firmware Support Package (Intel® FSP) provides key programming information for initializing Intel® silicon and can be easily integrated into a boot loader of the developer’s choice. It is easy to adopt, scalable to design, reduces time-to-market, and is economical to build." http://www.intel.com/fsp Change-Id: I0fa64dbaf640493cdb5e670e8d213a49d9e7dcfb Signed-off-by: Martin Roth Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/5456 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/vendorcode/intel/fsp/baytrail/include/fsp.h | 69 +++++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 src/vendorcode/intel/fsp/baytrail/include/fsp.h (limited to 'src/vendorcode/intel/fsp/baytrail/include/fsp.h') diff --git a/src/vendorcode/intel/fsp/baytrail/include/fsp.h b/src/vendorcode/intel/fsp/baytrail/include/fsp.h new file mode 100644 index 0000000000..f2e1d8fabf --- /dev/null +++ b/src/vendorcode/intel/fsp/baytrail/include/fsp.h @@ -0,0 +1,69 @@ +/** + +Copyright (C) 2013, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +/** \file fsp.h + * + * + */ +#include +#include "fsptypes.h" +#include "fspfv.h" +#include "fspffs.h" +#include "fsphob.h" +#include "fspapi.h" +#include "fspplatform.h" +#include "fspinfoheader.h" +#include "fspvpd.h" + +#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ +{ 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } } +#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ +{ 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } } +#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ +{ 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } } +#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ +{ 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } } +#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ +{ 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } } + +// +// 0x21 - 0xf..f are reserved. +// +#define BOOT_WITH_FULL_CONFIGURATION 0x00 +#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01 +#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02 +#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03 +#define BOOT_WITH_DEFAULT_SETTINGS 0x04 +#define BOOT_ON_S4_RESUME 0x05 +#define BOOT_ON_S5_RESUME 0x06 +#define BOOT_ON_S2_RESUME 0x10 +#define BOOT_ON_S3_RESUME 0x11 +#define BOOT_ON_FLASH_UPDATE 0x12 +#define BOOT_IN_RECOVERY_MODE 0x20 -- cgit v1.2.3