From 8b9f28994a1b5702ce33e62e55d1595b1a056892 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 25 Jan 2018 10:50:39 +0530 Subject: vendorcode/intel: Add UDK2017 support This patch includes (edk2/UDK2017) all required headers for UDK2017 from EDK2 github project using below command >> git clone https://github.com/tianocore/edk2.git vUDK2017 commit hash: 66833b2a87d98be8d81d1337c193bcbf0de47d47 Change-Id: If0d5a3fef016c67e9eed6aed9b698b3b13b930c4 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/23425 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- .../MdePkg/Include/IndustryStandard/SdramSpd.h | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpd.h (limited to 'src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpd.h') diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpd.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpd.h new file mode 100644 index 0000000000..0a4d8943c0 --- /dev/null +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpd.h @@ -0,0 +1,74 @@ +/** @file + This file contains definitions for the SPD fields on an SDRAM. + + Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef _SDRAM_SPD_H_ +#define _SDRAM_SPD_H_ + +#include +#include +#include + +// +// SDRAM SPD field definitions +// +#define SPD_MEMORY_TYPE 2 +#define SPD_SDRAM_ROW_ADDR 3 +#define SPD_SDRAM_COL_ADDR 4 +#define SPD_SDRAM_MODULE_ROWS 5 +#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6 +#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7 +#define SPD_SDRAM_ECC_SUPPORT 11 +#define SPD_SDRAM_REFRESH 12 +#define SPD_SDRAM_WIDTH 13 +#define SPD_SDRAM_ERROR_WIDTH 14 +#define SPD_SDRAM_BURST_LENGTH 16 +#define SPD_SDRAM_NO_OF_BANKS 17 +#define SPD_SDRAM_CAS_LATENCY 18 +#define SPD_SDRAM_MODULE_ATTR 21 + +#define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency +#define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency +#define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency +#define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency +#define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency +#define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency +#define SPD_SDRAM_MIN_PRECHARGE 27 +#define SPD_SDRAM_ACTIVE_MIN 28 +#define SPD_SDRAM_RAS_CAS 29 +#define SPD_SDRAM_RAS_PULSE 30 +#define SPD_SDRAM_DENSITY 31 + +// +// Memory Type Definitions +// +#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory +#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory +#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory +#define SPD_VAL_DDR3_TYPE 11 ///< DDR3 SDRAM memory +#define SPD_VAL_DDR4_TYPE 12 ///< DDR4 SDRAM memory +#define SPD_VAL_LPDDR3_TYPE 15 ///< LPDDR3 SDRAM memory +#define SPD_VAL_LPDDR4_TYPE 16 ///< LPDDR4 SDRAM memory + +// +// ECC Type Definitions +// +#define SPD_ECC_TYPE_NONE 0x00 ///< No error checking +#define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking +#define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only +// +// Module Attributes (Bit positions) +// +#define SPD_BUFFERED 0x01 +#define SPD_REGISTERED 0x02 + +#endif -- cgit v1.2.3