From 9aea04aa892903009e487ada7f7b911691e68630 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 30 Mar 2012 12:01:06 -0700 Subject: Add Google ChromeOS vendor support Google's ChromeOS can be booted super fast and safely using coreboot. This adds the ChromeOS specific code that is required by all ChromeBooks to do this. Change-Id: Ic03ff090a569a27acbd798ce1e5f89a34897a2f2 Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/817 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/vendorcode/google/chromeos/Kconfig | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) (limited to 'src/vendorcode/google/chromeos/Kconfig') diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index f838b74804..207431d0ec 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -22,7 +22,34 @@ config CHROMEOS select TPM select CACHE_ROM help - Enable ChromeOS specific features + Enable ChromeOS specific features like the GPIO sub table in + the coreboot table. NOTE: Enabling this option on an unsupported + board will most likely break your build. +config VBNV_OFFSET + hex + default 0x26 + help + CMOS offset for VbNv data. This value must match cmos.layout + in the mainboard directory, minus 14 bytes for the RTC. + +config VBNV_SIZE + hex + default 0x10 + help + CMOS storage size for VbNv data. This value must match cmos.layout + in the mainboard directory. + +config CHROMEOS_RAMOOPS + bool "Reserve space for Chrome OS ramoops" + default y +config CHROMEOS_RAMOOPS_RAM_START + hex "Physical address of preserved RAM" + default 0x00f00000 + depends on CHROMEOS_RAMOOPS +config CHROMEOS_RAMOOPS_RAM_SIZE + hex "Size of preserved RAM" + default 0x00100000 + depends on CHROMEOS_RAMOOPS -- cgit v1.2.3