From 7d48ac5c7dfb52fc470bbad1013b4d460bc6a1e0 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 9 Mar 2018 14:30:38 -0800 Subject: soc/cavium: Integrate BDK files into coreboot * Make it compile. * Fix whitespace errors. * Fix printf formats. * Add missing headers includes * Guard headers with ifdefs Compile DRAM init code in romstage. Compile QLM, PCIe, RNG, PHY, GPIO, MDIO init code in ramstage. Change-Id: I0a93219a14bfb6ebe41103a825d5032b11e7f2c6 Signed-off-by: David Hendricks Reviewed-on: https://review.coreboot.org/25089 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- .../cavium/include/bdk/libbdk-hal/bdk-atomic.h | 74 +++------------------- 1 file changed, 10 insertions(+), 64 deletions(-) (limited to 'src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-atomic.h') diff --git a/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-atomic.h b/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-atomic.h index 7f521a67e2..1b8f7847fd 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-atomic.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-atomic.h @@ -1,3 +1,5 @@ +#ifndef __CB_BDK_ATOMIC_H__ +#define __CB_BDK_ATOMIC_H__ /***********************license start*********************************** * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights * reserved. @@ -197,26 +199,12 @@ static inline int bdk_atomic_compare_and_store32_nosync(uint32_t *ptr, uint32_t /* CN88XX pass 1.x has errata AP-22500: GlobalSync request during a multi-cycle ATOMIC stalls forever Don't use compare and swap on these chips */ - if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS1_X)) - { - asm volatile ("1: ldxr %w[v], [%[b]] \n" - " cmp %w[v], %w[o] \n" - " b.ne 2f \n" - " stxr %w[v], %w[n], [%[b]]\n" /* Returns zero on success */ - " cbnz %w[v], 1b \n" - " mov %w[v], %w[o] \n" - "2: \n" - : [mem] "+m" (*ptr), [v] "=&r" (val) - : [b] "r" (ptr), [n] "r" (new_val), [o] "r" (old_val) - : ); - } - else - { + asm volatile ("cas %w[o], %w[n], [%[b]]" : [mem] "+m" (*ptr), [o] "+r" (val) : [b] "r" (ptr), [n] "r" (new_val) : ); - } + return old_val == val; } @@ -239,26 +227,12 @@ static inline int bdk_atomic_compare_and_store32(uint32_t *ptr, uint32_t old_val /* CN88XX pass 1.x has errata AP-22500: GlobalSync request during a multi-cycle ATOMIC stalls forever Don't use compare and swap on these chips */ - if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS1_X)) - { - asm volatile ("1: ldaxr %w[v], [%[b]] \n" - " cmp %w[v], %w[o] \n" - " b.ne 2f \n" - " stlxr %w[v], %w[n], [%[b]]\n" /* Returns zero on success */ - " cbnz %w[v], 1b \n" - " mov %w[v], %w[o] \n" - "2: \n" - : [mem] "+m" (*ptr), [v] "=&r" (val) - : [b] "r" (ptr), [n] "r" (new_val), [o] "r" (old_val) - : ); - } - else - { + asm volatile ("casal %w[o], %w[n], [%[b]]" : [mem] "+m" (*ptr), [o] "+r" (val) : [b] "r" (ptr), [n] "r" (new_val) : ); - } + return old_val == val; } @@ -281,26 +255,12 @@ static inline int bdk_atomic_compare_and_store64_nosync(uint64_t *ptr, uint64_t /* CN88XX pass 1.x has errata AP-22500: GlobalSync request during a multi-cycle ATOMIC stalls forever Don't use compare and swap on these chips */ - if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS1_X)) - { - asm volatile ("1: ldxr %x[v], [%[b]] \n" - " cmp %x[v], %x[o] \n" - " b.ne 2f \n" - " stxr %x[v], %x[n], [%[b]]\n" /* Returns zero on success */ - " cbnz %x[v], 1b \n" - " mov %x[v], %x[o] \n" - "2: \n" - : [mem] "+m" (*ptr), [v] "=&r" (val) - : [b] "r" (ptr), [n] "r" (new_val), [o] "r" (old_val) - : ); - } - else - { + asm volatile ("cas %x[o], %x[n], [%[b]]" : [mem] "+m" (*ptr), [o] "+r" (val) : [b] "r" (ptr), [n] "r" (new_val) : ); - } + return old_val == val; } @@ -323,26 +283,11 @@ static inline int bdk_atomic_compare_and_store64(uint64_t *ptr, uint64_t old_val /* CN88XX pass 1.x has errata AP-22500: GlobalSync request during a multi-cycle ATOMIC stalls forever Don't use compare and swap on these chips */ - if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS1_X)) - { - asm volatile ("1: ldaxr %x[v], [%[b]] \n" - " cmp %x[v], %x[o] \n" - " b.ne 2f \n" - " stlxr %x[v], %x[n], [%[b]]\n" /* Returns zero on success */ - " cbnz %x[v], 1b \n" - " mov %x[v], %x[o] \n" - "2: \n" - : [mem] "+m" (*ptr), [v] "=&r" (val) - : [b] "r" (ptr), [n] "r" (new_val), [o] "r" (old_val) - : ); - } - else - { + asm volatile ("casal %x[o], %x[n], [%[b]]" : [mem] "+m" (*ptr), [o] "+r" (val) : [b] "r" (ptr), [n] "r" (new_val) : ); - } return old_val == val; } @@ -539,3 +484,4 @@ static inline uint32_t bdk_atomic_fetch_and_bclr32_nosync(uint32_t *ptr, uint32_ } /** @} */ +#endif /* !__CB_BDK_ATOMIC_H__ */ -- cgit v1.2.3