From 7bbe3bb9f0caf518af89bc18b99cd9ac32ceff3f Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Fri, 7 Dec 2018 11:23:21 +0100 Subject: vendorcode/{amd,cavium,intel}: Remove trailing whitespace find src -type f "!" -regex ".*\.\(vbt\|bin\)" -exec sed -i -e "s,\s\+$,,g" {} \; Change-Id: Ic70cf8524dcd0a0f5700f91b704b3c545dd8a01a Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/30959 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- .../cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c | 8 +-- .../bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c | 14 ++-- .../bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c | 76 +++++++++++----------- 3 files changed, 49 insertions(+), 49 deletions(-) (limited to 'src/vendorcode/cavium/bdk/libbdk-hal/if') diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c index e8f3a009dd..0efe6975e5 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c @@ -81,7 +81,7 @@ static void setup_marvell_phy(bdk_node_t node, int mdio_bus, int mdio_addr) phy_status = bdk_mdio_read(node, mdio_bus, mdio_addr, 22); if (phy_status < 0) return; - + phy_status = bdk_mdio_read(node, mdio_bus, mdio_addr, 17); if (phy_status < 0) return; @@ -99,14 +99,14 @@ int bdk_if_phy_marvell_setup(bdk_node_t node, int qlm, int mdio_bus, int phy_add /* Check that the GSER mode is SGMII */ /* Switch the marvell PHY to the correct mode */ bdk_qlm_modes_t qlm_mode = bdk_qlm_get_mode(node, qlm); - + BDK_TRACE(PHY,"%s: QLM:%d QLM_MODE:%d\n",__FUNCTION__, qlm, qlm_mode); - + if ((qlm_mode != BDK_QLM_MODE_SGMII_1X1) && (qlm_mode != BDK_QLM_MODE_SGMII_2X1)) return 0; - BDK_TRACE(PHY,"%s: Detected Marvell Phy in SGMII mode\n", __FUNCTION__); + BDK_TRACE(PHY,"%s: Detected Marvell Phy in SGMII mode\n", __FUNCTION__); for (int port = 0; port < 2; port++) { setup_marvell_phy(node, mdio_bus, phy_addr + port); diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c index 4d6ef8d25d..26c4fd45a1 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c @@ -90,7 +90,7 @@ static void vitesse_init_script(bdk_node_t node, int mdio_bus, int phy_addr) uint16_t reg_addr; uint16_t reg_val; uint16_t mask; - + BDK_TRACE(PHY,"In %s\n",__FUNCTION__); BDK_TRACE(PHY,"Loading init script for VSC8514\n"); @@ -122,20 +122,20 @@ static void vitesse_program(bdk_node_t node, int mdio_bus, int phy_addr) /** * Setup Vitesse PHYs - * This function sets up one port in a Vitesse VSC8514 + * This function sets up one port in a Vitesse VSC8514 */ static void setup_vitesse_phy(bdk_node_t node, int mdio_bus, int phy_addr) { /*setting MAC if*/ bdk_mdio_write(node, mdio_bus, phy_addr, 31, VSC_PHY_GPIO_PAGE); - wr_masked(node,mdio_bus,phy_addr, 19, 0x4000, 0xc000); + wr_masked(node,mdio_bus,phy_addr, 19, 0x4000, 0xc000); bdk_mdio_write(node, mdio_bus, phy_addr, 18, 0x80e0); /*Setting media if*/ bdk_mdio_write(node, mdio_bus, phy_addr, 31, VSC_PHY_STD_PAGE); // Reg23, 10:8 Select copper, CAT5 copper only wr_masked(node,mdio_bus,phy_addr, 23, 0x0000, 0x0700); - + // Reg0:15, soft Reset wr_masked(node,mdio_bus,phy_addr, 0, 0x8000, 0x8000); int time_out = 100; @@ -159,9 +159,9 @@ static void setup_vitesse_phy(bdk_node_t node, int mdio_bus, int phy_addr) bdk_mdio_write(node, mdio_bus, phy_addr, 16, 0x80); // Select main registers bdk_mdio_write(node, mdio_bus, phy_addr, 31, VSC_PHY_STD_PAGE); - + /* - + if (LOOP_INTERNAL) { reg0 = bdk_mdio_read(node, mdio_bus, phy_addr, 0); @@ -176,7 +176,7 @@ static void setup_vitesse_phy(bdk_node_t node, int mdio_bus, int phy_addr) reg23 = bdk_insert(reg23, 1, 3, 1); bdk_mdio_write(node, mdio_bus, phy_addr, 23, reg23); } - + // Dump registers if (false) diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c index b6f052ad47..77ba4c4233 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c @@ -48,10 +48,10 @@ BDK_REQUIRE_DEFINE(XFI); /* Rate Select Settings -Mode State : 6/8 -Rate Select State : 0 -RSEL1 : 0 -RSEL0 : 0 +Mode State : 6/8 +Rate Select State : 0 +RSEL1 : 0 +RSEL0 : 0 Ref Clock Gen(MHz) : 156.25 Data Rate(Gbps) : 10.3125 Description : 10 GbE @@ -60,60 +60,60 @@ Description : 10 GbE Data Rate Detection Configuration Registers Mode Pin Settings: -Mode State : 0 -MODE1 : 0 -MODE0 : 0 +Mode State : 0 +MODE1 : 0 +MODE0 : 0 Mode : Two-wire serial interface mode LOS Pin Strap Mode Settings -Mode State : 2/6/8 -State : 4 +Mode State : 2/6/8 +State : 4 LOS1 : Float -LOS0 : Float -LOS Amplitude(mVpp) : 20 +LOS0 : Float +LOS Amplitude(mVpp) : 20 LOS Hysteresis(dB) : 2 Input Equalization Retimer Mode Settings Mode State : 6/8 -EQ State : 0 -EQ1 : 0 -EQ0 : 0 -EQ(dB) : Auto -DFE : Auto +EQ State : 0 +EQ1 : 0 +EQ0 : 0 +EQ(dB) : Auto +DFE : Auto Comment : Full Auto Input Equalization Re-Driver Mode Settings -Mode State : -EQ State : 0 -EQ1 : 0 -EQ0 : 0 -EQ(dB) : Auto -DFE : APowered Down +Mode State : +EQ State : 0 +EQ1 : 0 +EQ0 : 0 +EQ(dB) : Auto +DFE : APowered Down Comment : Analog EQ Only Output De-Emphasis Retimer Mode Settings -Mode State : 6/8 -DE State : 3 -TX1 : Float -TX0 : 0 -PRE c(-1) mA : -1 +Mode State : 6/8 +DE State : 3 +TX1 : Float +TX0 : 0 +PRE c(-1) mA : -1 MAIN c( 0) mA : 15 -POST c(+1) mA : 4 +POST c(+1) mA : 4 DC Amplitude(mV): 500 De-Emphasis(dB) : -6.02 -Comment : +Comment : Output De-Emphasis Re-Driver Mode Settings -Mode State : 2 -DE State : 3 -TX1 : Float -TX0 : 0 -Frequency(Gbps) : 10.3125 +Mode State : 2 +DE State : 3 +TX1 : Float +TX0 : 0 +Frequency(Gbps) : 10.3125 DC Amplitude(mV): 600 -De-Emphasis(dB) : 4 +De-Emphasis(dB) : 4 Comment : 10GbE @@ -181,10 +181,10 @@ Page Reg Position Mask val RegFieldName 0x00 0x97 b09 0x0200 1 PD_OD 0x00 0xA0 b11 0x0800 1 PD_LOS 0x00 0xA4 b15 0x8000 1 PD_CH -0x00 0xB5 b07 0x0080 1 PD_INBUF -0x00 0xB9 b15 0x8000 1 ASYN_SYNN +0x00 0xB5 b07 0x0080 1 PD_INBUF +0x00 0xB9 b15 0x8000 1 ASYN_SYNN 0x00 0xB9 b09 0x0200 1 PD_OD -0x00 0xBF b07 0x0080 1 PD_INBUF +0x00 0xBF b07 0x0080 1 PD_INBUF 0x00 0xF0 b15 0x8000 1 ASYN_SYNN 0x00 0xF0 b09 0x0200 1 PD_OD 0x00 0xF6 b07 0x0080 1 PD_INBUF -- cgit v1.2.3