From e522258907c0f16fb46c8abfed64532fd3d81202 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 27 Mar 2017 19:02:55 +0300 Subject: AGESA f14: Fix memory clock register decoding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bottom five LSBs are used to store the running frequency of memory clock. Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/19042 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/vendorcode/amd') diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c index ee14fed847..411caf843c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c @@ -528,7 +528,8 @@ MemMSetCSRNb ( IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); RetVal = FALSE; } - if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.TargetSpeed) != ((Value & 7) + 1))) { + if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, + NBPtr->DCTPtr->Timings.TargetSpeed) != (Value & 0x1f))) { IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: MemClk has changed\n"); RetVal = FALSE; } -- cgit v1.2.3