From bb3a5efaf7d684898899b97532629a32c575ae9c Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Mon, 9 Apr 2018 20:14:19 +0200 Subject: Correct "MTTR" to "MTRR" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The term MTRR has been misspelled in a few places. Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/25568 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Aaron Durbin --- src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc | 2 +- src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc | 2 +- src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc | 2 +- src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/vendorcode/amd') diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc index fc7d0e461f..f444852e54 100644 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc @@ -1348,7 +1348,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc index 45ed2948e7..0fbcf77eea 100644 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc @@ -1084,7 +1084,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc index c744e47a03..2399bec91b 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc @@ -1063,7 +1063,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc index 5a4f7b9290..7e12db1d06 100644 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc @@ -1063,7 +1063,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. -- cgit v1.2.3