From 1756e10a3460435a475c1bde06a2587e5da24d84 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 29 Jul 2020 16:31:01 -0600 Subject: vc/amd/picasso/bl_uapp: Update header file Update to match the 0.8.5.7B release of PSP blobs. BUG=b:162057232 TEST=Boot Trembyle with, and without, new blobs. Inspect vboot using a serial-enabled bootloader Change-Id: I03f11cfc1dc8f511661def1c81421f8558dcd1f5 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/44041 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- .../picasso/include/bl_uapp/bl_syscall_public.h | 48 ++++++++++------------ 1 file changed, 21 insertions(+), 27 deletions(-) (limited to 'src/vendorcode/amd') diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h index 17913c0c46..45ea67e5c4 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h @@ -35,6 +35,7 @@ #define SVC_EXIT 0x00 #define SVC_MAP_USER_STACK 0x01 #define SVC_DEBUG_PRINT 0x06 +#define SVC_RSAPSS_VERIFY 0x0D #define SVC_DEBUG_PRINT_EX 0x1A #define SVC_WAIT_10NS_MULTIPLE 0x1B #define SVC_GET_BOOT_MODE 0x1C @@ -52,6 +53,17 @@ #define SVC_GET_MAX_WORKBUF_SIZE 0x45 #define SVC_SHA 0x46 +typedef struct _RSAPSS_VERIFY_PARAMS_T +{ + char *pHash; // Message digest to verify the RSA signature + unsigned int HashLen; // hash length in bytes + char *pModulus; // Modulus address + unsigned int ModulusSize; // Modulus length in bytes + char *pExponent; // Exponent address + unsigned int ExpSize; // Exponent length in bytes + char *pSig; // Signature to be verified, same size as ModulusSize +} RSAPSS_VERIFY_PARAMS; + typedef enum _PSP_BOOT_MODE { PSP_BOOT_MODE_S0 = 0x0, @@ -62,24 +74,6 @@ typedef enum _PSP_BOOT_MODE PSP_BOOT_MODE_S5_WARM = 0x5, } PSP_BOOT_MODE; -/* TLB2_n settings for AWUSER and TLB3_n settings for ARUSER: - * USER[0] - ReqIO bit, 1'b1 for FCH MMIO address - * USER[1] - Compat bit, 1'b1 for FCH access, 0 for everything else - * USER[2] - ByPass_IOMMU bit, 1'b1 to always bypass IOMMU, 0 for IOMMU translation - */ -typedef enum SYSHUB_TARGET_TYPE_E -{ - // Target Type // Address // [2:0] =[Bypass,Compat,ReqIO] - AxUSER_PCIE_HT0 = 0x0, // PCIe HT (Bypass=0) // [2:0] =[0,0,0] - AxUSER_DRAM_VIA_IOMMU = 0x1, // DRAM ACCESS via IOMMU// [2:0] =[0,0,1] - AxUSER_PCIE_HT1 = 0x2, // PCIe HT (Bypass=1) // [2:0] =[0,1,0] - AxUSER_RSVD = 0x3, // - NOT USED ,INVALID // [2:0] =[0,1,1] - AxUSER_DRAM_BYPASS_IOMMU = 0x4, // GENERAL DRAM // [2:0] =[1,0,0] - AxUSER_PCIE_MMIO = 0x5, // PCIe MMIO // [2:0] =[1,0,1] - AxUSER_FCH_HT_IO = 0x6, // FCH HT (port80) // [2:0] =[1,1,0] - AxUSER_FCH_MMIO = 0x6 // FCH MMIO // [2:0] =[1,1,1] -} SYSHUB_TARGET_TYPE; - typedef enum FCH_IO_DEVICE { FCH_IO_DEVICE_SPI, FCH_IO_DEVICE_I2C, @@ -123,15 +117,6 @@ typedef struct SPIROM_INFO uint32_t SpiBiosSize; } SPIROM_INFO; -typedef struct SYSHUB_RW_PARMS_EX_E -{ - uint32_t SyshubAddressLo; - uint32_t SyshubAddressHi; - uint32_t *pValue; - uint32_t Size; - SYSHUB_TARGET_TYPE TargetType; -} SYSHUB_RW_PARMS_EX; - typedef enum PSP_TIMER_TYPE { PSP_TIMER_TYPE_CHRONO = 0, PSP_TIMER_TYPE_RTC = 1, @@ -362,6 +347,15 @@ uint32_t svc_get_max_workbuf_size(uint32_t *size); */ uint32_t svc_crypto_sha(SHA_GENERIC_DATA *sha_op, SHA_OPERATION_MODE sha_mode); +/* RSA PSS Verification of signature and data + * + * Parameters: + * RSAPSS_VERIFY_PARAMS - Pointer to RSA PSS parameters + * + * Return value: BL_OK or error code + */ +uint32_t svc_rsa_pss_verify(const RSAPSS_VERIFY_PARAMS *params); + /* C entry point for the Bootloader Userspace Application */ void Main(void); -- cgit v1.2.3