From b8cb142ccd1922f8f0a245923eabaed5030048e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 23 Jun 2020 21:36:14 +0300 Subject: sb/amd/pi/hudson: Enable use of common GPIO API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code in soc/amd/common has an implementation of GPIO register space that is compatible with the hardware sb/amd/pi/hudson supports. Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/vendorcode/amd/pi/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/vendorcode/amd/pi') diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 25e3652751..47db4e108e 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -76,7 +76,7 @@ export AGESA_CFLAGS := $(AGESA_CFLAGS) CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) -CC_postcar:= $(CC_postcar) -I$(AGESA_ROOT)/binaryPI +CC_postcar:= $(CC_postcar) -I$(src)/southbridge/amd/pi/hudson -I$(AGESA_ROOT)/binaryPI CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) -- cgit v1.2.3