From ccb53e181726ddd90ec6d5a2b6d6b62ab8bd6a70 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 5 May 2018 15:56:18 +0300 Subject: binaryPI: Fix cache coherency use for AP CPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise global variables may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all for some cases. Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Signed-off-by: Kyösti Mälkki Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/26115 Reviewed-by: Michał Żygowski Reviewed-by: Paul Menzel Reviewed-by: Richard Spiegel Tested-by: build bot (Jenkins) --- src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc') diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc index 7e12db1d06..6c4ad596e1 100644 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc @@ -1153,6 +1153,13 @@ SetupStack: 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR # + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR -- cgit v1.2.3