From 0b11bd0d028089288e52f9f08cdcfafc9910511b Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Sun, 19 Jul 2015 15:20:17 -0600 Subject: vendorcode: Move AMD sources from blobs to vendorcode The AMD AGESA binaryPI sources were incorrectly committed to 3rdparty/blobs. Move them from blobs to vendorcode and fix Kconfig and Makefile.inc to match. Change-Id: I55a777553c1203464d7f7f4293b361fedcfa3283 Signed-off-by: Marc Jones Reviewed-on: http://review.coreboot.org/10982 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- .../amd/pi/00730F01/Proc/Fch/Common/AcpiLib.h | 91 ++ .../pi/00730F01/Proc/Fch/Common/FchBiosRamUsage.h | 67 + .../amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h | 1296 ++++++++++++++++++++ .../amd/pi/00730F01/Proc/Fch/Common/FchDef.h | 400 ++++++ 4 files changed, 1854 insertions(+) create mode 100644 src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/AcpiLib.h create mode 100644 src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchBiosRamUsage.h create mode 100644 src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h create mode 100644 src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchDef.h (limited to 'src/vendorcode/amd/pi/00730F01/Proc/Fch/Common') diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/AcpiLib.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/AcpiLib.h new file mode 100644 index 0000000000..23fb37ca44 --- /dev/null +++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/AcpiLib.h @@ -0,0 +1,91 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH ACPI lib + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $ + * + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _FCH_ACPILIB_H_ +#define _FCH_ACPILIB_H_ +/// +/// RSDP - ACPI 2.0 table RSDP +/// +typedef struct _RSDP_HEADER { + UINT64 Signature; ///< RSDP signature "RSD PTR" + UINT8 CheckSum; ///< checksum of the first 20 bytes + UINT8 OEMID[6]; ///< OEM ID + UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0 + UINT32 RsdtAddress; ///< physical address of RSDT + UINT32 Length; ///< total length of RSDP (including extended part) + UINT64 XsdtAddress; ///< physical address of XSDT + UINT8 ExtendedCheckSum; ///< chechsum of whole table + UINT8 Reserved[3]; ///< Reserved +} RSDP_HEADER; + +/// +/// DESCRIPTION_HEADER - ACPI common table header +/// +typedef struct _DESCRIPTION_HEADER { + UINT32 Signature; ///< ACPI signature (4 ASCII characters) + UINT32 Length; ///< Length of table, in bytes, including header + UINT8 Revision; ///< ACPI Specification minor version # + UINT8 CheckSum; ///< To make sum of entire table == 0 + UINT8 OemId[6]; ///< OEM identification + UINT8 OemTableId[8]; ///< OEM table identification + UINT32 OemRevision; ///< OEM revision number + UINT32 CreatorId; ///< ASL compiler vendor ID + UINT32 CreatorRevision; ///< ASL compiler revision number +} DESCRIPTION_HEADER; + +/// +/// _AcpiRegWrite - ACPI MMIO register R/W structure +/// +typedef struct _ACPI_REG_WRITE { + UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02) + UINT8 MmioReg; /// MmioReg : Register index + UINT8 DataAndMask; /// DataANDMask : AND Register Data + UINT8 DataOrMask; /// DataOrMask : Or Register Data +} ACPI_REG_WRITE; + +VOID* AcpiLocateTable (IN UINT32 Signature); +VOID AcpiSetTableCheckSum (IN VOID *TablePtr); +UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr); +UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length); + +#endif diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchBiosRamUsage.h new file mode 100644 index 0000000000..dcd12be43a --- /dev/null +++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchBiosRamUsage.h @@ -0,0 +1,67 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH BIOS Ram usage + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $ + * + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _FCH_BIOS_RAM_USAGE_H_ +#define _FCH_BIOS_RAM_USAGE_H_ + +#define RESTORE_MEMORY_CONTROLLER_START 0 +#define XHCI_REGISTER_BAR00 0xD0 +#define XHCI_REGISTER_BAR01 0xD1 +#define XHCI_REGISTER_BAR02 0xD2 +#define XHCI_REGISTER_BAR03 0xD3 +#define XHCI_REGISTER_04H 0xD4 +#define XHCI_REGISTER_0CH 0xD5 +#define XHCI_REGISTER_3CH 0xD6 +#define XHCI1_REGISTER_BAR00 0xE0 +#define XHCI1_REGISTER_BAR01 0xE1 +#define XHCI1_REGISTER_BAR02 0xE2 +#define XHCI1_REGISTER_BAR03 0xE3 +#define XHCI1_REGISTER_04H 0xE4 +#define XHCI1_REGISTER_0CH 0xE5 +#define XHCI1_REGISTER_3CH 0xE6 +#define RTC_WORKAROUND_DATA_START 0xF0 +#define BOOT_TIME_FLAG_SEC 0xF8 +#define BOOT_TIME_FLAG_INT19 0xFC + +#endif + diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h new file mode 100644 index 0000000000..72e6aeb857 --- /dev/null +++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h @@ -0,0 +1,1296 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH Function Support Definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $ + * + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _FCH_COMMON_CFG_H_ +#define _FCH_COMMON_CFG_H_ + +#pragma pack (push, 1) + +//----------------------------------------------------------------------------- +// FCH DEFINITIONS AND MACROS +//----------------------------------------------------------------------------- + +// +// FCH Component Data Structure Definitions +// + +/// PCI_ADDRESS - PCI access structure +#define PCI_ADDRESS(bus, dev, func, reg) \ + (UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) + +#define CPUID_FMF 0x80000001ul // Family Model Features information +/// +/// - Byte Register R/W structure +/// +typedef struct _REG8_MASK { + UINT8 RegIndex; /// RegIndex - Reserved + UINT8 AndMask; /// AndMask - Reserved + UINT8 OrMask; /// OrMask - Reserved +} REG8_MASK; + + +/// +/// PCIE Reset Block +/// +typedef enum { + NbBlock, ///< Reset for NB PCIE + FchBlock ///< Reset for FCH GPP +} RESET_BLOCK; + +/// +/// PCIE Reset Operation +/// +typedef enum { + DeassertReset, ///< DeassertRese - Deassert reset + AssertReset ///< AssertReset - Assert reset +} RESET_OP; + + +/// +/// SD structure +/// +typedef struct { + SD_MODE SdConfig; ///< SD Mode configuration + /// @li 00 - Disabled + /// @li 00 - AMDA + /// @li 01 - DMA + /// @li 10 - PIO + /// + UINT8 SdSpeed; ///< SD Speed + /// @li 0 - Low speed + /// @li 1 - High speed + /// + UINT8 SdBitWidth; ///< SD Bit Width + /// @li 0 - 32BIT clear 23 + /// @li 1 - 64BIT, set 23,default + /// + UINT32 SdSsid; ///< SD Subsystem ID + SD_CLOCK_CONTROL SdClockControl; ///< SD Clock Control + BOOLEAN SdClockMultiplier; ///< SD Clock Multiplier enable/disable + UINT8 SdReTuningMode; ///< SD Re-tuning modes select + /// @li 0 - mode 1 + /// @li 1 - mode 2 + /// @li 2 - mode 3 + UINT8 SdHostControllerVersion; ///< SD controller Version + /// @li 1 - SD 2.0 + /// @li 2 - SD 3.0 + UINT8 SdrCapabilities; ///< SDR Capability mode select + /// @li 00 - SDR25/15 + /// @li 01 - SDR50 + /// @li 11 - SDR104 + UINT8 SdSlotType; ///< SDR Slot Type select + /// @li 00 - Removable Card Slot + /// @li 01 - Embedded Slot for One Device + /// @li 10 - Shared Bus Slot + BOOLEAN SdForce18; ///< SD Force18 +} FCH_SD; + +/// +/// CODEC_ENTRY - Fch HD Audio OEM Codec structure +/// +typedef struct _CODEC_ENTRY { + UINT8 Nid; /// Nid - Reserved + UINT32 Byte40; /// Byte40 - Reserved +} CODEC_ENTRY; + +/// +/// CODEC_TBL_LIST - Fch HD Audio Codec table list +/// +typedef struct _CODEC_TBL_LIST { + UINT32 CodecId; /// CodecID - Codec ID + CONST CODEC_ENTRY* CodecTablePtr; /// CodecTablePtr - Codec table pointer +} CODEC_TBL_LIST; + +/// +/// AZALIA_PIN - HID Azalia or GPIO define structure. +/// +typedef struct _AZALIA_PIN { + UINT8 AzaliaSdin0; ///< AzaliaSdin0 + /// @par + /// @li 00 - GPIO PIN + /// @li 10 - As a Azalia SDIN pin + + UINT8 AzaliaSdin1; ///< AzaliaSdin1 + /// @par + /// SDIN1 is define at BIT2 & BIT3 + /// @li 00 - GPIO PIN + /// @li 10 - As a Azalia SDIN pin + + UINT8 AzaliaSdin2; ///< AzaliaSdin2 + /// @par + /// SDIN2 is define at BIT4 & BIT5 + /// @li 00 - GPIO PIN + /// @li 10 - As a Azalia SDIN pin + + UINT8 AzaliaSdin3; ///< AzaliaSdin3 + /// @par + /// SDIN3 is define at BIT6 & BIT7 + /// @li 00 - GPIO PIN + /// @li 10 - As a Azalia SDIN pin +} AZALIA_PIN; + +/// +/// Azalia structure +/// +typedef struct { + HDA_CONFIG AzaliaEnable; ///< AzaliaEnable - Azalia function configuration + BOOLEAN AzaliaMsiEnable; ///< AzaliaMsiEnable - Azalia MSI capability + UINT32 AzaliaSsid; ///< AzaliaSsid - Azalia Subsystem ID + UINT8 AzaliaPinCfg; ///< AzaliaPinCfg - Azalia Controller SDIN pin Configuration + /// @par + /// @li 0 - disable + /// @li 1 - enable + + UINT8 AzaliaFrontPanel; ///< AzaliaFrontPanel - Azalia Controller Front Panel Configuration + /// @par + /// Support Front Panel configuration + /// @li 0 - Auto + /// @li 1 - disable + /// @li 2 - enable + + UINT8 FrontPanelDetected; ///< FrontPanelDetected - Force Azalia Controller Front Panel Configuration + /// @par + /// Force Front Panel configuration + /// @li 0 - Not Detected + /// @li 1 - Detected + + UINT8 AzaliaSnoop; ///< AzaliaSnoop - Azalia Controller Snoop feature Configuration + /// @par + /// Azalia Controller Snoop feature Configuration + /// @li 0 - disable + /// @li 1 - enable + + UINT8 AzaliaDummy; /// AzaliaDummy - Reserved */ + + AZALIA_PIN AzaliaConfig; /// AzaliaConfig - Azaliz Pin Configuration + +/// +/// AZOEMTBL - Azalia Controller OEM Codec Table Pointer +/// + CONST CODEC_TBL_LIST *AzaliaOemCodecTablePtr; /// AzaliaOemCodecTablePtr - Oem Azalia Codec Table Pointer + +/// +/// AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer +/// + CONST VOID *AzaliaOemFpCodecTablePtr; /// AzaliaOemFpCodecTablePtr - Oem Front Panel Codec Table Pointer +} FCH_AZALIA; + +/// +/// _SPI_DEVICE_PROFILE Spi Device Profile structure +/// +typedef struct _SPI_DEVICE_PROFILE { + UINT32 JEDEC_ID; /// JEDEC ID + UINT32 RomSize; /// ROM Size + UINT32 SectorSize; /// Sector Size + UINT16 MaxNormalSpeed; /// Max Normal Speed + UINT16 MaxFastSpeed; /// Max Fast Speed + UINT16 MaxDualSpeed; /// Max Dual Speed + UINT16 MaxQuadSpeed; /// Max Quad Speed + UINT8 QeReadRegister; /// QE Read Register + UINT8 QeWriteRegister; /// QE Write Register + UINT8 QeOperateSize; /// QE Operate Size 1byte/2bytes + UINT16 QeLocation; // QE Location in the register +} SPI_DEVICE_PROFILE; + +/// +/// _SPI_CONTROLLER_PROFILE Spi Device Profile structure +/// +typedef struct _SPI_CONTROLLER_PROFILE { +// UINT32 SPI_CONTROLLER_ID; /// SPI Controller ID + UINT16 FifoSize; /// FIFO Size + UINT16 MaxNormalSpeed; /// Max Normal Speed + UINT16 MaxFastSpeed; /// Max Fast Speed + UINT16 MaxDualSpeed; /// Max Dual Speed + UINT16 MaxQuadSpeed; /// Max Quad Speed +} SPI_CONTROLLER_PROFILE; + +/// +/// SPI structure +/// +typedef struct { + BOOLEAN LpcMsiEnable; ///< LPC MSI capability + UINT32 LpcSsid; ///< LPC Subsystem ID + UINT32 RomBaseAddress; ///< SpiRomBaseAddress + /// @par + /// SPI ROM BASE Address + /// + UINT8 SpiSpeed; ///< SpiSpeed - Spi Frequency + /// @par + /// SPI Speed [1.0] - the clock speed for non-fast read command + /// @li 00 - 66Mhz + /// @li 01 - 33Mhz + /// @li 10 - 22Mhz + /// @li 11 - 16.5Mhz + /// + UINT8 SpiFastSpeed; ///< FastSpeed - Spi Fast Speed feature + /// SPIFastSpeed [1.0] - the clock speed for Fast Speed Feature + /// @li 00 - 66Mhz + /// @li 01 - 33Mhz + /// @li 10 - 22Mhz + /// @li 11 - 16.5Mhz + /// + UINT8 WriteSpeed; ///< WriteSpeed - Spi Write Speed + /// @par + /// WriteSpeed [1.0] - the clock speed for Spi write command + /// @li 00 - 66Mhz + /// @li 01 - 33Mhz + /// @li 10 - 22Mhz + /// @li 11 - 16.5Mhz + /// + UINT8 SpiMode; ///< SpiMode - Spi Mode Setting + /// @par + /// @li 101 - Qual-io 1-4-4 + /// @li 100 - Dual-io 1-2-2 + /// @li 011 - Qual-io 1-1-4 + /// @li 010 - Dual-io 1-1-2 + /// @li 111 - FastRead + /// @li 110 - Normal + /// + UINT8 AutoMode; ///< AutoMode - Spi Auto Mode + /// @par + /// SPI Auto Mode + /// @li 0 - Disabled + /// @li 1 - Enabled + /// + UINT8 SpiBurstWrite; ///< SpiBurstWrite - Spi Burst Write Mode + /// @par + /// SPI Burst Write + /// @li 0 - Disabled + /// @li 1 - Enabled + BOOLEAN LpcClk0; ///< Lclk0En - LPCCLK0 + /// @par + /// LPC Clock 0 mode + /// @li 0 - forced to stop + /// @li 1 - functioning with CLKRUN protocol + BOOLEAN LpcClk1; ///< Lclk1En - LPCCLK1 + /// @par + /// LPC Clock 1 mode + /// @li 0 - forced to stop + /// @li 1 - functioning with CLKRUN protocol +// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38 +// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C +// UINT8 SpiProtectEn0_1d_34; /// + UINT8 SPI100_Enable; /// + SPI_DEVICE_PROFILE SpiDeviceProfile; /// Spi Device Profile +} FCH_SPI; + + +/// +/// IDE structure +/// +typedef struct { + BOOLEAN IdeEnable; ///< IDE function switch + BOOLEAN IdeMsiEnable; ///< IDE MSI capability + UINT32 IdeSsid; ///< IDE controller Subsystem ID +} FCH_IDE; + +/// +/// IR Structure +/// +typedef struct { + IR_CONFIG IrConfig; ///< IrConfig + UINT8 IrPinControl; ///< IrPinControl +} FCH_IR; + + +/// +/// PCI Bridge Structure +/// +typedef struct { + BOOLEAN PcibMsiEnable; ///< PCI-PCI Bridge MSI capability + UINT32 PcibSsid; ///< PCI-PCI Bridge Subsystem ID + UINT8 PciClks; ///< 33MHz PCICLK0/1/2/3 Enable, bits [0:3] used + /// @li 0 - disable + /// @li 1 - enable + /// + UINT16 PcibClkStopOverride; ///< PCIB_CLK_Stop Override + BOOLEAN PcibClockRun; ///< Enable the auto clkrun functionality + /// @li 0 - disable + /// @li 1 - enable + /// +} FCH_PCIB; + + +/// +/// - SATA Phy setting structure +/// +typedef struct _SATA_PHY_SETTING { + UINT16 PhyCoreControlWord; /// PhyCoreControlWord - Reserved + UINT32 PhyFineTuneDword; /// PhyFineTuneDword - Reserved +} SATA_PHY_SETTING; + +/// +/// SATA main setting structure +/// +typedef struct _SATA_ST { + UINT8 SataModeReg; ///< SataModeReg - Sata Controller Mode + BOOLEAN SataEnable; ///< SataEnable - Sata Controller Function + /// @par + /// Sata Controller + /// @li 0 - disable + /// @li 1 - enable + /// + UINT8 Sata6AhciCap; ///< Sata6AhciCap - Reserved */ + BOOLEAN SataSetMaxGen2; ///< SataSetMaxGen2 - Set Sata Max Gen2 mode + /// @par + /// Sata Controller Set to Max Gen2 mode + /// @li 0 - disable + /// @li 1 - enable + /// + BOOLEAN IdeEnable; ///< IdeEnable - Hidden IDE + /// @par + /// Sata IDE Controller Combined Mode + /// Enable - SATA controller has control over Port0 through Port3, + /// IDE controller has control over Port4 and Port7. + /// Disable - SATA controller has full control of all 8 Ports + /// when operating in non-IDE mode. + /// @li 0 - enable + /// @li 1 - disable + /// + UINT8 SataClkMode; /// SataClkMode - Reserved +} SATA_ST; + +/// +/// SATA_PORT_ST - SATA PORT structure +/// +typedef struct _SATA_PORT_ST { + UINT8 SataPortReg; ///< SATA Port bit map - bits[0:7] for ports 0 ~ 7 + /// @li 0 - disable + /// @li 1 - enable + /// + BOOLEAN Port0; ///< PORT0 - 0:disable, 1:enable + BOOLEAN Port1; ///< PORT1 - 0:disable, 1:enable + BOOLEAN Port2; ///< PORT2 - 0:disable, 1:enable + BOOLEAN Port3; ///< PORT3 - 0:disable, 1:enable + BOOLEAN Port4; ///< PORT4 - 0:disable, 1:enable + BOOLEAN Port5; ///< PORT5 - 0:disable, 1:enable + BOOLEAN Port6; ///< PORT6 - 0:disable, 1:enable + BOOLEAN Port7; ///< PORT7 - 0:disable, 1:enable +} SATA_PORT_ST; + +/// +///< _SATA_PORT_MD - Force Each PORT to GEN1/GEN2 mode +/// +typedef struct _SATA_PORT_MD { + UINT16 SataPortMode; ///< SATA Port GEN1/GEN2 mode bit map - bits [0:15] for ports 0 ~ 7 + UINT8 Port0; ///< PORT0 - set BIT0 to GEN1, BIT1 - PORT0 set to GEN2 + UINT8 Port1; ///< PORT1 - set BIT2 to GEN1, BIT3 - PORT1 set to GEN2 + UINT8 Port2; ///< PORT2 - set BIT4 to GEN1, BIT5 - PORT2 set to GEN2 + UINT8 Port3; ///< PORT3 - set BIT6 to GEN1, BIT7 - PORT3 set to GEN2 + UINT8 Port4; ///< PORT4 - set BIT8 to GEN1, BIT9 - PORT4 set to GEN2 + UINT8 Port5; ///< PORT5 - set BIT10 to GEN1, BIT11 - PORT5 set to GEN2 + UINT8 Port6; ///< PORT6 - set BIT12 to GEN1, BIT13 - PORT6 set to GEN2 + UINT8 Port7; ///< PORT7 - set BIT14 to GEN1, BIT15 - PORT7 set to GEN2 +} SATA_PORT_MD; +/// +/// SATA structure +/// +typedef struct { + BOOLEAN SataMsiEnable; ///< SATA MSI capability + UINT32 SataIdeSsid; ///< SATA IDE mode SSID + UINT32 SataRaidSsid; ///< SATA RAID mode SSID + UINT32 SataRaid5Ssid; ///< SATA RAID 5 mode SSID + UINT32 SataAhciSsid; ///< SATA AHCI mode SSID + + SATA_ST SataMode; /// SataMode - Reserved + SATA_CLASS SataClass; ///< SataClass - SATA Controller mode [2:0] + UINT8 SataIdeMode; ///< SataIdeMode - Sata IDE Controller mode + /// @par + /// @li 0 - Legacy IDE mode + /// @li 1 - Native IDE mode + /// + UINT8 SataDisUnusedIdePChannel; ///< SataDisUnusedIdePChannel-Disable Unused IDE Primary Channel + /// @par + /// @li 0 - Channel Enable + /// @li 1 - Channel Disable + /// + UINT8 SataDisUnusedIdeSChannel; ///< SataDisUnusedIdeSChannel - Disable Unused IDE Secondary Channel + /// @par + /// @li 0 - Channel Enable + /// @li 1 - Channel Disable + /// + UINT8 IdeDisUnusedIdePChannel; ///< IdeDisUnusedIdePChannel-Disable Unused IDE Primary Channel + /// @par + /// @li 0 - Channel Enable + /// @li 1 - Channel Disable + /// + UINT8 IdeDisUnusedIdeSChannel; ///< IdeDisUnusedIdeSChannel-Disable Unused IDE Secondary Channel + /// @par + /// @li 0 - Channel Enable + /// @li 1 - Channel Disable + /// + UINT8 SataOptionReserved; /// SataOptionReserved - Reserved + + SATA_PORT_ST SataEspPort; ///< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:) + + SATA_PORT_ST SataPortPower; ///< SataPortPower - Port Power configuration + + SATA_PORT_MD SataPortMd; ///< SataPortMd - Port Mode + + UINT8 SataAggrLinkPmCap; /// SataAggrLinkPmCap - 0:OFF 1:ON + UINT8 SataPortMultCap; /// SataPortMultCap - 0:OFF 1:ON + UINT8 SataClkAutoOff; /// SataClkAutoOff - AutoClockOff 0:Disabled, 1:Enabled + UINT8 SataPscCap; /// SataPscCap 1:Enable PSC, 0:Disable PSC capability + UINT8 BiosOsHandOff; /// BiosOsHandOff - Reserved + UINT8 SataFisBasedSwitching; /// SataFisBasedSwitching - Reserved + UINT8 SataCccSupport; /// SataCccSupport - Reserved + UINT8 SataSscCap; /// SataSscCap - 1:Enable, 0:Disable SSC capability + UINT8 SataMsiCapability; /// SataMsiCapability 0:Hidden 1:Visible + UINT8 SataForceRaid; /// SataForceRaid 0:No function 1:Force RAID + UINT8 SataInternal100Spread; /// SataInternal100Spread - Reserved + UINT8 SataDebugDummy; /// SataDebugDummy - Reserved + UINT8 SataTargetSupport8Device; /// SataTargetSupport8Device - Reserved + UINT8 SataDisableGenericMode; /// SataDisableGenericMode - Reserved + BOOLEAN SataAhciEnclosureManagement; /// SataAhciEnclosureManagement - Reserved + UINT8 SataSgpio0; /// SataSgpio0 - Reserved + UINT8 SataSgpio1; /// SataSgpio1 - Reserved + UINT8 SataPhyPllShutDown; /// SataPhyPllShutDown - Reserved + BOOLEAN SataHotRemovalEnh; /// SataHotRemovalEnh - Reserved + + SATA_PORT_ST SataHotRemovalEnhPort; ///< SataHotRemovalEnhPort - Hot Remove + + BOOLEAN SataOobDetectionEnh; /// SataOobDetectionEnh - TRUE + BOOLEAN SataPowerSavingEnh; /// SataPowerSavingEnh - TRUE + UINT8 SataMemoryPowerSaving; /// SataMemoryPowerSaving - 0-3 Default [3] + BOOLEAN SataRasSupport; /// SataRasSupport - Support RAS function TRUE: Enable FALSE: Disable + BOOLEAN SataAhciDisPrefetchFunction; /// SataAhciDisPrefetchFunction - Disable AHCI Prefetch Function Support + BOOLEAN SataDevSlpPort0; /// SataDevSlpPort0 - Reserved + BOOLEAN SataDevSlpPort1; /// SataDevSlpPort1 - Reserved + UINT32 TempMmio; /// TempMmio - Reserved +} FCH_SATA; + + +// +// IMC Message Register Software Interface +// +#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3) + +#define MSG_SYS_TO_IMC 0x80 +#define Fun_80 0x80 +#define Fun_81 0x81 +#define Fun_82 0x82 +#define Fun_83 0x83 +#define Fun_84 0x84 +#define Fun_85 0x85 +#define Fun_86 0x86 +#define Fun_87 0x87 +#define Fun_88 0x88 +#define Fun_89 0x89 +#define Fun_90 0x90 +#define MSG_IMC_TO_SYS 0x81 +#define MSG_REG0 0x82 +#define MSG_REG1 0x83 +#define MSG_REG2 0x84 +#define MSG_REG3 0x85 +#define MSG_REG4 0x86 +#define MSG_REG5 0x87 +#define MSG_REG6 0x88 +#define MSG_REG7 0x89 +#define MSG_REG8 0x8A +#define MSG_REG9 0x8B +#define MSG_REGA 0x8C +#define MSG_REGB 0x8D +#define MSG_REGC 0x8E +#define MSG_REGD 0x8F + +#define DISABLED 0 +#define ENABLED 1 + + + +/// +/// EC structure +/// +typedef struct _FCH_EC { + UINT8 MsgFun81Zone0MsgReg0; ///00 - by default strapping + /// @li 01 - enable + /// @li 10 - disable + /// +} FCH_IMC; + + +/// +/// Hpet structure +/// +typedef struct { + BOOLEAN HpetEnable; ///< HPET function switch + + BOOLEAN HpetMsiDis; ///< HpetMsiDis - South Bridge HPET MSI Configuration + /// @par + /// @li 1 - disable + /// @li 0 - enable + + UINT32 HpetBase; ///< HpetBase + /// @par + /// HPET Base address +} FCH_HPET; + + +/// +/// GCPU related parameters +/// +typedef struct { + UINT8 AcDcMsg; ///< Send a message to CPU to indicate the power mode (AC vs battery) + /// @li 1 - disable + /// @li 0 - enable + + UINT8 TimerTickTrack; ///< Send a message to CPU to indicate the latest periodic timer interval + /// @li 1 - disable + /// @li 0 - enable + + UINT8 ClockInterruptTag; ///< Mark the periodic timer interrupt + /// @li 1 - disable + /// @li 0 - enable + + UINT8 OhciTrafficHanding; ///< Cause CPU to break out from C state when USB OHCI has pending traffic + /// @li 1 - disable + /// @li 0 - enable + + UINT8 EhciTrafficHanding; ///< Cause CPU to break out from C state when USB EHCI has pending traffic + /// @li 1 - disable + /// @li 0 - enable + + UINT8 GcpuMsgCMultiCore; ///< Track of CPU C state by monitoring each core's C state message + /// @li 1 - disable + /// @li 0 - enable + + UINT8 GcpuMsgCStage; ///< Enable the FCH C state coordination logic + /// @li 1 - disable + /// @li 0 - enable +} FCH_GCPU; + + +/// +/// Timer +/// +typedef struct { + BOOLEAN Enable; ///< Whether to register timer SMI in POST + BOOLEAN StartNow; ///< Whether to start the SMI immediately during registration + UINT16 CycleDuration; ///< [14:0] - Actual cycle duration = CycleDuration + 1 +} TIMER_SMI; + +/// +/// CS support +/// +typedef struct { + BOOLEAN FchCsD3Cold; ///< FCH Cs D3 Cold function + BOOLEAN FchCsHwReduced; ///< FCH Cs hardware reduced ACPI flag + BOOLEAN FchCsPwrBtn; ///< FCH Cs Power Button function + BOOLEAN FchCsAcDc; ///< FCH Cs AcDc function + BOOLEAN AsfNfcEnable; ///< FCH Cs NFC function + UINT8 AsfNfcInterruptPin; ///< NFC Interrupt pin define + UINT8 AsfNfcRegPuPin; ///< NFC RegPu pin define + UINT8 AsfNfcWakePin; ///< NFC Wake Pin define + UINT8 PowerButtonGpe; ///< GPE# used by Power Button device + UINT8 AcDcTimerGpe; ///< GPE# used by Timer device +} FCH_CS; + + +/// +/// MISC structure +/// +typedef struct { + BOOLEAN NativePcieSupport; /// PCIe NativePcieSupport - Debug function. 1:Enabled, 0:Disabled + BOOLEAN S3Resume; /// S3Resume - Flag of ACPI S3 Resume. + BOOLEAN RebootRequired; /// RebootRequired - Flag of Reboot system is required. + UINT8 FchVariant; /// FchVariant - FCH Variant value. + UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable + TIMER_SMI LongTimer; ///< Long Timer SMI + TIMER_SMI ShortTimer; ///< Short Timer SMI + UINT32 FchCpuId; ///< Saving CpuId for FCH Module. + BOOLEAN NoneSioKbcSupport; ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function ) + FCH_CS FchCsSupport; ///< FCH Cs function structure +} FCH_MISC; + + +/// +/// SMBus structure +/// +typedef struct { + UINT32 SmbusSsid; ///< SMBUS controller Subsystem ID +} FCH_SMBUS; + + +/// +/// Acpi structure +/// +typedef struct { + UINT16 Smbus0BaseAddress; ///< Smbus0BaseAddress + /// @par + /// Smbus BASE Address + /// + UINT16 Smbus1BaseAddress; ///< Smbus1BaseAddress + /// @par + /// Smbus1 (ASF) BASE Address + /// + UINT16 SioPmeBaseAddress; ///< SioPmeBaseAddress + /// @par + /// SIO PME BASE Address + /// + UINT32 WatchDogTimerBase; ///< WatchDogTimerBase + /// @par + /// Watch Dog Timer Address + /// + UINT16 AcpiPm1EvtBlkAddr; ///< AcpiPm1EvtBlkAddr + /// @par + /// ACPI PM1 event block Address + /// + UINT16 AcpiPm1CntBlkAddr; ///< AcpiPm1CntBlkAddr + /// @par + /// ACPI PM1 Control block Address + /// + UINT16 AcpiPmTmrBlkAddr; ///< AcpiPmTmrBlkAddr + /// @par + /// ACPI PM timer block Address + /// + UINT16 CpuControlBlkAddr; ///< CpuControlBlkAddr + /// @par + /// ACPI CPU control block Address + /// + UINT16 AcpiGpe0BlkAddr; ///< AcpiGpe0BlkAddr + /// @par + /// ACPI GPE0 block Address + /// + UINT16 SmiCmdPortAddr; ///< SmiCmdPortAddr + /// @par + /// SMI command port Address + /// + UINT16 AcpiPmaCntBlkAddr; ///< AcpiPmaCntBlkAddr + /// @par + /// ACPI PMA Control block Address + /// + BOOLEAN AnyHt200MhzLink; ///< AnyHt200MhzLink + /// @par + /// HT Link Speed on 200MHz option for each CPU specific LDTSTP# (Force enable) + /// + BOOLEAN SpreadSpectrum; ///< SpreadSpectrum + /// @par + /// Spread Spectrum function + /// @li 0 - disable + /// @li 1 - enable + /// + POWER_FAIL PwrFailShadow; ///< PwrFailShadow = PM_Reg: 5Bh [3:0] + /// @par + /// @li 00 - Always off + /// @li 01 - Always on + /// @li 11 - Use previous + /// + UINT8 StressResetMode; ///< StressResetMode 01-10 + /// @li 00 - Disabed + /// @li 01 - Io Write 0x64 with 0xfe + /// @li 10 - Io Write 0xcf9 with 0x06 + /// @li 11 - Io Write 0xcf9 with 0x0e + /// + BOOLEAN MtC1eEnable; /// MtC1eEnable - Enable MtC1e + VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table + UINT8 SpreadSpectrumOptions; /// SpreadSpectrumOptions - Spread Spectrum Option +} FCH_ACPI; + + +/// +/// HWM temp parameter structure +/// +typedef struct _FCH_HWM_TEMP_PAR { + UINT16 At; ///< At + UINT16 Ct; ///< Ct + UINT8 Mode; ///< Mode BIT0:HiRatio BIT1:HiCurrent +} FCH_HWM_TEMP_PAR; + +/// +/// HWM Current structure +/// +typedef struct _FCH_HWM_CUR { + UINT16 FanSpeed[5]; ///< FanSpeed - fan Speed + UINT16 Temperature[5]; ///< Temperature - temperature + UINT16 Voltage[8]; ///< Voltage - voltage +} FCH_HWM_CUR; + +/// +/// HWM fan control structure +/// +typedef struct _FCH_HWM_FAN_CTR { + UINT8 InputControlReg00; /// Fan Input Control register, PM2 offset [0:4]0 + UINT8 ControlReg01; /// Fan control register, PM2 offset [0:4]1 + UINT8 FreqReg02; /// Fan frequency register, PM2 offset [0:4]2 + UINT8 LowDutyReg03; /// Low Duty register, PM2 offset [0:4]3 + UINT8 MedDutyReg04; /// Med Duty register, PM2 offset [0:4]4 + UINT8 MultiplierReg05; /// Multiplier register, PM2 offset [0:4]5 + UINT16 LowTempReg06; /// Low Temp register, PM2 offset [0:4]6 + UINT16 MedTempReg08; /// Med Temp register, PM2 offset [0:4]8 + UINT16 HighTempReg0A; /// High Temp register, PM2 offset [0:4]A + UINT8 LinearRangeReg0C; /// Linear Range register, PM2 offset [0:4]C + UINT8 LinearHoldCountReg0D; /// Linear Hold Count register, PM2 offset [0:4]D +} FCH_HWM_FAN_CTR; + +/// +/// Hwm structure +/// +typedef struct _FCH_HWM { + UINT8 HwMonitorEnable; ///< HwMonitorEnable + UINT32 HwmControl; ///< hwmControl + /// @par + /// HWM control configuration + /// @li 0 - HWM is Enabled + /// @li 1 - IMC is Enabled + /// + UINT8 FanSampleFreqDiv; ///< Sampling rate of Fan Speed + /// @li 00 - Base(22.5KHz) + /// @li 01 - Base(22.5KHz)/2 + /// @li 10 - Base(22.5KHz)/4 + /// @li 11 - Base(22.5KHz)/8 + /// + UINT8 HwmFchtsiAutoPoll; ///< TSI Auto Polling + /// @li 0 - disable + /// @li 1 - enable + /// + UINT8 HwmFchtsiAutoPollStarted; ///< HwmSbtsiAutoPollStarted + UINT8 FanLinearEnhanceEn; ///< FanLinearEnhanceEn + UINT8 FanLinearHoldFix; ///< FanLinearHoldFix + UINT8 FanLinearRangeOutLimit; ///< FanLinearRangeOutLimit + UINT16 HwmCalibrationFactor; /// Calibration Factor + FCH_HWM_CUR HwmCurrent; /// HWM Current structure + FCH_HWM_CUR HwmCurrentRaw; /// HWM Current Raw structure + FCH_HWM_TEMP_PAR HwmTempPar[5]; /// HWM Temp parameter structure + FCH_HWM_FAN_CTR HwmFanControl[5]; /// HWM Fan Control structure + FCH_HWM_FAN_CTR HwmFanControlCooked[5]; /// HWM Fan Control structure +} FCH_HWM; + + +/// +/// Gec structure +/// +typedef struct { + BOOLEAN GecEnable; ///< GecEnable - GEC function switch + UINT8 GecPhyStatus; /// GEC PHY Status + UINT8 GecPowerPolicy; /// GEC Power Policy + /// @li 00 - GEC is powered down in S3 and S5 + /// @li 01 - GEC is powered down only in S5 + /// @li 10 - GEC is powered down only in S3 + /// @li 11 - GEC is never powered down + /// + UINT8 GecDebugBus; /// GEC Debug Bus + /// @li 0 - disable + /// @li 1 - enable + /// + UINT32 GecShadowRomBase; ///< GecShadowRomBase + /// @par + /// GEC (NIC) SHADOWROM BASE Address + /// + VOID *PtrDynamicGecRomAddress; /// Pointer of Dynamic GEC ROM Address +} FCH_GEC; + + +/// +/// _ABTblEntry - AB link register table R/W structure +/// +typedef struct _AB_TBL_ENTRY { + UINT8 RegType; /// RegType : AB Register Type (ABCFG, AXCFG and so on) + UINT32 RegIndex; /// RegIndex : AB Register Index + UINT32 RegMask; /// RegMask : AB Register Mask + UINT32 RegData; /// RegData : AB Register Data +} AB_TBL_ENTRY; + +/// +/// AB structure +/// +typedef struct { + BOOLEAN AbMsiEnable; ///< ABlink MSI capability + UINT8 ALinkClkGateOff; /// Alink Clock Gate-Off function - 0:disable, 1:enable *KR + UINT8 BLinkClkGateOff; /// Blink Clock Gate-Off function - 0:disable, 1:enable *KR + UINT8 AbClockGating; /// AB Clock Gating - 0:disable, 1:enable *KR + UINT8 GppClockGating; /// GPP Clock Gating - 0:disable, 1:enable + UINT8 UmiL1TimerOverride; /// UMI L1 inactivity timer overwrite value + UINT8 UmiLinkWidth; /// UMI Link Width + UINT8 UmiDynamicSpeedChange; /// UMI Dynamic Speed Change - 0:disable, 1:enable + UINT8 PcieRefClockOverClocking; /// PCIe Ref Clock OverClocking value + UINT8 UmiGppTxDriverStrength; /// UMI GPP TX Driver Strength + BOOLEAN NbSbGen2; /// UMI link Gen2 - 0:Gen1, 1:Gen2 + UINT8 PcieOrderRule; /// PCIe Order Rule - 0:disable, 1:enable *KR AB Posted Pass Non-Posted + UINT8 SlowSpeedAbLinkClock; /// Slow Speed AB Link Clock - 0:disable, 1:enable *KR + BOOLEAN ResetCpuOnSyncFlood; /// Reset Cpu On Sync Flood - 0:disable, 1:enable *KR + BOOLEAN AbDmaMemoryWrtie3264B; /// AB DMA Memory Write 32/64 BYTE Support *KR only + BOOLEAN AbMemoryPowerSaving; /// AB Memory Power Saving *KR only + BOOLEAN SbgDmaMemoryWrtie3264ByteCount; /// SBG DMA Memory Write 32/64 BYTE Count Support *KR only + BOOLEAN SbgMemoryPowerSaving; /// SBG Memory Power Saving *KR only +} FCH_AB; + + +/** + * PCIE_CAP_ID - PCIe Cap ID + * + */ +#define PCIE_CAP_ID 0x10 + +/// +/// FCH_GPP_PORT_CONFIG - Fch GPP port config structure +/// +typedef struct { + BOOLEAN PortPresent; ///< Port connection + /// @par + /// @li 0 - Port doesn't have slot. No need to train the link + /// @li 1 - Port connection defined and needs to be trained + /// + BOOLEAN PortDetected; ///< Link training status + /// @par + /// @li 0 - EP not detected + /// @li 1 - EP detected + /// + BOOLEAN PortIsGen2; ///< Port link speed configuration + /// @par + /// @li 00 - Auto + /// @li 01 - Forced GEN1 + /// @li 10 - Forced GEN2 + /// @li 11 - Reserved + /// + BOOLEAN PortHotPlug; ///< Support hot plug? + /// @par + /// @li 0 - No support + /// @li 1 - support + /// + UINT8 PortMisc; /// PortMisc - Reserved +} FCH_GPP_PORT_CONFIG; + +/// +/// GPP structure +/// +typedef struct { + FCH_GPP_PORT_CONFIG PortCfg[4]; /// GPP port configuration structure + GPP_LINKMODE GppLinkConfig; ///< GppLinkConfig - PCIE_GPP_Enable[3:0] + /// @li 0000 - Port ABCD -> 4:0:0:0 + /// @li 0010 - Port ABCD -> 2:2:0:0 + /// @li 0011 - Port ABCD -> 2:1:1:0 + /// @li 0100 - Port ABCD -> 1:1:1:1 + /// + BOOLEAN GppFunctionEnable; ///< GPP Function - 0:disable, 1:enable + BOOLEAN GppToggleReset; ///< Toggle GPP core reset + UINT8 GppHotPlugGeventNum; ///< Hotplug GEVENT # - valid value 0-31 + UINT8 GppFoundGfxDev; ///< Gpp Found Gfx Device + /// @li 0 - Not found + /// @li 1 - Found + /// + BOOLEAN GppGen2; ///< GPP Gen2 - 0:disable, 1:enable + UINT8 GppGen2Strap; ///< GPP Gen2 Strap - 0:disable, 1:enable, FCH itself uses this + BOOLEAN GppMemWrImprove; ///< GPP Memory Write Improve - 0:disable, 1:enable + BOOLEAN GppUnhidePorts; ///< GPP Unhide Ports - 0:disable, 1:enable + UINT8 GppPortAspm; ///< GppPortAspm - ASPM state for all GPP ports + /// @li 01 - Disabled + /// @li 01 - L0s + /// @li 10 - L1 + /// @li 11 - L0s + L1 + /// + BOOLEAN GppLaneReversal; ///< GPP Lane Reversal - 0:disable, 1:enable + BOOLEAN GppPhyPllPowerDown; ///< GPP PHY PLL Power Down - 0:disable, 1:enable + BOOLEAN GppDynamicPowerSaving; ///< GPP Dynamic Power Saving - 0:disable, 1:enable + BOOLEAN PcieAer; ///< PcieAer - Advanced Error Report: 0/1-disable/enable + BOOLEAN PcieRas; ///< PCIe RAS - 0:disable, 1:enable + BOOLEAN PcieCompliance; ///< PCIe Compliance - 0:disable, 1:enable + BOOLEAN PcieSoftwareDownGrade; ///< PCIe Software Down Grade + BOOLEAN UmiPhyPllPowerDown; ///< UMI PHY PLL Power Down - 0:disable, 1:enable + BOOLEAN SerialDebugBusEnable; ///< Serial Debug Bus Enable + UINT8 GppHardwareDownGrade; ///< GppHardwareDownGrade - Gpp HW Down Grade function 0:Disable, 1-4: portA-D + UINT8 GppL1ImmediateAck; ///< GppL1ImmediateAck - Gpp L1 Immediate ACK 0: enable, 1: disable + BOOLEAN NewGppAlgorithm; ///< NewGppAlgorithm - New GPP procedure + UINT8 HotPlugPortsStatus; ///< HotPlugPortsStatus - Save Hot-Plug Ports Status + UINT8 FailPortsStatus; ///< FailPortsStatus - Save Failure Ports Status + UINT8 GppPortMinPollingTime; ///< GppPortMinPollingTime - Min. Polling time for Gpp Port Training + BOOLEAN IsCapsuleMode; ///< IsCapsuleMode - Support Capsule Mode in FCH +} FCH_GPP; + +/// FCH USB Over Current Data Block +typedef struct { + UINT8 Usb1OcPinMap[5]; ///< USB1 over current pin mapping + UINT8 Usb2OcPinMap[5]; ///< USB2 over current pin mapping + UINT8 Usb3OcPinMap[4]; ///< USB3 over current pin mapping + UINT8 Usb4OcPinMap[2]; ///< USB4 over current pin mapping + UINT8 Xhci0OcPinMap[2]; ///< XHCI0 over current pin mapping + UINT8 Xhci1OcPinMap[2]; ///< XHCI1 over current pin mapping +} FCH_USB_OC; + + +/// +/// FCH USB sturcture +/// +typedef struct { + BOOLEAN Ohci1Enable; ///< OHCI1 controller enable + BOOLEAN Ohci2Enable; ///< OHCI2 controller enable + BOOLEAN Ohci3Enable; ///< OHCI3 controller enable + BOOLEAN Ohci4Enable; ///< OHCI4 controller enable + BOOLEAN Ehci1Enable; ///< EHCI1 controller enable + BOOLEAN Ehci2Enable; ///< EHCI2 controller enable + BOOLEAN Ehci3Enable; ///< EHCI3 controller enable + BOOLEAN Xhci0Enable; ///< XHCI0 controller enable + BOOLEAN Xhci1Enable; ///< XHCI1 controller enable + BOOLEAN UsbMsiEnable; ///< USB MSI capability + UINT32 OhciSsid; ///< OHCI SSID + UINT32 Ohci4Ssid; ///< OHCI 4 SSID + UINT32 EhciSsid; ///< EHCI SSID + UINT32 XhciSsid; ///< XHCI SSID + BOOLEAN UsbPhyPowerDown; ///< USB PHY Power Down - 0:disable, 1:enable + UINT32 UserDefineXhciRomAddr; ///< XHCI ROM address define by platform BIOS + UINT8 Ehci1Phy[5]; ///< EHCI1 USB PHY Driving Strength value table + UINT8 Ehci2Phy[5]; ///< EHCI2 USB PHY Driving Strength value table + UINT8 Ehci3Phy[4]; ///< EHCI3 USB PHY Driving Strength value table + UINT8 Xhci20Phy[4]; ///< XHCI USB 2.0 PHY Driving Strength value table + UINT8 Ehci1DebugPortSel; ///< DebugPortSel for Ehci1 Hub + /// @li 000 - Disable + /// @li 001 - HubDownStreamPort0 + /// @li 010 - HubDownStreamPort1 + /// @li 011 - HubDownStreamPort2 + /// @li 100 - HubDownStreamPort3 + UINT8 Ehci2DebugPortSel; ///< DebugPortSel for Ehci2 Hub + /// @li 000 - Disable + /// @li 001 - HubDownStreamPort0 + /// @li 010 - HubDownStreamPort1 + /// @li 011 - HubDownStreamPort2 + /// @li 100 - HubDownStreamPort3 + UINT8 Ehci3DebugPortSel; ///< DebugPortSel for Ehci3 Hub + /// @li 000 - Disable + /// @li 001 - HubDownStreamPort0 + /// @li 010 - HubDownStreamPort1 + /// @li 011 - HubDownStreamPort2 + /// @li 100 - HubDownStreamPort3 + FCH_USB_OC FchUsbOcMap; ///< Fch USB OC Map +} FCH_USB; + + +/// Private: FCH_DATA_BLOCK_RESET +typedef struct _FCH_RESET_DATA_BLOCK { + AMD_CONFIG_PARAMS *StdHeader; ///< Header structure + FCH_RESET_INTERFACE FchReset; ///< Reset interface + + UINT8 FastSpeed; ///< SPI FastSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz + UINT8 WriteSpeed; ///< SPI Write Speed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz + UINT8 Mode; ///< SPI Mode + /// @li 101 - Qual-io 1-4-4 + /// @li 100 - Dual-io 1-2-2 + /// @li 011 - Qual-io 1-1-4 + /// @li 010 - Dual-io 1-1-2 + /// @li 111 - FastRead + /// @li 110 - Normal + /// + UINT8 AutoMode; ///< SPI Auto Mode - 0:disable, 1:enable + UINT8 BurstWrite; ///< SPI Burst Write - 0:disable, 1:enable + BOOLEAN Sata6AhciCap; ///< SATA 6 AHCI Capability - TRUE:enable, FALSE:disable + UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable + BOOLEAN EcKbd; ///< EC KBD - 0:disable, 1:enable + BOOLEAN LegacyFree; ///< Legacy Free - 0:disable, 1:enable + BOOLEAN SataSetMaxGen2; ///< SATA enable maximum GEN2 + UINT8 SataClkMode; ///< SATA reference clock selector and divider + UINT8 SataModeReg; ///< Output: SATAConfig PMIO:0xDA + BOOLEAN SataInternal100Spread; ///< SATA internal 100MHz spread ON/OFF + UINT8 SpiSpeed; ///< SPI NormSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz +// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38 +// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C +// UINT8 SpiProtectEn0_1d_34; /// + UINT8 SPI100_Enable; /// + BOOLEAN EcChannel0; ///< Enable EC channel 0 + FCH_GPP Gpp; ///< GPP subsystem + FCH_SPI Spi; ///< SPI subsystem + BOOLEAN QeEnabled; /// Quad Mode Enabled + BOOLEAN FchOscout1ClkContinous; ///< FCH OSCOUT1_CLK Continous + VOID* EarlyOemGpioTable; /// Pointer of Early OEM GPIO table +// VOID* OemSpiDeviceTable; /// Pointer of OEM Spi Device table + VOID* OemResetProgrammingTablePtr; /// Pointer of ACPI OEM table +} FCH_RESET_DATA_BLOCK; + + +/// Private: FCH_DATA_BLOCK +typedef struct _FCH_DATA_BLOCK { + AMD_CONFIG_PARAMS *StdHeader; ///< Header structure + + FCH_ACPI HwAcpi; ///< ACPI structure + FCH_AB Ab; ///< AB structure + FCH_GPP Gpp; ///< GPP structure + FCH_USB Usb; ///< USB structure + FCH_SATA Sata; ///< SATA structure + FCH_SMBUS Smbus; ///< SMBus structure + FCH_IDE Ide; ///< IDE structure + FCH_AZALIA Azalia; ///< Azalia structure + FCH_SPI Spi; ///< SPI structure + FCH_PCIB Pcib; ///< PCIB structure + FCH_GEC Gec; ///< GEC structure + FCH_SD Sd; ///< SD structure + FCH_HWM Hwm; ///< Hardware Moniter structure + FCH_IR Ir; ///< IR structure + FCH_HPET Hpet; ///< HPET structure + FCH_GCPU Gcpu; ///< GCPU structure + FCH_IMC Imc; ///< IMC structure + FCH_MISC Misc; ///< MISC structure + VOID* PostOemGpioTable; /// Pointer of Post OEM GPIO table +} FCH_DATA_BLOCK; + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchDef.h new file mode 100644 index 0000000000..13906c5be8 --- /dev/null +++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchDef.h @@ -0,0 +1,400 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH routine definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $ + * + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _FCH_DEF_H_ +#define _FCH_DEF_H_ + + +UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); +VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); +VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); +VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); +VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl); +VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); +VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader); +VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader); +UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader); +UINT8 ReadFchChipsetRevision (IN AMD_CONFIG_PARAMS *StdHeader); +UINT8 GetFchRevision (IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN CheckAvalonRevisionA0 (IN AMD_CONFIG_PARAMS *StdHeader); + +/// +/// Fch Ab Routines +/// +/// Pei Phase +/// +VOID FchInitResetAb (IN VOID* FchDataPtr); +VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvAb (IN VOID* FchDataPtr); +VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr); +VOID FchInitMidAb (IN VOID* FchDataPtr); +VOID FchInitLateAb (IN VOID* FchDataPtr); +/// +/// Other Public Routines +/// +VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr); +BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchAbLateProgram (IN VOID* FchDataPtr); +VOID ProgramPcieNativeMode (IN VOID* FchDataPtr); + +/// +/// Fch Azalia Routines +/// +/// Pei Phase +/// +VOID FchInitResetAzalia (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvAzalia (IN VOID *FchDataPtr); +VOID FchInitMidAzalia (IN VOID *FchDataPtr); +VOID FchInitLateAzalia (IN VOID *FchDataPtr); + +/// +/// Fch HwAcpi Routines +/// +/// Pei Phase +/// +VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr); +VOID FchInitResetHwAcpi (IN VOID *FchDataPtr); +VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr); +VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr); +VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr); +VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr); +VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr); +VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr); +VOID FchInitMidHwAcpi (IN VOID *FchDataPtr); +VOID FchInitLateHwAcpi (IN VOID *FchDataPtr); + +/// +/// Other Public Routines +/// +VOID HpetInit (IN VOID *FchDataPtr); +VOID C3PopupSetting (IN VOID *FchDataPtr); +VOID MtC1eEnable (IN VOID *FchDataPtr); +VOID GcpuRelatedSetting (IN VOID *FchDataPtr); +VOID StressResetModeLate (IN VOID *FchDataPtr); + +/// +/// Fch Hwm Routines +/// +/// Pei Phase +/// +VOID FchInitResetHwm (IN VOID* FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvHwm (IN VOID* FchDataPtr); +VOID FchInitMidHwm (IN VOID* FchDataPtr); +VOID FchInitLateHwm (IN VOID* FchDataPtr); +/// +/// Other Public Routines +/// +VOID HwmInitRegister (IN VOID* FchDataPtr); +VOID HwmProcessParameter (IN VOID* FchDataPtr); +VOID HwmSetRegister (IN VOID* FchDataPtr); +VOID HwmGetCalibrationFactor (IN VOID* FchDataPtr); +VOID HwmFchtsiAutoPolling (IN VOID* FchDataPtr); +VOID HwmGetRawData (IN VOID* FchDataPtr); +VOID HwmCaculate (IN VOID* FchDataPtr); +VOID HwmFchtsiAutoPollingOff (IN VOID* FchDataPtr); +VOID FchECfancontrolservice (IN VOID* FchDataPtr); + +/// +/// Fch Imc Routines +/// +/// Pei Phase +/// +VOID FchInitResetImc (IN VOID *FchDataPtr); +VOID FchInitResetEc (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvImc (IN VOID *FchDataPtr); +VOID FchInitMidImc (IN VOID *FchDataPtr); +VOID FchInitLateImc (IN VOID *FchDataPtr); +VOID FchInitEnvEc (IN VOID *FchDataPtr); +VOID FchInitMidEc (IN VOID *FchDataPtr); +VOID FchInitLateEc (IN VOID *FchDataPtr); +/// +/// Other Public Routines +/// +VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader); +VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader); + +VOID ImcSleep (IN VOID *FchDataPtr); +VOID ImcEnableSurebootTimer (IN VOID *FchDataPtr); +VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr); +VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr); +VOID ImcWakeup (IN VOID *FchDataPtr); +VOID ImcIdle (IN VOID *FchDataPtr); +BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr); +VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr); +VOID ImcCrashReset (IN VOID *FchDataPtr); +VOID SoftwareDisableImc (IN VOID *FchDataPtr); + + +/// +/// Fch Ir Routines +/// +/// Dxe Phase +/// +VOID FchInitEnvIr (IN VOID* FchDataPtr); +VOID FchInitMidIr (IN VOID* FchDataPtr); +VOID FchInitLateIr (IN VOID* FchDataPtr); + +/// +/// Fch SATA Routines +/// +/// Pei Phase +/// +VOID FchInitResetSata (IN VOID *FchDataPtr); +VOID FchInitResetSataProgram (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitMidSata (IN VOID *FchDataPtr); +VOID FchInitEnvSata (IN VOID *FchDataPtr); +VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr); +VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr); +VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr); + +VOID FchInitLateSata (IN VOID *FchDataPtr); +VOID FchInitEnvSataIde (IN VOID *FchDataPtr); +VOID FchInitMidSataIde (IN VOID *FchDataPtr); +VOID FchInitLateSataIde (IN VOID *FchDataPtr); +VOID FchInitEnvSataAhci (IN VOID *FchDataPtr); +VOID FchInitMidSataAhci (IN VOID *FchDataPtr); +VOID FchInitLateSataAhci (IN VOID *FchDataPtr); +VOID FchInitEnvSataRaid (IN VOID *FchDataPtr); +VOID FchInitMidSataRaid (IN VOID *FchDataPtr); +VOID FchInitLateSataRaid (IN VOID *FchDataPtr); +VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr); +VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr); +VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr); + +VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader); +VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); +VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader); +VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader); +VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5); +VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5); +VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); +VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); +VOID FchSataGpioInitial (IN VOID *FchDataPtr); +VOID SataBar5RegSet (IN VOID *FchDataPtr); +VOID SataSetPortGenMode (IN VOID *FchDataPtr); +VOID FchSataSetPortGenMode (IN VOID *FchDataPtr); +VOID FchProgramSataPhy (IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchSataDriveFpga (IN VOID *FchDataPtr); +VOID FchInitEnvSataRaidProgram (IN VOID *FchDataPtr); + +/// +/// FCH USB Controller Public Function +/// +/// Pei Phase +/// +VOID FchInitResetUsb (IN VOID *FchDataPtr); +VOID FchInitResetEhci (IN VOID *FchDataPtr); +VOID FchInitResetXhci (IN VOID *FchDataPtr); +VOID FchInitResetXhciProgram (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvUsb (IN VOID *FchDataPtr); +VOID FchInitMidUsb (IN VOID *FchDataPtr); +VOID FchInitLateUsb (IN VOID *FchDataPtr); +VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr); +VOID FchInitMidUsbEhci (IN VOID *FchDataPtr); +VOID FchInitLateUsbEhci (IN VOID *FchDataPtr); +VOID FchEhciDebugPortService (IN VOID *FchDataPtr); +VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr); +VOID FchInitMidUsbXhci (IN VOID *FchDataPtr); +VOID FchInitLateUsbXhci (IN VOID *FchDataPtr); +VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitMidUsbEhci2 (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitMidUsbEhci3 (IN FCH_DATA_BLOCK *FchDataPtr); +/// +/// Other Public Routines +/// +VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr); +VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr); +UINT8 FchUsbCommonPhyCalibration (IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchUsbOverCurrentControl (IN VOID *FchDataPtr); + +/// +/// Fch Sd Routines +/// +VOID FchInitEnvSd (IN VOID *FchDataPtr); +VOID FchInitMidSd (IN VOID *FchDataPtr); +VOID FchInitLateSd (IN VOID *FchDataPtr); + +/// +/// Other Public Routines +/// + +VOID FchInitEnvSdProgram (IN VOID *FchDataPtr); + +/// +/// Fch Spi Routines +/// +/// Pei Phase +/// +VOID FchInitResetSpi (IN VOID *FchDataPtr); +VOID FchInitResetLpc (IN VOID *FchDataPtr); +VOID FchInitResetLpcProgram (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvSpi (IN VOID *FchDataPtr); +VOID FchInitMidSpi (IN VOID *FchDataPtr); +VOID FchInitLateSpi (IN VOID *FchDataPtr); +VOID FchInitEnvLpc (IN VOID *FchDataPtr); +VOID FchInitMidLpc (IN VOID *FchDataPtr); +VOID FchInitLateLpc (IN VOID *FchDataPtr); +VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr); +/// +/// Other Public Routines +/// +VOID FchSpiUnlock (IN VOID *FchDataPtr); +VOID FchSpiLock (IN VOID *FchDataPtr); + +/*--------------------------- Documentation Pages ---------------------------*/ +VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader); +VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader); +VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader); +VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader); +VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID TurnOffCG2 (OUT VOID); +VOID BackUpCG2 (OUT VOID); +VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length); +VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadXhci1Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID AcLossControl (IN UINT8 AcLossControlValue); +VOID FchVgaInit (OUT VOID); +VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr); +VOID ValidateFchVariant (IN VOID *FchDataPtr); +VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader); +VOID ClearAllSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN IsGCPU (IN VOID *FchDataPtr); +BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr); +VOID SbSleepTrapControl (IN BOOLEAN SleepTrap); + +AGESA_STATUS +FchSpiTransfer ( + IN UINT8 PrefixCode, + IN UINT8 Opcode, + IN OUT UINT8 *DataPtr, + IN UINT8 *AddressPtr, + IN UINT8 Length, + IN BOOLEAN WriteFlag, + IN BOOLEAN AddressFlag, + IN BOOLEAN DataFlag, + IN BOOLEAN FinishedFlag + ); + +BOOLEAN +FchConfigureSpiDeviceDummyCycle ( + IN UINT32 DeviceID, + IN UINT8 SpiMode + ); + +UINT32 +FchReadSpiId ( + IN BOOLEAN Flag + ); + + +BOOLEAN +FchPlatformSpiQe ( + IN VOID *FchDataPtr + ); + +#endif + -- cgit v1.2.3