From 9ef6e52353dbbcfac727e0207dbbcc07dfb75d47 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Tue, 20 Sep 2016 20:16:20 -0600 Subject: vendorcode/amd: Copy 00660F01 directory to 00670F00 Prepare for new 00670FF00 support. Original-Signed-off-by: Marc Jones Original-Reviewed-by: Marshall Dawson Original-Tested-by: Marshall Dawson (cherry picked from commit ca53cac5c847c55e56ad6f5feb382c04f33ae77a) Change-Id: Ib48b1611bf70ec302c50f6e07bd2b3d9b09e0a24 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/17193 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/vendorcode/amd/pi/00670F00/Include/Filecode.h | 648 +++++++++ .../amd/pi/00670F00/Include/GeneralServices.h | 222 +++ src/vendorcode/amd/pi/00670F00/Include/Ids.h | 1484 ++++++++++++++++++++ src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h | 145 ++ src/vendorcode/amd/pi/00670F00/Include/Options.h | 68 + .../00670F00/Include/PlatformMemoryConfiguration.h | 530 +++++++ src/vendorcode/amd/pi/00670F00/Include/Topology.h | 86 ++ 7 files changed, 3183 insertions(+) create mode 100644 src/vendorcode/amd/pi/00670F00/Include/Filecode.h create mode 100644 src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h create mode 100644 src/vendorcode/amd/pi/00670F00/Include/Ids.h create mode 100644 src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h create mode 100644 src/vendorcode/amd/pi/00670F00/Include/Options.h create mode 100644 src/vendorcode/amd/pi/00670F00/Include/PlatformMemoryConfiguration.h create mode 100644 src/vendorcode/amd/pi/00670F00/Include/Topology.h (limited to 'src/vendorcode/amd/pi/00670F00/Include') diff --git a/src/vendorcode/amd/pi/00670F00/Include/Filecode.h b/src/vendorcode/amd/pi/00670F00/Include/Filecode.h new file mode 100644 index 0000000000..0e01812626 --- /dev/null +++ b/src/vendorcode/amd/pi/00670F00/Include/Filecode.h @@ -0,0 +1,648 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Collectively assign unique filecodes for assert and debug to each source file. + * + * Publish values for decorated filenames, which can be used for + * ASSERT and debug support using a preprocessor define like: + * @n \#define FILECODE MY_C_FILENAME_FILECODE @n + * This file serves as a reference for debugging to associate the code and filename. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $ + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _FILECODE_H_ +#define _FILECODE_H_ + +#define UNASSIGNED_FILE_FILECODE (0xFFFF) + +/// For debug use in any Platform's options C file. +/// Can be reused for platforms and image builds, since only one options file can be built. +#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB) + + +#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001) +#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017) +#define PROC_GNB_GNBINITATENV_FILECODE (0xA020) +#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021) +#define PROC_GNB_GNBINITATMID_FILECODE (0xA022) +#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023) +#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030) +#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031) +#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032) +#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE (0xA033) +#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036) +#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037) +#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038) +#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049) +#define PROC_GNB_MODULES_GNBPCIECOMMCLKCFG_PCIECOMMCLKCFG_FILECODE (0xA04C) + +#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E) +#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F) +#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE (0xA090) +#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE (0xA093) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6) +#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE (0xA0A7) +#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE (0xA0A8) +#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE (0xA0A9) +#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE (0xA0AA) + +#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE (0xA0BA) +#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE (0xA0BB) +#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE (0xA0BC) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBTIMERLIB_FILECODE (0xA0BD) +#define PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE (0xA0BF) +#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE (0xA0C0) +#define PROC_GNB_MODULES_GNBPCIEASPM_PCIEASPM_FILECODE (0xA0C2) + +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEASPMEXITLATENCYV5_FILECODE (0xA0C5) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE (0xA0C6) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE (0xA0C7) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE (0xA0C8) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA) +#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE (0xA0CB) + +#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE (0xA0DB) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE (0xA0DC) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE (0xA0DD) + +#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE (0xA0E0) + +#define PROC_GNB_MODULES_GNBIOAPIC_GNBIOAPIC_FILECODE (0xA0EE) + +#define PROC_GNB_MODULES_GNBPCIEMAXPAYLOAD_PCIEMAXPAYLOAD_FILECODE (0xA0F4) +#define PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE (0xA0F5) + +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIETOPOLOGYSERVICESV5_FILECODE (0xA100) +#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIETRAININGV2_FILECODE (0xA101) +#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIEWORKAROUNDSV2_FILECODE (0xA102) + +#define PROC_GNB_MODULES_GNBINITCZ_ALIBCZ_FILECODE (0xA202) +#define PROC_GNB_MODULES_GNBINITCZ_GFXENVINITCZ_FILECODE (0xA203) +#define PROC_GNB_MODULES_GNBINITCZ_GFXGMCINITCZ_FILECODE (0xA204) +#define PROC_GNB_MODULES_GNBINITCZ_GFXINTEGRATEDINFOTABLECZ_FILECODE (0xA205) +#define PROC_GNB_MODULES_GNBINITCZ_GFXLIBCZ_FILECODE (0xA206) +#define PROC_GNB_MODULES_GNBINITCZ_GFXMIDINITCZ_FILECODE (0xA207) +#define PROC_GNB_MODULES_GNBINITCZ_GFXPOSTINITCZ_FILECODE (0xA208) +#define PROC_GNB_MODULES_GNBINITCZ_GNBEARLYINITCZ_FILECODE (0xA209) +#define PROC_GNB_MODULES_GNBINITCZ_GNBENVINITCZ_FILECODE (0xA20A) +#define PROC_GNB_MODULES_GNBINITCZ_GNBFUSETABLECZ_FILECODE (0xA20B) +#define PROC_GNB_MODULES_GNBINITCZ_GNBIOMMUIVRSCZ_FILECODE (0xA20C) +#define PROC_GNB_MODULES_GNBINITCZ_GNBMIDINITCZ_FILECODE (0xA20D) +#define PROC_GNB_MODULES_GNBINITCZ_GNBPOSTINITCZ_FILECODE (0xA20E) +#define PROC_GNB_MODULES_GNBINITCZ_GNBREGISTERACCCZ_FILECODE (0xA20F) +#define PROC_GNB_MODULES_GNBINITCZ_GNBURATOKENMAPCZ_FILECODE (0xA211) +#define PROC_GNB_MODULES_GNBINITCZ_PCIECOMPLEXDATACZ_FILECODE (0xA212) +#define PROC_GNB_MODULES_GNBINITCZ_PCIECONFIGCZ_FILECODE (0xA213) +#define PROC_GNB_MODULES_GNBINITCZ_PCIEEARLYINITCZ_FILECODE (0xA214) +#define PROC_GNB_MODULES_GNBINITCZ_PCIEENVINITCZ_FILECODE (0xA215) +#define PROC_GNB_MODULES_GNBINITCZ_PCIELIBCZ_FILECODE (0xA216) +#define PROC_GNB_MODULES_GNBINITCZ_PCIEMIDINITCZ_FILECODE (0xA217) +#define PROC_GNB_MODULES_GNBINITCZ_PCIEPOSTINITCZ_FILECODE (0xA218) +#define PROC_GNB_MODULES_GNBINITCZ_PCIEPOWERGATECZ_FILECODE (0xA219) +#define PROC_GNB_MODULES_GNBINITCZ_GNBURACZ_FILECODE (0xA21A) +#define PROC_GNB_MODULES_GNBSMULIBV8_GNBSMUINITLIBV8_FILECODE (0xA21B) +#define PROC_GNB_MODULES_GNBINITCZ_PCIEARIINITCZ_FILECODE (0xA21C) +#define PROC_GNB_MODULES_GNBINITCZ_GNBBOOTTIMECALCZ_FILECODE (0xA21D) +#define PROC_GNB_MODULES_GNBINITCZ_GNBPSPCZ_FILECODE (0xA21E) +#define PROC_GNB_MODULES_GNBINITCZ_GNBSMUINITCZ_FILECODE (0xA21F) + +#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01) +#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02) +#define PROC_GNB_GNBINITATRTB_FILECODE (0xAE03) +#define PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE (0xAE04) + +#define PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE (0xAE18) + +#define PROC_GNB_MODULES_GNBPCIEALIBV2_PCIEALIBV2_FILECODE (0xAE33) +#define PROC_GNB_MODULES_GNBURALIBV1_GNBURALIBV1_FILECODE (0xAE3A) +#define PROC_GNB_MODULES_GNBGFXINTTABLEV5_GFXLIBV5_FILECODE (0xAE41) +#define PROC_GNB_MODULES_GNBGFXINTTABLEV5_GFXINTEGRATEDINFOTABLEV5_FILECODE (0xAE42) +#define PROC_GNB_MODULES_GNBGFXINTTABLEV5_GFXPWRPLAYTABLEV5_FILECODE (0xAE43) +#define PROC_GNB_MODULES_GNBAZALIALIB_GNBAZALIALIB_FILECODE (0xAE44) + +// FCH +#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010) +#define PROC_FCH_COMMON_FCHLIB_FILECODE (0xB011) +#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012) +#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013) +#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014) +#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015) +#define PROC_FCH_COMMON_FCHPELIB_FILECODE (0xB016) + +#define UEFI_SMM_MEMSMMLIB_MEMSMMLIB_FILECODE (0xB2C1) +#define UEFI_SMM_MEMSMMLIB_CZ_DRAMMAPCZ_FILECODE (0xB2C3) +#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIARESET_FILECODE (0xB400) +#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIAENV_FILECODE (0xB401) +#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIAMID_FILECODE (0xB402) +#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIALATE_FILECODE (0xB403) +#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIRESET_FILECODE (0xB410) +#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIENV_FILECODE (0xB411) +#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIMID_FILECODE (0xB412) +#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPILATE_FILECODE (0xB413) +#define PROC_FCH_KERN_KERNHWACPI_KERNSSSERVICE_FILECODE (0xB414) +#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIENVSERVICE_FILECODE (0xB415) +#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIMIDSERVICE_FILECODE (0xB416) +#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPILATESERVICE_FILECODE (0xB417) +#define PROC_FCH_KERN_KERNHWM_KERNHWMRESET_FILECODE (0xB420) +#define PROC_FCH_KERN_KERNHWM_KERNHWMENV_FILECODE (0xB421) +#define PROC_FCH_KERN_KERNHWM_KERNHWMMID_FILECODE (0xB422) +#define PROC_FCH_KERN_KERNHWM_KERNHWMLATE_FILECODE (0xB423) +#define PROC_FCH_KERN_KERNHWM_KERNHWMENVSERVICE_FILECODE (0xB424) +#define PROC_FCH_KERN_KERNHWM_KERNHWMMIDSERVICE_FILECODE (0xB425) +#define PROC_FCH_KERN_KERNHWM_KERNHWMLATESERVICE_FILECODE (0xB426) +#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITRESET_FILECODE (0xB427) +#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITENV_FILECODE (0xB428) +#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITMID_FILECODE (0xB429) +#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITLATE_FILECODE (0xB42A) +#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITS3_FILECODE (0xB42B) +#define PROC_FCH_KERN_KERNINTERFACE_KERNINITRESETDEF_FILECODE (0xB42C) +#define PROC_FCH_KERN_KERNINTERFACE_KERNINITENVDEF_FILECODE (0xB42D) +#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHTASKLAUNCHER_FILECODE (0xB42E) +#define PROC_FCH_KERN_KERNIMC_KERNIMCRESET_FILECODE (0xB430) +#define PROC_FCH_KERN_KERNIMC_KERNIMCENV_FILECODE (0xB431) +#define PROC_FCH_KERN_KERNIMC_KERNIMCMID_FILECODE (0xB432) +#define PROC_FCH_KERN_KERNIMC_KERNIMCLATE_FILECODE (0xB433) +#define PROC_FCH_KERN_KERNIMC_KERNFCHECRESET_FILECODE (0xB434) +#define PROC_FCH_KERN_KERNIMC_KERNFCHECENV_FILECODE (0xB435) +#define PROC_FCH_KERN_KERNIMC_KERNFCHECMID_FILECODE (0xB436) +#define PROC_FCH_KERN_KERNIMC_KERNFCHECLATE_FILECODE (0xB437) +#define PROC_FCH_KERN_KERNIMC_KERNIMCLIB_FILECODE (0xB438) +#define PROC_FCH_KERN_KERNIMC_KERNIMCSERVICE_FILECODE (0xB439) +#define PROC_FCH_KERN_KERNIR_KERNIRENV_FILECODE (0xB43A) +#define PROC_FCH_KERN_KERNIR_KERNIRMID_FILECODE (0xB43B) +#define PROC_FCH_KERN_KERNIR_KERNIRLATE_FILECODE (0xB43C) +#define PROC_FCH_KERN_KERNPCIE_KERNABRESET_FILECODE (0xB440) +#define PROC_FCH_KERN_KERNPCIE_KERNABENV_FILECODE (0xB441) +#define PROC_FCH_KERN_KERNPCIE_KERNABMID_FILECODE (0xB442) +#define PROC_FCH_KERN_KERNPCIE_KERNABLATE_FILECODE (0xB443) +#define PROC_FCH_KERN_KERNPCIE_KERNABENVSERVICE_FILECODE (0xB44C) +#define PROC_FCH_KERN_KERNPCIE_KERNABRESETSERVICE_FILECODE (0xB44D) +#define PROC_FCH_KERN_KERNPCIE_KERNABSERVICE_FILECODE (0xB44E) +#define PROC_FCH_KERN_KERNSATA_KERNSATARESET_FILECODE (0xB460) +#define PROC_FCH_KERN_KERNSATA_KERNSATAENV_FILECODE (0xB461) +#define PROC_FCH_KERN_KERNSATA_KERNSATAMID_FILECODE (0xB462) +#define PROC_FCH_KERN_KERNSATA_KERNSATALATE_FILECODE (0xB463) +#define PROC_FCH_KERN_KERNSATA_KERNSATARESETSERVICE_FILECODE (0xB464) +#define PROC_FCH_KERN_KERNSATA_KERNSATAENVSERVICE_FILECODE (0xB465) +#define PROC_FCH_KERN_KERNSATA_KERNSATASERVICE_FILECODE (0xB466) +#define PROC_FCH_KERN_KERNSATA_KERNSATALIB_FILECODE (0xB467) +#define PROC_FCH_KERN_KERNSATA_KERNSATAENVLIB_FILECODE (0xB468) +#define PROC_FCH_KERN_KERNSATA_KERNAHCILIB_FILECODE (0xB469) +#define PROC_FCH_KERN_KERNSATA_KERNAHCIENV_FILECODE (0xB46A) +#define PROC_FCH_KERN_KERNSATA_KERNAHCIMID_FILECODE (0xB46B) +#define PROC_FCH_KERN_KERNSATA_KERNAHCILATE_FILECODE (0xB46C) +#define PROC_FCH_KERN_KERNSATA_KERNRAIDLIB_FILECODE (0xB46D) +#define PROC_FCH_KERN_KERNSATA_KERNRAIDENV_FILECODE (0xB46E) +#define PROC_FCH_KERN_KERNSATA_KERNRAIDMID_FILECODE (0xB46F) +#define PROC_FCH_KERN_KERNSATA_KERNRAIDLATE_FILECODE (0xB470) +#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCILIB_FILECODE (0xB471) +#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCIENV_FILECODE (0xB472) +#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCIMID_FILECODE (0xB473) +#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCILATE_FILECODE (0xB474) +#define PROC_FCH_KERN_KERNSATA_KERNSATAIDELIB_FILECODE (0xB475) +#define PROC_FCH_KERN_KERNSATA_KERNSATAIDEENV_FILECODE (0xB476) +#define PROC_FCH_KERN_KERNSATA_KERNSATAIDEMID_FILECODE (0xB477) +#define PROC_FCH_KERN_KERNSATA_KERNSATAIDELATE_FILECODE (0xB478) +#define PROC_FCH_KERN_KERNSD_KERNSDENV_FILECODE (0xB481) +#define PROC_FCH_KERN_KERNSD_KERNSDMID_FILECODE (0xB482) +#define PROC_FCH_KERN_KERNSD_KERNSDLATE_FILECODE (0xB483) +#define PROC_FCH_KERN_KERNSD_KERNSDRESETSERVICE_FILECODE (0xB484) +#define PROC_FCH_KERN_KERNSD_KERNSDENVSERVICE_FILECODE (0xB485) +#define PROC_FCH_KERN_KERNSD_KERNSDSERVICE_FILECODE (0xB486) +#define PROC_FCH_KERN_KERNSPI_KERNSPIRESET_FILECODE (0xB490) +#define PROC_FCH_KERN_KERNSPI_KERNSPIENV_FILECODE (0xB491) +#define PROC_FCH_KERN_KERNSPI_KERNSPIMID_FILECODE (0xB492) +#define PROC_FCH_KERN_KERNSPI_KERNSPILATE_FILECODE (0xB493) +#define PROC_FCH_KERN_KERNSPI_KERNLPCRESET_FILECODE (0xB494) +#define PROC_FCH_KERN_KERNSPI_KERNLPCENV_FILECODE (0xB495) +#define PROC_FCH_KERN_KERNSPI_KERNLPCMID_FILECODE (0xB496) +#define PROC_FCH_KERN_KERNSPI_KERNLPCLATE_FILECODE (0xB497) +#define PROC_FCH_KERN_KERNSPI_KERNLPCRESETSERVICE_FILECODE (0xB498) +#define PROC_FCH_KERN_KERNSPI_KERNLPCENVSERVICE_FILECODE (0xB499) +#define PROC_FCH_KERN_KERNUSB_KERNUSBRESET_FILECODE (0xB4A0) +#define PROC_FCH_KERN_KERNUSB_KERNUSBENV_FILECODE (0xB4A1) +#define PROC_FCH_KERN_KERNUSB_KERNUSBMID_FILECODE (0xB4A2) +#define PROC_FCH_KERN_KERNUSB_KERNUSBLATE_FILECODE (0xB4A3) +#define PROC_FCH_KERN_KERNUSB_KERNEHCIRESET_FILECODE (0xB4A4) +#define PROC_FCH_KERN_KERNUSB_KERNEHCIENV_FILECODE (0xB4A5) +#define PROC_FCH_KERN_KERNUSB_KERNEHCIMID_FILECODE (0xB4A6) +#define PROC_FCH_KERN_KERNUSB_KERNEHCILATE_FILECODE (0xB4A7) +#define PROC_FCH_KERN_KERNUSB_KERNEHCIMIDSERVICE_FILECODE (0xB4A8) +#define PROC_FCH_KERN_KERNUSB_KERNEHCIENVSERVICE_FILECODE (0xB4A9) +#define PROC_FCH_KERN_KERNUSB_KERNEHCILATESERVICE_FILECODE (0xB4AA) +#define PROC_FCH_KERN_KERNUSB_KERNXHCIRESET_FILECODE (0xB4B2) +#define PROC_FCH_KERN_KERNUSB_KERNXHCIENV_FILECODE (0xB4B3) +#define PROC_FCH_KERN_KERNUSB_KERNXHCIMID_FILECODE (0xB4B4) +#define PROC_FCH_KERN_KERNUSB_KERNXHCILATE_FILECODE (0xB4B5) +#define PROC_FCH_KERN_KERNUSB_KERNXHCIRESETSERVICE_FILECODE (0xB4B6) +#define PROC_FCH_KERN_KERNUSB_KERNXHCIENVSERVICE_FILECODE (0xB4B7) +#define PROC_FCH_KERN_KERNUSB_KERNXHCIMIDSERVICE_FILECODE (0xB4B8) +#define PROC_FCH_KERN_KERNUSB_KERNXHCILATESERVICE_FILECODE (0xB4B9) +#define PROC_FCH_KERN_KERNUSB_KERNXHCIRECOVERY_FILECODE (0xB4BA) +#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICS_FILECODE (0xB408) +#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICSAML_FILECODE (0xB409) +#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICSCONTROL_FILECODE (0xB40A) +#define UEFI_FCH_KERN_DXE_FCHACPICS_FUNCTIONS_FCHD3COLD_FCHD3COLD_FILECODE (0xB40B) +#define UEFI_FCH_KERN_DXE_AMDFCHHWM_AMDFCHHWM_FILECODE (0xB4C1) +#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEA_FILECODE (0xB4C2) +#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEAEINJ_FILECODE (0xB4C3) +#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEAHEST_FILECODE (0xB4C4) +#define UEFI_FCH_KERN_DXE_CF9RESET_CF9RESET_FILECODE (0xB4C5) +#define UEFI_FCH_KERN_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB4C6) +#define UEFI_FCH_KERN_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB4C7) +#define UEFI_FCH_KERN_DXE_FCHDXE_FCHDXE_FILECODE (0xB4C8) +#define UEFI_FCH_KERN_DXE_FCHDXE_USBOC_FILECODE (0xB4C9) +#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEBOOTTIMER_FILECODE (0xB4CA) +#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEDISUSBPORT_FILECODE (0xB4CB) +#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEESATAPORT_FILECODE (0xB4CC) +#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEGPIO_FILECODE (0xB4CD) +#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEGPIOREAD_FILECODE (0xB4CE) +#define UEFI_FCH_KERN_DXE_FCHDXEAUX_FCHDXEAUX_FILECODE (0xB4CF) +#define UEFI_FCH_KERN_DXE_FCHDXELIB_FCHDXELIB_FILECODE (0xB4D0) +#define UEFI_FCH_KERN_DXE_FCHDXELPCCLKRUN_FCHDXELPCCLKRUN_FILECODE (0xB4D1) +#define UEFI_FCH_KERN_DXE_FCHDXEMMIO_FCHDXEMMIO_FILECODE (0xB4D2) +#define UEFI_FCH_KERN_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB4D3) +#define UEFI_FCH_KERN_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB4D4) +#define UEFI_FCH_KERN_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB4D5) +#define UEFI_FCH_KERN_PEI_FCHPEI_FCHEHCIRECOVERY_FILECODE (0xB4D6) +#define UEFI_FCH_KERN_PEI_FCHPEI_FCHPEI_FILECODE (0xB4D8) +#define UEFI_FCH_KERN_PEI_FCHPEI_FCHRESET_FILECODE (0xB4D9) +#define UEFI_FCH_KERN_PEI_FCHPEI_FCHSATARECOVERY_FILECODE (0xB4DA) +#define UEFI_FCH_KERN_PEI_FCHPEI_FCHSTALL_FILECODE (0xB4DB) +#define UEFI_FCH_KERN_PEI_FCHPEI_FCHXHCIRECOVERY_FILECODE (0xB4DC) +#define UEFI_FCH_KERN_PEI_FCHPEIAUX_FCHPEIAUX_FILECODE (0xB4DD) +#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIBOOTTIMER_FILECODE (0xB4DE) +#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIDISUSBPORT_FILECODE (0xB4DF) +#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIGPIO_FILECODE (0xB4E0) +#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIGPIOREAD_FILECODE (0xB4E1) +#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIOSCOUTCLOCK_FILECODE (0xB4E2) +#define UEFI_FCH_KERN_PEI_FCHPEILIB_FCHPEILIB_FILECODE (0xB4E3) +#define UEFI_FCH_KERN_PEI_FCHPEILIB_LIBAMDPEI_FILECODE (0xB4E4) +#define UEFI_FCH_KERN_PEI_SMBUS_SMBUS_FILECODE (0xB4E5) +#define UEFI_FCH_KERN_SMM_FCHSMM_FCHSMM_FILECODE (0xB4E6) +#define UEFI_FCH_KERN_SMM_FCHSMM_GPESMI_FILECODE (0xB4E7) +#define UEFI_FCH_KERN_SMM_FCHSMM_IOTRAPSMI_FILECODE (0xB4E8) +#define UEFI_FCH_KERN_SMM_FCHSMM_MISCSMI_FILECODE (0xB4E9) +#define UEFI_FCH_KERN_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE (0xB4EA) +#define UEFI_FCH_KERN_SMM_FCHSMM_POWERBUTTONSMI_FILECODE (0xB4EB) +#define UEFI_FCH_KERN_SMM_FCHSMM_SWSMI_FILECODE (0xB4EC) +#define UEFI_FCH_KERN_SMM_FCHSMM_SXSMI_FILECODE (0xB4ED) +#define UEFI_FCH_KERN_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROL_FILECODE (0xB4F0) +#define UEFI_FCH_KERN_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROLLIB_FILECODE (0xB4F1) +#define UEFI_FCH_KERN_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB4F5) +#define UEFI_FCH_KERN_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB4F6) +#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE (0xB4F7) +#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE (0xB4F8) +#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE (0xB4F9) +#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE (0xB4FA) +#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB4FB) +#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE (0xB4FC) +#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE (0xB4FE) +#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE (0xB4FF) +#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE (0xB4F2) + + +#define LIB_AMDLIB_FILECODE (0xC001) +#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010) +#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011) +#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012) + +#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120) + +#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140) +#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141) +#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142) +#define UEFI_PROC_COMMON_HOBTRANSFERUEFI_FILECODE (0xC160) +#define UEFI_PROC_DXE_HOBTRANSFERUEFIDXE_FILECODE (0xC161) +#define UEFI_PROC_PEI_HOBTRANSFERUEFIPEI_FILECODE (0xC162) + +#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020) +#define PROC_COMMON_AMDINITENV_FILECODE (0xC021) +#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022) +#define PROC_COMMON_AMDINITMID_FILECODE (0xC023) +#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024) +#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025) +#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026) +#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027) +#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028) +#define PROC_COMMON_AMDINITRTB_FILECODE (0xC029) +#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A) +#define PROC_COMMON_AMDS3FINALRESTORE_FILECODE (0xC02B) + +#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0) +#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0) +#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0) +#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8) +#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9) +#define PROC_COMMON_S3INIT_FILECODE (0xC0FA) + +#define PROC_CPU_CPUAPCOMM_FILECODE (0xC401) +#define PROC_CPU_CPUAPCOMMAPIC_FILECODE (0xC402) +#define PROC_CPU_CPUAPCOMMPCI_FILECODE (0xC403) +#define PROC_CPU_TABLE_FILECODE (0xC404) +#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405) +#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406) +#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407) +#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408) +#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A) +#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B) +#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C) +#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D) +#define PROC_CPU_CPUBIST_FILECODE (0xC40E) +#define PROC_CPU_MMIOMAPMANAGER_FILECODE (0xC40F) +#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC410) +#define PROC_CPU_CPURESETINIT_FILECODE (0xC411) +#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420) +#define PROC_CPU_CPUMIDINIT_FILECODE (0xC421) +#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430) +#define PROC_CPU_S3_FILECODE (0xC460) + +// Family 15h +#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01) +#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02) +#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03) +#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB04) +#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB08) +#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB09) +#define PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE (0xCB0A) +#define PROC_CPU_FAMILY_0X15_CPUF15CRAT_FILECODE (0xCB0B) +#define PROC_CPU_FAMILY_0X15_CPUF15MMIOMAP_FILECODE (0xCB0C) +#define PROC_CPU_FAMILY_0X15_CPUF15PREFETCHMODE_FILECODE (0xCB0D) + +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCOREAFTERRESET_FILECODE (0xCB70) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZDMI_FILECODE (0xCB71) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZNBAFTERRESET_FILECODE (0xCB72) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPSTATE_FILECODE (0xCB73) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZLOGICALIDTABLES_FILECODE (0xCB74) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZMICROCODEPATCHTABLES_FILECODE (0xCB75) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZALLCORETABLES_FILECODE (0xCB76) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCOMPUTEUNITTABLES_FILECODE (0xCB77) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZEQUIVALENCETABLE_FILECODE (0xCB78) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPRIMARYCORETABLES_FILECODE (0xCB79) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPOWERMGMTSYSTEMTABLES_FILECODE (0xCB7A) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZUTILITIES_FILECODE (0xCB7C) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZC6STATE_FILECODE (0xCB7D) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCPB_FILECODE (0xCB7E) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZIOCSTATE_FILECODE (0xCB7F) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCACHEFLUSHONHALT_FILECODE (0xCB80) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZHTC_FILECODE (0xCB81) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZINITEARLYTABLE_FILECODE (0xCB82) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZEARLYSAMPLES_FILECODE (0xCB83) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPSI_FILECODE (0xCB85) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZWORKAROUNDTABLE_FILECODE (0xCB87) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCC6EXITCONTROL_FILECODE (0xCB88) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCONNECTEDSTANDBY_FILECODE (0xCB89) +#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZBTC_FILECODE (0xCB8A) + +#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01) +#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02) +#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10) +#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43) +#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70) +#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82) +#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83) +#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85) +#define PROC_CPU_FEATURE_CPUAPM_FILECODE (0xDC86) +#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90) +#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0) +#define PROC_CPU_FEATURE_CPUPSI_FILECODE (0xDCC0) +#define PROC_CPU_FEATURE_CPUHTC_FILECODE (0xDCC1) +#define PROC_CPU_FEATURE_CPUCRAT_FILECODE (0xDCD0) +#define PROC_CPU_FEATURE_CPUCDIT_FILECODE (0xDCD1) +#define PROC_CPU_FEATURE_CPUPREFETCHMODE_FILECODE (0xDCD3) +#define PROC_CPU_FEATURE_CPUCONNECTEDSTANDBY_FILECODE (0xDCD5) +#define PROC_CPU_FEATURE_CPUCC6EXITCONTROL_FILECODE (0xDCD6) + +#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01) + +#define PROC_TOPOLOGY_TOPOMAIN_FILECODE (0xE001) +#define PROC_TOPOLOGY_TOPONB_FILECODE (0xE002) +#define PROC_TOPOLOGY_FAM15_TOPONBFAM15_FILECODE (0xE087) +#define PROC_TOPOLOGY_FAM15_TOPONBUTILITIESFAM15_FILECODE (0xE088) + +#define PROC_RECOVERY_TOPOLOGY_TOPOINITRECOVERY_FILECODE (0xE0FF) + +#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801) +#define PROC_IDS_LIBRARY_IDSLIB_FILECODE (0xE802) +#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803) +#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804) +#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C) + +#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE (0xE810) +#define PROC_IDS_DEBUG_IDSDPHDTOUT_FILECODE (0xE811) +#define PROC_IDS_DEBUG_IDSDEBUGPRINT_FILECODE (0xE812) +#define PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE (0xE813) +#define PROC_IDS_DEBUG_IDSDPREDIRECTIO_FILECODE (0xE814) +#define PROC_IDS_DEBUG_IDSDPRAM_FILECODE (0xE815) + +#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E) +#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F) +#define PROC_IDS_FAMILY_0X15_CZ_IDSF15CZALLSERVICE_FILECODE (0xE821) + + +///0xE820 ~ 0xE840 is reserved for ids extend module + +#define PROC_MEM_ARDK_MA_FILECODE (0xF001) + +#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081) +#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082) +#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083) +#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085) +#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086) +#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088) +#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089) +#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A) +#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B) +#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C) +#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D) +#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E) +#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091) +#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092) +#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093) +#define PROC_MEM_FEAT_CHINTLV_MFMCHI_FILECODE (0xF094) +#define PROC_MEM_FEAT_CRAT_MFCRAT_FILECODE (0xF095) +#define PROC_MEM_FEAT_AMP_MFAMP_FILECODE (0xF096) +#define PROC_MEM_FEAT_DATAEYE_MF2DDATAEYE_FILECODE (0xF097) +#define PROC_MEM_FEAT_RDWR2DTRAINING_MFWRDAT2DTRAINING_FILECODE (0xF098) +#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DEYERIMSEARCH_FILECODE (0xF099) +#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDDQS2DTRAINING_FILECODE (0xF09A) +#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DTRAINING_FILECODE (0xF09B) +#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DPATTERNGENERATION_FILECODE (0xF09C) +#define PROC_MEM_FEAT_AGGRESSOR_MFAGGRESSOR_FILECODE (0xF09F) +#define PROC_MEM_FEAT_DLLPDBYPASS_MFDLLPDBYPASS_FILECODE (0xF0A0) + +#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101) +#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102) +#define PROC_MEM_MAIN_MM_FILECODE (0xF103) +#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104) +#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105) +#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106) +#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B) +#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C) +#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D) +#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E) +#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F) +#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110) +#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112) +#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113) +#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115) +#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116) +#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117) +#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118) +#define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119) +#define PROC_MEM_MAIN_CZ_MMFLOWD3CZ_FILECODE (0xF127) + +#define PROC_MEM_NB_MN_FILECODE (0XF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0XF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) +#define PROC_MEM_NB_MNREG_FILECODE (0XF285) +#define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) +#define PROC_MEM_NB_CZ_MNCZ_FILECODE (0xF2D8) +#define PROC_MEM_NB_CZ_MNDCTCZ_FILECODE (0xF2D9) +#define PROC_MEM_NB_CZ_MNIDENDIMMCZ_FILECODE (0xF2DA) +#define PROC_MEM_NB_CZ_MNMCTCZ_FILECODE (0xF2DB) +#define PROC_MEM_NB_CZ_MNPHYCZ_FILECODE (0xF2DC) +#define PROC_MEM_NB_CZ_MNPMUCZ_FILECODE (0xF2DD) +#define PROC_MEM_NB_CZ_MNPMUSRAMMSGBLOCKCZ_FILECODE (0xF2DE) +#define PROC_MEM_NB_CZ_MNPROTOCZ_FILECODE (0xF2DF) +#define PROC_MEM_NB_CZ_MNREGCZ_FILECODE (0xF2E0) +#define PROC_MEM_NB_CZ_MNS3CZ_FILECODE (0xF2E1) +#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0XF2E3) + + +#define PROC_MEM_PS_MP_FILECODE (0XF401) +#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) +#define PROC_MEM_PS_MPS2D_FILECODE (0XF436) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) +#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) +#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) +#define PROC_MEM_PS_CZ_MPCZ3_FILECODE (0XF445) +#define PROC_MEM_PS_CZ_MPSCZ3_FILECODE (0XF446) +#define PROC_MEM_PS_CZ_MPUCZ3_FILECODE (0XF447) +#define PROC_MEM_PS_CZ_FP4_MPSCZFP4_FILECODE (0XF44A) +#define PROC_MEM_PS_CZ_FP4_MPUCZFP4_FILECODE (0XF44B) + + +#define PROC_MEM_TECH_MT_FILECODE (0XF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) +#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) +#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) + +#define PROC_MEM_X86_MEMINITLIBX86_FILECODE (0xF590) +#define PROC_MEM_A57_MEMINITLIBA57_FILECODE (0xF591) + +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) +#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA) + +//Psp +#define PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE (0xFA20) + +#endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h b/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h new file mode 100644 index 0000000000..aea946a784 --- /dev/null +++ b/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h @@ -0,0 +1,222 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * General Services + * + * Provides Services similar to the external General Services API, except + * suited to use within AGESA components. Socket, Core and PCI identification. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _GENERAL_SERVICES_H_ +#define _GENERAL_SERVICES_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define NUMBER_OF_EVENT_DATA_PARAMS 4 + +/** + * AMD Device id for MMIO check. + */ +#define AMD_DEV_VEN_ID 0x1022 +#define AMD_DEV_VEN_ID_ADDRESS 0 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +/** + * An AGESA Event Log entry. + */ +typedef struct { + AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS. + UINT32 EventInfo; ///< Uniquely identifies the event. + UINT32 DataParam1; ///< Event specific additional data + UINT32 DataParam2; ///< Event specific additional data + UINT32 DataParam3; ///< Event specific additional data + UINT32 DataParam4; ///< Event specific additional data +} AGESA_EVENT; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +/** + * Get a specified Core's APIC ID. + * + * @param[in] StdHeader Header for library and services. + * @param[in] Socket The Core's Socket. + * @param[in] Core The Core id. + * @param[out] ApicAddress The Core's APIC ID. + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + * @retval TRUE The core is present, APIC Id valid + * @retval FALSE The core is not present, APIC Id not valid. + */ +BOOLEAN +GetApicId ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 Socket, + IN UINT32 Core, + OUT UINT8 *ApicAddress, + OUT AGESA_STATUS *AgesaStatus +); + +/** + * Get Processor Module's PCI Config Space address. + * + * @param[in] StdHeader Header for library and services. + * @param[in] Socket The Core's Socket. + * @param[in] Module The Module in that Processor + * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + * @retval TRUE The core is present, PCI Address valid + * @retval FALSE The core is not present, PCI Address not valid. + */ +BOOLEAN +GetPciAddress ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 Socket, + IN UINT32 Module, + OUT PCI_ADDR *PciAddress, + OUT AGESA_STATUS *AgesaStatus +); + +/** + * "Who am I" for the current running core. + * + * @param[in] StdHeader Header for library and services. + * @param[out] Socket The current Core's Socket + * @param[out] Module The current Core's Processor Module + * @param[out] Core The current Core's core id. + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + */ +VOID +IdentifyCore ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT UINT32 *Socket, + OUT UINT32 *Module, + OUT UINT32 *Core, + OUT AGESA_STATUS *AgesaStatus +); + +/*---------------------------------------------------------------------------------------*/ +/** + * Is this the BSP core? + * + * @param[in,out] StdHeader Header for library and services + * + * @retval TRUE Is BSP core + * @retval FALSE Is not BSP Core + * + */ +BOOLEAN +IsBsp ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function logs AGESA events into the event log. + */ +VOID +PutEventLog ( + IN AGESA_STATUS EventClass, + IN UINT32 EventInfo, + IN UINT32 DataParam1, + IN UINT32 DataParam2, + IN UINT32 DataParam3, + IN UINT32 DataParam4, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function gets event logs from the circular buffer. + */ +AGESA_STATUS +GetEventLog ( + OUT AGESA_EVENT *EventRecord, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function gets event logs from the circular buffer without flushing the entry. + */ +BOOLEAN +PeekEventLog ( + OUT AGESA_EVENT *EventRecord, + IN UINT16 Index, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * This routine programs the registers necessary to get the PCI MMIO mechanism + * up and functioning. + */ +VOID +InitializePciMmio ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Is it SecureS3 + * + * @param[in] StdHeader Header for library and services + * + * @retval TRUE It's SecureS3 + * @retval FALSE It's NOT SecureS3 + * + */ +BOOLEAN +IsSecureS3 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _GENERAL_SERVICES_H_ diff --git a/src/vendorcode/amd/pi/00670F00/Include/Ids.h b/src/vendorcode/amd/pi/00670F00/Include/Ids.h new file mode 100644 index 0000000000..cb101869e3 --- /dev/null +++ b/src/vendorcode/amd/pi/00670F00/Include/Ids.h @@ -0,0 +1,1484 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD IDS Routines + * + * Contains AMD AGESA Integrated Debug Macros + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $ + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + + /* Macros to aid debugging */ + /* These definitions expand to zero (0) bytes of code when disabled */ + +#ifndef _IDS_H_ +#define _IDS_H_ + +#undef FALSE +#undef TRUE +#define FALSE 0 +#define TRUE 1 +// Proto type for optionsids.h +typedef UINT32 IDS_STATUS; ///< Status of IDS function. +#define IDS_SUCCESS ((IDS_STATUS) 0x00000000ul) ///< IDS Function is Successful. +#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFFul) ///< IDS Function is not existed. + +#define IDS_STRINGIZE(a) #a ///< for define stringize macro +#ifndef IDS_DEADLOOP + #define IDS_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); } +#endif +/** + * IDS Option Hook Points + * + * These are the values to indicate hook point in AGESA for IDS Options. + * + */ +typedef enum { //vv- for debug reference only + IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY. + ///< IDS Object is initialized. + ///< Override CPU Core Leveling Mode. + ///< Set P-State in Post + IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY. + IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE. + ///< It will be used to control the following tables. + ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC) + ///< ACPI WHEA Table + ///< DMI Table + IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE. + IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID. + IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID. + IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST. + ///< Control Interleaving and DRAM memory hole + ///< Override the setting of ECC Control + ///< Override the setting of Online Spare Rank + IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST. + IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET. + IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET. + IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST. + IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save. + IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore + IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save + IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore + IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training + IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization + IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change + IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset + IDS_BEFORE_PCI_INIT, ///< 13 Override PCI or MSR Registers Before PCI Init + IDS_BEFORE_AP_EARLY_HALT, ///< 14 Option Hook Point before AP early halt + IDS_BEFORE_S3_RESUME, ///< 15 Option Hook Point before s3 resume + IDS_AFTER_S3_RESUME, ///< 16 Option Hook Point after s3 resume + IDS_BEFORE_PM_INIT, ///< 17 Option Hook Point Before Pm Init + + IDS_INIT_RTB_BEFORE, ///< 18 Option Hook Point before AGESA function AMD_INIT_RTB. + IDS_INIT_RTB_AFTER, ///< 19 Option Hook Point after AGESA function AMD_INIT_RTB. + + IDS_MT_BASE = 0x20, ///< 0x20 ~ 0x38 24 time points reserved for MTTime + + IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used + + // All the above timing point is used by BVM, their value should never be changed + IDS_INIT_DRAM_TABLE, ///< 40 Generate override table for Dram Timing + ///< Dram Controller, Drive Strength and DQS Timing + IDS_GET_DRAM_TABLE, ///< 41 Generate override table for Dram Timing + IDS_GANGING_MODE, ///< 42 override Memory Mode Unganged + IDS_POWERDOWN_MODE, ///< 43 override Power Down Mode + IDS_BURST_LENGTH32, ///< 44 override Burst Length32 + IDS_ALL_MEMORY_CLOCK, ///< 45 override All Memory Clks Enable + IDS_ECC, ///< 46 override ECC parameter + IDS_ECCSYMBOLSIZE, ///< 47 override ECC symbol size + IDS_CPU_Early_Override, ///< 48 override CPU early parameter + IDS_CACHE_FLUSH_HLT, ///< 49 override Cache Flush Hlt + IDS_CHANNEL_INTERLEAVE, ///< 4a override Channel Interleave + IDS_MEM_ERROR_RECOVERY, ///< 4b override memory error recovery + IDS_MEM_RETRAIN_TIMES, ///< 4c override memory retrain times + IDS_MEM_SIZE_OVERLAY, ///< 4d Override the syslimit + IDS_CHECK_NEGATIVE_WL, ///< 4e Check for negative write leveling result + IDS_DLL_SHUT_DOWN, ///< 4f Check for Dll Shut Down + IDS_POR_MEM_FREQ, ///< 50 Entry to enable/disable MemClk frequency enforcement + IDS_PHY_DLL_STANDBY_CTRL, ///< 51 Enable/Disable Phy DLL standby feature + IDS_PLATFORMCFG_OVERRIDE, ///< 52 Hook for Override PlatformConfig structure + IDS_LOADCARD_ERROR_RECOVERY, ///< 53 Special error handling for load card support + IDS_MEM_IGNORE_ERROR, ///< 54 Ignore error and do not do fatal exit in memory + IDS_GNB_SMU_SERVICE_CONFIG, ///< 55 Config GNB SMU service + IDS_GNB_ORBDYNAMIC_WAKE, ///< 56 config GNB dynamic wake + IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 57 override ids gnb platform config + IDS_GNB_LCLK_DPM_EN, ///< 58 override GNB LCLK DPM configuration + IDS_GNB_LCLK_DEEP_SLEEP, ///< 59 override GNB LCLK DPM deep sleep + IDS_GNB_CLOCK_GATING, ///< 5a Override GNB Clock gating config + IDS_NB_PSTATE_DIDVID, ///< 5b Override NB P-state settings + IDS_CPB_CTRL, ///< 5c Config the Core peformance boost feature + IDS_HTC_CTRL, ///< 5d Hook for Hardware Thermal Control + IDS_CC6_WORKAROUND, ///< 5e Hook for skip CC6 work around + IDS_MEM_MR0, ///< 5f Hook for override Memory Mr0 register + IDS_TRAP_TABLE, ///< 60 Hook for add IDS register table to the loop + IDS_NBBUFFERALLOCATIONATEARLY, ///< 61 Hook for override North bridge bufer allocation + IDS_BEFORE_S3_SPECIAL, ///< 62 Hook to bypass S3 special functions + IDS_SET_PCI_REGISTER_ENTRY, ///< 63 Hook to SetRegisterForPciEntry + IDS_ERRATUM463_WORKAROUND, ///< 64 Hook to Erratum 463 workaround + IDS_BEFORE_MEMCLR, ///< 65 Hook before set Memclr bit + IDS_OVERRIDE_IO_CSTATE, ///< 66 Hook for override io C-state setting + IDS_NBPSDIS_OVERRIDE, ///< 67 Hook for override NB pstate disable setting + IDS_NBPS_REG_OVERRIDE, ///< 68 Hook for override Memory NBps reg + IDS_MEM_PHY_POWER_SAVING, ///< 69 Hook to bypass DRAM Phy power savings + IDS_CST_CREATE, ///< 6a Hook for create _CST + IDS_CST_SIZE, ///< 6b Hook for get _CST size + IDS_ENFORCE_VDDIO, ///< 6c Hook to override VDDIO + IDS_STRETCH_FREQUENCY_LIMIT, ///< 6d Hook for enforcing memory stretch frequency limit + IDS_INIT_MEM_REG_TABLE, ///< 6e Hook for init memory register table + IDS_SKIP_FUSED_MAX_RATE, ///< 6f Hook to skip fused max rate cap + IDS_FCH_INIT_AT_RESET, ///< 70 Hook for FCH reset parameter + IDS_FCH_INIT_AT_ENV, ///< 71 Hook for FCH ENV parameter + IDS_ENFORCE_PLAT_TABLES, ///< 72 Hook to enforce platform specific tables + IDS_NBPS_MIN_FREQ, ///< 73 Hook for override MIN nb ps freq + IDS_GNB_FORCE_CABLESAFE, ///< 74 Hook for override Force Cable Safe + IDS_SKIP_PM_TRANSITION_STEP, ///< 75 Hook for provide IDS ability to skip this PM step + IDS_GNB_PROPERTY, ///< 76 Hook for GNB Property + IDS_GNB_PCIE_POWER_GATING, ///< 77 Hook for GNB PCIe Power Gating + IDS_MEM_DYN_DRAM_TERM, ///< 78 Hook for Override Dynamic Dram Term + IDS_MEM_DRAM_TERM, ///< 79 Hook for Override Dram Term + IDS_GNB_ALTVDDNB, ///< 7a Hook for Override AltVddNB + IDS_UCODE, ///< 7b Enable or Disable microcode patching + IDS_FAM_REG_GMMX, ///< 7c GMMX register access + IDS_MEMORY_POWER_POLICY, ///< 7d Memory power policy + IDS_GET_STRETCH_FREQUENCY_LIMIT, ///< 7e Hook for enforcing memory stretch frequency limit + IDS_CPU_FEAT, ///< 7f Hook for runtime force cpu feature disable + IDS_AFTER_DCT_PHY_ACCESS, ///< 80 Hook for DctAccessDone check + IDS_FORCE_PHY_TO_M0, ///< 81 Hook to bypass M0 enforcement + IDS_GNB_PMM_SWTJOFFSET, ///< 82 Hook to GNBSWTJOFFSET + IDS_LOCK_DRAM_CFG, ///< 83 Hook to BFLockDramCfg + IDS_BEFORE_GEN2_INIT, ///< 84 Hook to Before Gen2 Init + IDS_BEFORE_GPP_TRAINING, ///< 85 Hook to Before Gpp training + IDS_BEFORE_RECONFIGURATION, ///< 86 Hook to Before Reconfiguration + IDS_BEFORE_GEN3_INIT, ///< 87 Hook to Before Gen3 Init + IDS_BEFORE_POWER_GATING, ///< 88 Hook to Before Power Gating + IDS_AFTER_EARLY_INIT_ONCORE, ///< 89 Hook to after EarlyInit On Core + IDS_GNB_PCIE_PORT_REMAP, ///< 8a Hook to change mapping of PCIe devices + IDS_ECC_CONTROL, ///< 8b Enable/Disable ECC feature + IDS_GNB_PCIE_PHY_ISOLATION, ///< 8c Enable/Disable PCIE PHY ISOLATION + IDS_AFTER_RESTORING_PCI_REG, ///< 8d Hook after restoring PCI register during S3 resume + IDS_MSR_ACCESS_OVERRIDE, ///< 8e Hook to disable MSR access + IDS_REPORT_SMU_FW_VERSION, ///< 8f Hook to report SMU firmware version + IDS_GNB_LOAD_SAMU_PATCH, ///< 90 Hook to Load SAMU patch + IDS_DLLSTAGGERDLY_OVERRIDE, ///< 91 Hook to skip Dll Stagger Delay + IDS_CSAMPLE_TIMER, ///< 92 Hook to override CSampleTimer + IDS_PIPE_THROTTLE, ///< 93 Hook to override PipeThrottle + IDS_GNB_PMM_NATIVEGEN1PLL, ///< 94 Enable/Disable Native Gen1 PLL + IDS_BEFORE_PLAT_TABLES, ///< 95 Hook before processing platform specific tables + IDS_GNB_PCIE_MASTERPLL_SELECTION, ///< 96 Hook to override PCIe Master PLL selection + IDS_GNB_PCIE_PHYLANE_CONFIG, ///< 97 Hook to override PCIe PhyLane configuration + IDS_DSM_LP_SELECTION, ///< 98 Set Dsm low power mode + IDS_GNB_EQUAL_PRESET, ///< 99 Set equalization preset + IDS_GNB_GEN1_LOOPBACK, ///< 9a Override Gen 1 loopback mode + IDS_GNB_SMU_SERVICE_MASK, ///< 9b Override SMU service enablement mask + IDS_BEFORE_HT_MEM_MAP, ///< 9c Hook before mapping memory address space among DCTs + IDS_GNB_GEN3_SETTINGS_OVERRIDE, ///< 9d Hook to override Gen3 Adapt PI Offset Bypass Enable + IDS_GNB_TARGET_TDP, ///< 9e Hook to override Target TDP + IDS_GNB_SMU_PORT80_PARAMS, ///< 9f Hook to override gnb smu port80 values + IDS_CPU_OVERRIDE_REG_AFTER_AP_LAUNCH, ///< a0 Hook to override registers after AP lauch + IDS_AFTER_FEAT_MID_INIT, ///< a1 Hook to override feature setting after cpuMidInit + IDS_MEM_MCLK_ABOVE_NCLK, ///< a2 Hook to bypass system bandwidth for memory clock + IDS_ALL_MEMORY_CKE, ///< a3 override All Memory CKE + IDS_ALL_MEMORY_CS, ///< a4 override All Memory CS + IDS_NPST, ///< a5 cTDP NbPstate Selection Table + IDS_MEM_MRL_RETRAIN_TIMES, ///< a6 override memory MRL retrain times + IDS_AFTER_DQS_TRAINING, ///< a7 override any settings after DQS training + IDS_OVERRIDE_DIMM_MASK, ///< a8 override DimmMask for S3 data blob creation + IDS_BYPASS_S3_REGISTERS, ///< a9 bypass restoring certain registers + IDS_OPTION_END ///< AA End of IDS option +} AGESA_IDS_OPTION; + +#include "OptionsIds.h" +#include "Filecode.h" +#include "IdsPerf.h" + +/* Initialize IDS controls */ +#ifndef IDSOPT_IDS_ENABLED + #define IDSOPT_IDS_ENABLED FALSE +#endif + +#ifndef IDSOPT_CONTROL_ENABLED + #define IDSOPT_CONTROL_ENABLED FALSE +#endif + +#ifndef IDSOPT_CONTROL_NV_TO_CMOS + #define IDSOPT_CONTROL_NV_TO_CMOS FALSE +#endif + +#ifndef IDSOPT_TRACING_ENABLED + #define IDSOPT_TRACING_ENABLED FALSE +#endif + +#ifndef IDSOPT_TRACE_USER_OPTIONS + #define IDSOPT_TRACE_USER_OPTIONS TRUE +#endif + +#ifndef IDSOPT_PERF_ANALYSIS + #define IDSOPT_PERF_ANALYSIS FALSE +#endif + +#ifndef IDSOPT_HEAP_CHECKING + #define IDSOPT_HEAP_CHECKING FALSE +#endif + +#ifndef IDSOPT_ASSERT_ENABLED + #define IDSOPT_ASSERT_ENABLED FALSE +#endif + +#ifndef IDSOPT_ERROR_TRAP_ENABLED + #define IDSOPT_ERROR_TRAP_ENABLED FALSE +#endif + +#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE +#endif + +#ifndef IDSOPT_DEBUG_CODE_ENABLED + #define IDSOPT_DEBUG_CODE_ENABLED FALSE +#endif + +#ifndef IDSOPT_IDT_EXCEPTION_TRAP + #define IDSOPT_IDT_EXCEPTION_TRAP FALSE +#endif + +#ifndef IDSOPT_C_OPTIMIZATION_DISABLED + #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE +#endif + +#ifndef IDSOPT_TRACING_CONSOLE_HDTOUT + #define IDSOPT_TRACING_CONSOLE_HDTOUT TRUE +#endif + +#ifndef IDSOPT_TRACING_CONSOLE_SERIALPORT + #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE +#endif + +#ifndef IDSOPT_TRACING_CONSOLE_REDIRECT_IO + #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE +#endif + +#ifndef IDSOPT_TRACING_CONSOLE_RAM + #define IDSOPT_TRACING_CONSOLE_RAM FALSE +#endif + +#if IDSOPT_IDS_ENABLED == FALSE + #undef IDSOPT_CONTROL_ENABLED + #undef IDSOPT_TRACING_ENABLED + #undef IDSOPT_PERF_ANALYSIS + #undef IDSOPT_HEAP_CHECKING + #undef IDSOPT_ASSERT_ENABLED + #undef IDSOPT_ERROR_TRAP_ENABLED + #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + #undef IDSOPT_DEBUG_CODE_ENABLED + #undef IDSOPT_TRACE_USER_OPTIONS + #undef IDSOPT_TRACING_CONSOLE_HDTOUT + #undef IDSOPT_TRACING_CONSOLE_SERIALPORT + #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO + #undef IDSOPT_TRACING_CONSOLE_RAM + + #define IDSOPT_CONTROL_ENABLED FALSE + #define IDSOPT_TRACING_ENABLED FALSE + #define IDSOPT_PERF_ANALYSIS FALSE + #define IDSOPT_HEAP_CHECKING FALSE + #define IDSOPT_ASSERT_ENABLED FALSE + #define IDSOPT_ERROR_TRAP_ENABLED FALSE + #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE + #define IDSOPT_DEBUG_CODE_ENABLED FALSE + #define IDSOPT_TRACE_USER_OPTIONS FALSE + #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE + #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE + #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE + #define IDSOPT_TRACING_CONSOLE_RAM FALSE +#endif + +//Disable when master token Tracing is set to FALSE +#if (IDSOPT_TRACING_ENABLED == FALSE) || (defined (IDSOPT_CUSTOMIZE_TRACING_SERVICE)) + #undef IDSOPT_TRACING_CONSOLE_HDTOUT + #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE + + #undef IDSOPT_TRACING_CONSOLE_SERIALPORT + #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE + + #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO + #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE + + #undef IDSOPT_TRACING_CONSOLE_RAM + #define IDSOPT_TRACING_CONSOLE_RAM FALSE +#endif + +//Disable Tracing if all support HW layer set to FALSE +#if ((IDSOPT_TRACING_CONSOLE_HDTOUT == FALSE) && (IDSOPT_TRACING_CONSOLE_SERIALPORT == FALSE) && (IDSOPT_TRACING_CONSOLE_REDIRECT_IO == FALSE) && (IDSOPT_TRACING_CONSOLE_RAM == FALSE)) + #ifndef IDSOPT_CUSTOMIZE_TRACING_SERVICE + #undef IDSOPT_TRACING_ENABLED + #define IDSOPT_TRACING_ENABLED FALSE + #endif +#endif +/** + * Make a Progress Report to the User. + * + * This Macro is always enabled. The default action is to write the TestPoint value + * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80. + * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port + * in OptionsIds.h in their build tip. + * + * @param[in] TestPoint The value for display indicating progress + * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS + * + **/ + +#define AGESA_TESTPOINT(TestPoint, StdHeader) IdsAgesaTestPoint ((TestPoint), (StdHeader)) + +#ifndef IDS_DEBUG_PORT + #define IDS_DEBUG_PORT 0x80 +#endif + +#if IDS_DEBUG_PORT > 0xFFFFul + #error "Invalid debug port defined. IDS_DEBUG_PORT address must not be larger than 16 bits." +#endif + +#ifndef IDS_DEBUG_PORT_SIZE_IN_BYTES + #define IDS_DEBUG_PORT_SIZE_IN_BYTES 4 +#endif + +#if IDS_DEBUG_PORT_SIZE_IN_BYTES == 1 + #define IDS_DEBUG_PORT_ACCESSWIDTH AccessWidth8 + #ifndef IDS_DEBUG_TP_PREFIX + #define IDS_DEBUG_TP_PREFIX 0x00ul + #endif + #if IDS_DEBUG_TP_PREFIX != 0 + #error "Invalid debug port prefix defined. IDS_DEBUG_TP_PREFIX << 8 must not exceed IDS_DEBUG_PORT_SIZE_IN_BYTES." + #endif +#else + #if IDS_DEBUG_PORT_SIZE_IN_BYTES == 2 + #define IDS_DEBUG_PORT_ACCESSWIDTH AccessWidth16 + #ifndef IDS_DEBUG_TP_PREFIX + #define IDS_DEBUG_TP_PREFIX 0xA0ul + #endif + #if IDS_DEBUG_TP_PREFIX > 0xFFul + #error "Invalid debug port prefix defined. IDS_DEBUG_TP_PREFIX << 8 must not exceed IDS_DEBUG_PORT_SIZE_IN_BYTES." + #endif + #else + #if IDS_DEBUG_PORT_SIZE_IN_BYTES == 4 + #define IDS_DEBUG_PORT_ACCESSWIDTH AccessWidth32 + #ifndef IDS_DEBUG_TP_PREFIX + #define IDS_DEBUG_TP_PREFIX 0xA9E5A0ul + #endif + #if IDS_DEBUG_TP_PREFIX > 0xFFFFFFul + #error "Invalid debug port prefix defined. IDS_DEBUG_TP_PREFIX << 8 must not exceed IDS_DEBUG_PORT_SIZE_IN_BYTES." + #endif + #else + #error "Invalid debug port size defined. Acceptable values of IDS_DEBUG_PORT_SIZE_IN_BYTES are 1, 2, or 4." + #endif + #endif +#endif + +#if (IDS_DEBUG_PORT & (IDS_DEBUG_PORT_SIZE_IN_BYTES - 1)) != 0 + #error "IDS_DEBUG_PORT must be aligned on IDS_DEBUG_PORT_SIZE_IN_BYTES boundary." +#endif + +/** + * @def STOP_HERE + * (macro) - Causes program to halt. This is @b only for use during active debugging . + * + * Causes the program to halt and display the file number of the source of the + * halt (displayed in decimal). + * + **/ +#if IDSOPT_IDS_ENABLED == TRUE + #ifdef STOP_CODE + #undef STOP_CODE + #endif + #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \ + ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ + (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) + #define STOP_HERE IdsErrorStop (STOP_CODE); +#else + #define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds." +#endif + +/** + * @def ASSERT + * Test an assertion that the given statement is True. + * + * The statement is evaluated to a boolean value. If the statement is True, + * then no action is taken (no error). If the statement is False, a error stop + * is generated to halt the program. Used for testing for fatal errors that + * must be resolved before production. This is used to do parameter checks, + * bounds checking, range checks and 'sanity' checks. + * + * @param[in] conditional Assert that evaluating this conditional results in TRUE. + * + **/ +#ifndef ASSERT + #if IDSOPT_ASSERT_ENABLED == TRUE + #ifdef STOP_CODE + #undef STOP_CODE + #endif + #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \ + ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ + (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) + + #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE)); + #else + #define ASSERT(conditional) + #endif +#endif + +#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE + #undef IDSOPT_ERROR_TRAP_ENABLED + #define IDSOPT_ERROR_TRAP_ENABLED TRUE + #define IDS_CAR_CORRUPTION_CHECK(StdHeader) IdsCarCorruptionCheck(StdHeader) +#else + #define IDS_CAR_CORRUPTION_CHECK(StdHeader) +#endif +/** + * @def DEBUG_CODE + * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable + * + */ +#ifndef DEBUG_CODE + #if IDSOPT_DEBUG_CODE_ENABLED == TRUE + #define DEBUG_CODE(Code) Code + #else + #define DEBUG_CODE(Code) + #endif +#endif + +/** + * @def IDS_ERROR_TRAP + * Trap AGESA Error events with stop code display. + * + * Works similarly to use of "ASSERT (FALSE);" + * + */ +#if IDSOPT_ERROR_TRAP_ENABLED == TRUE + #ifdef STOP_CODE + #undef STOP_CODE + #endif + #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \ + ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ + (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) + + #define IDS_ERROR_TRAP IdsErrorStop (STOP_CODE) +#else + #define IDS_ERROR_TRAP +#endif + +///give the extended Macro default value +#ifndef __IDS_EXTENDED__ + #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS + #define IDS_TRACE_DEFAULT (0) + #define IDS_INITIAL_F15_CZ_PM_STEP + #define IDS_F15_CZ_PM_CUSTOM_STEP + #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader) + #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader) + #define IDS_EXTENDED_HEAP_SIZE 0 + #define IDS_EXT_INCLUDE_F15(file) + #define IDS_EXT_INCLUDE(file) + #define IDS_PAD_4K + #define IDS_EXTENDED_CODE(code) + #define SMU_FIRMWARE_PADS_1K +#endif + +#ifndef IDS_NUM_NV_ITEM + #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM) +#endif + +#define IDS_CMOS_INDEX_PORT 0x70 +#define IDS_CMOS_DATA_PORT 0x71 +#define IDS_CMOS_REGION_START 0x20 +#define IDS_CMOS_REGION_END 0x7F +#define IDS_AP_GET_NV_FROM_CMOS(x) FALSE + +#if IDSOPT_CONTROL_ENABLED == TRUE + #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) \ + AmdIdsCtrlDispatcher ((IdsOption), (DataPtr), (StdHeader)) + + #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) \ + IdsOptionCallout ((CallOutId), (DataPtr), (StdHeader)) + #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE + #undef IDS_AP_GET_NV_FROM_CMOS + #define IDS_AP_GET_NV_FROM_CMOS(x) AmdIdsApGetNvFromCmos(x) + #ifdef IDS_OPT_CMOS_INDEX_PORT + #undef IDS_CMOS_INDEX_PORT + #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT + #endif + + #ifdef IDS_OPT_CMOS_DATA_PORT + #undef IDS_CMOS_DATA_PORT + #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT + #endif + + #ifdef IDS_OPT_CMOS_REGION_START + #undef IDS_CMOS_REGION_START + #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START + #endif + + #ifdef IDS_OPT_CMOS_REGION_END + #undef IDS_CMOS_REGION_END + #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END + #endif + #endif +#else + #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) + + #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) AGESA_SUCCESS +#endif + +/** + * Macro to add a *skip* hook for IDS options + * + * The default minimal action is to do nothing and there is no any code to increase. + * For debug environments, IDS dispatcher function will be called to perform + * the detailed action and to skip AGESA code if necessary. + * + * @param[in] IdsOption IDS Option ID for this hook point + * @param[in, out] DataPtr Data Pointer to override + * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS + * + * + **/ + +#if IDSOPT_CONTROL_ENABLED == TRUE + #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) \ + if (AmdIdsCtrlDispatcher (IdsOption, DataPtr, StdHeader) == IDS_SUCCESS) +#else + #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) +#endif + +/** + * Macro to add a heap manager routine + * + * when memory is allocated the heap manager actually allocates two extra dwords of data, + * one dword buffer before the actual memory, and one dword afterwards. + * a complete heap walk and check to be performed at any time. + * it would ASSERT if the heap is corrupt + * + * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS + * + * + **/ + +// Heap debug feature +#define SENTINEL_BEFORE_VALUE 0x64616548ul // "Head" +#define SENTINEL_AFTER_VALUE 0x6C696154ul // "Tail" +#if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_HEAP_CHECKING == TRUE + #define SIZE_OF_SENTINEL 4 + #define NUM_OF_SENTINEL 2 // Before ("Head") and After ("Tail") + #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE); + #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE); + #define Heap_Check(stdheader) AmdHeapIntactCheck(stdheader) + #else + #define SIZE_OF_SENTINEL 0 + #define NUM_OF_SENTINEL 0 + #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) + #define SET_SENTINEL_AFTER(NodePtr) + #define Heap_Check(stdheader) + #endif +#else + #define SIZE_OF_SENTINEL 0 + #define NUM_OF_SENTINEL 0 + #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) + #define SET_SENTINEL_AFTER(NodePtr) + #define Heap_Check(stdheader) +#endif + +/** + * Macro to add IDT for debugging exception. + * + * A debug feature. Adding a 'jmp $' into every exception handler. + * So debugger could use HDT to skip 'jmp $' and execute the iret, + * then they could find which instruction cause the exception. + * + * @param[in] FunctionId IDS Function ID for this hook point + * @param[in, out] DataPtr Data Pointer to override + * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS + * + * + **/ +#if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE + #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) IdsExceptionTrap (FunctionId, DataPtr, StdHeader) + #else + #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) + #endif +#else + #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) +#endif + + + //Note a is from 0 to 63 +#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a) +//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly +//Memory Masks +#define MEM_SETREG DEBUG_PRINT_SHIFT (0) +#define MEM_GETREG DEBUG_PRINT_SHIFT (1) +#define MEM_FLOW DEBUG_PRINT_SHIFT (2) +#define MEM_STATUS DEBUG_PRINT_SHIFT (3) +#define MEM_UNDEF_BF DEBUG_PRINT_SHIFT (4) +#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5) +#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6) +#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7) +#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8) +#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9) + +//CPU Masks +#define CPU_TRACE DEBUG_PRINT_SHIFT (10) +#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11) +#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12) +#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13) +#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14) +#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15) +#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16) +#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17) +#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18) +#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19) + +//GNB Masks +#define GNB_TRACE DEBUG_PRINT_SHIFT (20) +#define PCIE_MISC DEBUG_PRINT_SHIFT (21) +#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22) +#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23) +#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24) +#define NB_MISC DEBUG_PRINT_SHIFT (25) +#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26) +#define GFX_MISC DEBUG_PRINT_SHIFT (27) +#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28) +#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29) + +//Topology Masks +#define TOPO_TRACE DEBUG_PRINT_SHIFT (30) +#define TOPO_TRACE_RSV1 DEBUG_PRINT_SHIFT (31) +#define TOPO_TRACE_RSV2 DEBUG_PRINT_SHIFT (32) +#define TOPO_TRACE_RSV3 DEBUG_PRINT_SHIFT (33) +#define TOPO_TRACE_RSV4 DEBUG_PRINT_SHIFT (34) +#define TOPO_TRACE_RSV5 DEBUG_PRINT_SHIFT (35) +#define TOPO_TRACE_RSV6 DEBUG_PRINT_SHIFT (36) +#define TOPO_TRACE_RSV7 DEBUG_PRINT_SHIFT (37) +#define TOPO_TRACE_RSV8 DEBUG_PRINT_SHIFT (38) +#define TOPO_TRACE_RSV9 DEBUG_PRINT_SHIFT (39) + +//FCH Masks +#define FCH_TRACE DEBUG_PRINT_SHIFT (40) +#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41) +#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42) +#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43) +#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44) +#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45) +#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46) +#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47) +#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48) +#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49) + +//Other Masks +#define MAIN_FLOW DEBUG_PRINT_SHIFT (50) +#define EVENT_LOG DEBUG_PRINT_SHIFT (51) +#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52) + +//Ids Masks +#define IDS_TRACE DEBUG_PRINT_SHIFT (53) +#define BVM_TRACE DEBUG_PRINT_SHIFT (54) +#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55) +#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56) + +//S3 +#define S3_TRACE DEBUG_PRINT_SHIFT (57) + +//Library function to read/write PCI/MSR registers +#define LIB_PCI_RD DEBUG_PRINT_SHIFT (58) +#define LIB_PCI_WR DEBUG_PRINT_SHIFT (59) + +//AGESA test points +#define TEST_POINT DEBUG_PRINT_SHIFT (60) + +//Reserved for platform log +#define PLAT_RSV1 DEBUG_PRINT_SHIFT (61) +#define PLAT_RSV2 DEBUG_PRINT_SHIFT (62) +#define PLAT_RSV3 DEBUG_PRINT_SHIFT (63) + +#define GNB_TRACE_DEFAULT\ + (\ + GNB_TRACE | PCIE_MISC | NB_MISC | GFX_MISC \ + ) + +#define GNB_TRACE_REG\ + (\ + PCIE_PORTREG_TRACE | PCIE_HOSTREG_TRACE | \ + NB_SMUREG_TRACE | GNB_TRACE_RSV1 \ + ) + +#define GNB_TRACE_ALL\ + (\ + GNB_TRACE_DEFAULT | GNB_TRACE_REG \ + ) + +#define CPU_TRACE_ALL\ + (\ + CPU_TRACE | CPU_TRACE_RSV1 | CPU_TRACE_RSV2 | CPU_TRACE_RSV3 | \ + CPU_TRACE_RSV4 | CPU_TRACE_RSV5 | CPU_TRACE_RSV6 | CPU_TRACE_RSV7 | \ + CPU_TRACE_RSV8 | CPU_TRACE_RSV9\ + ) + +#define MEMORY_TRACE_ALL\ + (\ + MEM_FLOW | MEM_GETREG | MEM_SETREG | MEM_STATUS | \ + MEMORY_TRACE_RSV1 | MEMORY_TRACE_RSV2 | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \ + MEMORY_TRACE_RSV5 | MEMORY_TRACE_RSV6\ + ) + +#define TOPO_TRACE_ALL\ + (\ + TOPO_TRACE | TOPO_TRACE_RSV1 | TOPO_TRACE_RSV2 | TOPO_TRACE_RSV3 | \ + TOPO_TRACE_RSV4 | TOPO_TRACE_RSV5 | TOPO_TRACE_RSV6 | TOPO_TRACE_RSV7 | \ + TOPO_TRACE_RSV8 | TOPO_TRACE_RSV9\ + ) + +#define FCH_TRACE_ALL\ + (\ + FCH_TRACE | FCH_TRACE_RSV1 | FCH_TRACE_RSV2 | FCH_TRACE_RSV3 | \ + FCH_TRACE_RSV4 | FCH_TRACE_RSV5 | FCH_TRACE_RSV6 | FCH_TRACE_RSV7 | \ + FCH_TRACE_RSV8 | FCH_TRACE_RSV9\ + ) + +#define IDS_TRACE_ALL\ + (\ + IDS_TRACE | BVM_TRACE | IDS_TRACE_RSV2 | IDS_TRACE_RSV3\ + ) + +#define OTHER_TRACE_ALL\ + (\ + MAIN_FLOW | EVENT_LOG | PERFORMANCE_ANALYSE\ + ) + + +#define TRACE_MASK_ALL (0xFFFFFFFFFFFFFFFFull) +#ifndef IDS_DEBUG_PRINT_MASK + #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT | MEM_GETREG) +#endif + +/// if no specific define INIT & EXIT will be NULL +#define IDS_HDT_CONSOLE_INIT(x) +#define IDS_HDT_CONSOLE_EXIT(x) + +/// AGESA tracing service +#if IDSOPT_TRACING_ENABLED == TRUE + #ifdef VA_ARGS_SUPPORTED + #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE + #define IDS_HDT_CONSOLE(f, s, ...) AmdIdsDebugPrint (f, s, __VA_ARGS__) + #else + #pragma warning(disable: 4127) + #define IDS_HDT_CONSOLE(f, s, ...) if (f == MEM_FLOW) AmdIdsDebugPrintMem (s, __VA_ARGS__); \ + else if (f == CPU_TRACE) AmdIdsDebugPrintCpu (s, __VA_ARGS__); \ + else if (f == TOPO_TRACE) AmdIdsDebugPrintTopology (s, __VA_ARGS__); \ + else if (f == GNB_TRACE) AmdIdsDebugPrintGnb (s, __VA_ARGS__); \ + else AmdIdsDebugPrint (f, s, __VA_ARGS__) + #endif + #else + #define IDS_HDT_CONSOLE AmdIdsDebugPrint + #endif + #define CONSOLE AmdIdsDebugPrintAll + #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) Code + #define IDS_TIMEOUT_CTL(t) IdsMemTimeOut (t) +#else + #define IDS_HDT_CONSOLE 1 ? (VOID) 0 : AmdIdsDebugPrint + #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) + #define CONSOLE CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds." + #define IDS_TIMEOUT_CTL(t) +#endif + +/// Macros for serial port tracing +#ifdef IDSOPT_SERIAL_PORT + #define IDS_SERIAL_PORT IDSOPT_SERIAL_PORT +#endif + +#ifndef IDS_SERIAL_PORT + #define IDS_SERIAL_PORT 0x3F8 +#endif + +// Macros for redirect IO tracing +#ifdef IDSOPT_DEBUG_PRINT_IO_PORT + #define IDS_DEBUG_PRINT_IO_PORT IDSOPT_DEBUG_PRINT_IO_PORT +#endif + +#ifndef IDS_DEBUG_PRINT_IO_PORT + #define IDS_DEBUG_PRINT_IO_PORT 0x80 +#endif + +#define IDS_DPRAM_BASE 0 +#define IDS_DPRAM_SIZE 0 +///Default policy, shift the old data when buffer full +#define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL FALSE +#if IDSOPT_TRACING_CONSOLE_RAM == TRUE + #ifdef IDSOPT_DPRAM_BASE + #undef IDS_DPRAM_BASE + #define IDS_DPRAM_BASE IDSOPT_DPRAM_BASE + #else + #error "Debug Print Ram Base not specified, please define IDSOPT_DPRAM_BASE in optionsids.h" + #endif + + #ifdef IDSOPT_DPRAM_SIZE + #undef IDS_DPRAM_SIZE + #define IDS_DPRAM_SIZE IDSOPT_DPRAM_SIZE + #else + #error "Debug Print Ram size not specified, please define IDSOPT_DPRAM_SIZE in optionsids.h" + #endif + + #ifdef IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL + #define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL + #endif +#endif +/** + * Macros to add HDT OUT + * + * The default minimal action is to do nothing and there is no any code to increase. + * For debug environments, the debug information can be displayed in HDT or other + * devices. + * + **/ +#if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE + #undef IDS_HDT_CONSOLE_INIT + #undef IDS_HDT_CONSOLE_EXIT + #define IDS_HDT_CONSOLE_INIT(x) AmdIdsHdtOutInit (x) + #define IDS_HDT_CONSOLE_EXIT(x) AmdIdsHdtOutExit (x) + #define IDS_HDT_CONSOLE_S3_EXIT(x) AmdIdsHdtOutS3Exit (x) + #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) AmdIdsHdtOutS3ApExit (x) + + #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) AmdIdsHdtOutBufferFlush (x) + #define IDS_HDT_CONSOLE_ASSERT(x) AmdIdsDebugPrintAssert (x) + #define IDS_FUNCLIST_ADDR ScriptFuncList + #define IDS_FUNCLIST_EXTERN() extern SCRIPT_FUNCTION ScriptFuncList[] +#else + #define IDS_HDT_CONSOLE_S3_EXIT(x) + #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) + #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) + #define IDS_HDT_CONSOLE_ASSERT(x) + #define IDS_FUNCLIST_ADDR NULL + #define IDS_FUNCLIST_EXTERN() +#endif + +#if IDSOPT_TRACING_ENABLED == TRUE + #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE + #undef IDS_HDT_CONSOLE + #define IDS_HDT_CONSOLE IDSOPT_CUSTOMIZE_TRACING_SERVICE + #endif + #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT + #undef IDS_HDT_CONSOLE_INIT + #define IDS_HDT_CONSOLE_INIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT (x) + #endif + #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT + #undef IDS_HDT_CONSOLE_EXIT + #define IDS_HDT_CONSOLE_EXIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT (x) + #endif +#endif + +#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS + +#if IDSOPT_PERF_ANALYSIS == TRUE + #include "IdsPerf.h" + #ifdef STOP_CODE + #undef STOP_CODE + #endif + #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \ + ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ + (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) + + #define IDS_PERF_TIMESTAMP(ID, StdHeader) IdsPerfTimestamp (STOP_CODE, ID, (StdHeader)) + #define IDS_PERF_ANALYSE(StdHeader) IdsPerfAnalyseTimestamp (StdHeader) +#else + #define IDS_PERF_TIMESTAMP(ID, StdHeader) + #define IDS_PERF_ANALYSE(StdHeader) +#endif + +///For IDS feat use +#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull +#define IDS_BSP_ONLY TRUE +#define IDS_ALL_CORES FALSE + +#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_LIBRARY_IDSLIB_FILECODE + +#define IDS_CALLOUT_INIT 0x01 ///< The function data of IDS callout function of initialization. + +#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x83 ///< The function data of IDS callout function of GNB pp fuse table. +#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x84 ///< The function data of IDS callout function of GNB integrated table. +#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x85 ///< The function data of IDS callout function of GNB NB power gate config. +#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x86 ///< The function data of IDS callout function of GNB PCIE power gateconfig. +#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x87 ///< The function data of IDS callout function of GNB pcie platform config. +#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x88 ///< The function data of IDS callout function of GNB pcie PHY config. +#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x89 ///< The function data of IDS callout function of GNB GMM register override +#define IDS_CALLOUT_FCH_INIT_RESET 0x8A ///< The function data of IDS callout function of FchInitReset +#define IDS_CALLOUT_FCH_INIT_ENV 0x8B ///< The function data of IDS callout function of FchInitEnv. +#define IDS_CALLOUT_POWER_PLAN_INIT 0x8C ///< The function data of IDS callout function of Override Power Plan Init +#define IDS_CALLOUT_GET_PERF_BUFFER 0x8D ///< The function data of IDS callout function of get platform performance buffer. +#define IDS_CALLOUT_GNB_PACKAGE_POWER_CONFIG 0x8E ///< The function data of IDS callout function of Bapm Package Power. +#define IDS_CALLOUT_SMU_PORT80_LOGGING_BUFFER 0x8F ///< The function data of IDS callout function of SMU port80 logging buffer. +#define IDS_CALLOUT_GNB_BEFORE_EARLY_INIT 0x90 ///< The function data of IDS callout function of GNB before early init. +#define IDS_CALLOUT_GNB_SMUBIOSTABLE_OVERRIDE 0x91 ///< The function data of IDS callout function of GNB smu bios table. +#define IDS_CALLOUT_GNB_PCIE_AER_CONFIG 0x92 ///< The function data of IDS callout function of GNB PCIE AER config. +#define IDS_CALLOUT_GNB_PCIE_EARLY_PORT_CONFIG 0x93 ///< The function data of IDS callout function of GNB pcie early port config. +#define IDS_CALLOUT_GNB_BUILDOPTIONS_OVERRIDE 0x94 ///< The function data of IDS callout function of GNB build options override. +#define IDS_CALLOUT_GNB_SMUFEATURES_MASK_OVERRIDE 0x95 ///< The function data of IDS callout function of GNB SMU Features MASK override. +#define IDS_CALLOUT_GNB_BEFORE_TXPRESET_LOADING 0x96 ///< The function data of IDS callout function of GNB pcie Tx preset loading sequence. + +/// Function entry for HDT script to call +typedef struct _SCRIPT_FUNCTION { + UINT32 FuncAddr; ///< Function address in ROM + CHAR8 FuncName[40]; ///< Function name +} SCRIPT_FUNCTION; + +/// Data Structure for Mem ECC parameter override +typedef struct { + IN BOOLEAN CfgEccRedirection; ///< ECC Redirection + IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate + IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate + IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate + IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate + IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate + IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood +} ECC_OVERRIDE_STRUCT; + + + + +/** + * AGESA Test Points + * + * These are the values displayed to the user to indicate progress through boot. + * These can be used in a debug environment to stop the debugger at a specific + * test point: + * For SimNow!, this command + * bi 81 w vb 49 + * will stop the debugger on one of the TracePoints (49 is the TP value in this example). + * + */ +typedef enum { + StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs + + // Memory test points + TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface) + TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface) + TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface) + TpProcMemDramInit, ///< 04 .. DRAM initialization + TpProcMemSPDChecking, ///< 05 .. + TpProcMemModeChecking, ///< 06 .. + TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration + TpProcMemSpdTiming, ///< 08 .. + TpProcMemDramMapping, ///< 09 .. + TpProcMemPlatformSpecificConfig, ///< 0A .. + TPProcMemPhyCompensation, ///< 0B .. + TpProcMemStartDcts, ///< 0C .. + TpProcMemBeforeDramInit, ///< 0D .. (Public interface) + TpProcMemPhyFenceTraining, ///< 0E .. + TpProcMemSynchronizeDcts, ///< 0F .. + TpProcMemSystemMemoryMapping, ///< 10 .. + TpProcMemMtrrConfiguration, ///< 11 .. + TpProcMemDramTraining, ///< 12 .. + TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface) + TpProcMemWriteLevelizationTraining, ///< 14 .. + TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start + TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start + TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured + TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL + TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL + TpProcMemReceiverEnableTraining, ///< 1A .. + TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop + TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay + TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern + TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern + TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern + TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel + TpProcMemReceiveDqsTraining, ///< 21 .. + TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay + TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern + TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep + TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay + TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern + TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern + TpProcMemRcvDqsResults, ///< 28 .. Update results + TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window + TpProcMemTransmitDqsTraining, ///< 2A .. + TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep + TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay + TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern + TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern + TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern + TpProcMemTxDqResults, ///< 30 .. Update results + TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window + TpProcMemMaxRdLatencyTraining, ///< 32 .. + TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep + TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay + TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern + TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern + TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern + TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init + TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init + TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init + TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init + TpProcMemEccInitialization, ///< 3C .. ECC initialization + TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init + TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd" + TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd" + TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit" + TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit" + TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining" + TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining" + TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit" + TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit" + TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit + TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT + TpProcMemLvDdr3, ///< 48 .. Before LV DDR3 + TpProcMemInitMCT, ///< 49 .. Before InitMCT + TpProcMemOtherTiming, ///< 4A.. Before OtherTiming + TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping + TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs + TpProcMemMemClr, ///< 4D .. Before MemClr + TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal + TpProcMemDmi, ///< 4F .. Before DMI + TpProcMemEnd, ///< 50 .. End of memory code + + // CPU test points + TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords + TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt + TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling + TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData + TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea + TpProcS3Init, ///< 56 Entry point S3Init + TpProcCpuProcessRegisterTables = 0X58, ///< 58 .. Register table processing + TpProcCpuSetBrandID, ///< 59 .. Set brand ID + TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC + TpProcCpuLoadUcode, ///< 5B .. Load microcode patch + TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point + TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing + TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point + TpProcCpuCoreLeveling, ///< 5F .. Core Leveling + TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up + TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point + TpProcCpuBeforeRelinquishAPsFeatureInit = 0x63, ///< 63 .. Before Relinquishing control of APs feature dispatch point + TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer + TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer + TpProcCpuBeforeAllocateSsdtBuffer = 0x6A, ///< 6A .. Before the P-state init code calls out to allocate a buffer + TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer + TpProcCpuEntryCrat, ///< 6C .. Entry point CreateAcpiCrat + TpProcCpuEntryCdit, ///< 6D .. Entry point CreateAcpiCdit + TpProcCpuEntryScs, ///< 6E .. Entry point InitializeScsFeature + TpProcCpuRunBtc, ///< 6F .. Start of Btc run + TpProcCpuEndBtc, ///< 70 .. End of Btc run + + // Topology test points + TpProcTopologyEntry = 0x71, ///< 71 .. Topology Init begin + TpProcTopologyDone = 0x7C, ///< 7C .. Topology Init complete + + // Extended memory test point + TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2 + TpProcMemSendMRS3, ///< 81 .. Sedding MRS3 + TpProcMemSendMRS1, ///< 82 .. Sending MRS1 + TpProcMemSendMRS0, ///< 83 .. Sending MRS0 + TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read + TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write + TpProcMem2dRdDqsTraining, ///< 86 .. Mem: 2d RdDqs Training begin + TpProcMemBefore2dTrainExtVrefChange,///< 87 .. Mem: Before optional callout to platform BIOS to change External Vref during 2d Training + TpProcMemAfter2dTrainExtVrefChange, ///< 88 .. Mem: After optional callout to platform BIOS to change External Vref during 2d Training + TpProcMemConfigureDCTForGeneral, ///< 89 .. Configure DCT For General use begin + TpProcMemProcConfigureDCTForTraining, ///< 8A .. Configure DCT For training begin + TpProcMemConfigureDCTNonExplicitSeq,///< 8B .. Configure DCT For Non-Explicit + TpProcMemSynchronizeChannels, ///< 8C .. Configure to Sync channels + TpProcMemC6StorageAllocation, ///< 8D .. Allocate C6 Storage + + // Gnb Earlier init + TpGnbEarlierPcieConfigurationInit = 0x90, ///< 90 .. GNB earlier PCIE configuration init + TpGnbEarlierInterface = 0x91, ///< 91 .. GNB earlier interface + // Gnb Early init + TpGnbEarlyInterface = 0x92, ///< 92 .. GNB early interface + TpGnbPcieConfigurationMap, ///< 93 .. GNB early PCIE configuration map + TpGnbPcieEarlyInterface, ///< 94 .. GNB early PCIE interface + //Gnb post init + TpGnbPciePostEarlyInterface = 0x95, ///< 95 .. GNB post early interface + TpGnbGfxConfigPostInterface, ///< 96 .. GNB post GFX config interface + TpGnbGfxPostInterface, ///< 97 .. GNB post GFX interface + // Gnb post after DRAM init + TpGnbPostInterface = 0x98, ///< 98 .. GNB post after DRAM interface + TpGnbPciePostInterface, ///< 99 .. GNB post after DRAM PCIE interface + // Gnb Env init + TpGnbEnvInterface, ///< 9A .. GNB Env Nb interface + TpGnbPcieEnvInterface, ///< 9B .. GNB Env PCIE interface + TpGnbGfxConfigEnvInterface, ///< 9C .. GNB Env GFX Config interface + TpGnbGfxEnvInterface, ///< 9D .. GNB Env GFX interface + // Gnb Mid init + TpGnbGfxConfigMidInterface = 0x9E, ///< 9E .. GNB Mid GFX config interface + TpGnbGfxMidInterface, ///< 9F .. GNB Mid GFX interface + TpPcieMidInterface, ///< A0 .. GNB Mid PCIE interface + TpGnbMidInterface, ///< A1 .. GNB Mid interface + TpGnbSmuMidInterface, ///< A2 .. GNB Mid SMU feature + TpPciePowerGateFeature, ///< A3 .. GNB Mid pcie power gate feature + TpGnbPcieMaxPayloadInterface, ///< A4 .. GNB Mid pcie max payload interface + TpGnbPcieClkPmInterface, ///< A5 .. GNB Mid pcie clk pm port interface + TpGnbPcieAspmInterface, ///< A6 .. GNB Mid pcie ASPM interface + TpGnbNbIoapicInterface, ///< A7 .. GNB Mid IOAPIC interface + // Gnb Late init + TpGnbPcieAlibFeature = 0xA8, ///< A8 .. GNB Late pcie ALIB feature + TpGnbIommuIvrsTable, ///< A9 .. GNB Late pcie IOMMU + TpGnbBtcRun, ///< AA .. GNB Late run BTC + // Gnb S3 Save + TpGnbGfxInitSview = 0xAE, ///< AD .. GNB S3SAVE GFX sview init + TpGnbAlibDispatchFeature = 0xAE, ///< AE .. GNB ALIB dispatch feature + EndGnbTestPoints = 0xAF, ///< AF End of TP range for GNB + + StartFchTestPoints = 0xB0, ///< B0 Entry used for range testing for @b FCH related TPs + TpFchInitResetDispatching, ///< B1 .. FCH InitReset dispatch point + TpFchGppBeforePortTraining, ///< B2 .. Before FCH GPP port training + TpFchGppGen1PortPolling, ///< B3 .. FCH GPP port polling with GEN1 speed + TpFchGppGen2PortPolling, ///< B4 .. FCH GPP port polling with GEN2 speed + TpFchGppAfterPortTraining, ///< B5 .. After FCH GPP port training + TpFchInitEnvDispatching, ///< B6 .. FCH InitEnv dispatch point + TpFchInitMidDispatching, ///< B7 .. FCH InitMid dispatch point + TpFchInitLateDispatching, ///< B8 .. FCH InitLate dispatch point + TpFchGppHotPlugging, ///< B9 .. FCH GPP hot plug event + TpFchGppHotUnplugging, ///< BA .. AFCH GPP hot unplug event + TpFchInitS3EarlyDispatching, ///< BB .. FCH InitS3Early dispatch point + TpFchInitS3LateDispatching, ///< BC .. FCH InitS3Late dispatch point + EndFchTestPoints, ///< BF End of TP range for FCH + + // Interface test points + TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset + TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset + TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery + TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery + TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly + TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly + TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost + TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost + TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv + TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv + TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid + TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid + TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate + TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate + TpIfAmdInitRtbEntry, ///< CE .. Entry to AmdInitRtb + TpIfAmdInitRtbExit, ///< CF .. Exiting from AmdInitRtb + TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume + TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume + TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore + TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore + TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore + TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore + TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog + TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog + TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId + TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId + TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress + TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress + TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore + TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore + TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP + TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP + TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data + TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data + TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer + TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer + TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer + TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer + TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer + TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer + TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP + TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP + TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP + TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP + TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer + TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer + TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer + TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer + TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer + TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer + TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer + TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer + TpReadyToBoot, ///< F8 .. Ready to boot event + // PMU test points + TpProcMemPmuFailed, ///< F9 .. Failed PMU training. + TpIfAmdS3FinalRestoreEntry, ///< FA .. Entry to AmdS3FinalRestore + TpIfAmdS3FinalRestoreExit, ///< FB .. Exiting from AmdS3FinalRestore + + EndAgesaTps = 0xFF, ///< Last defined AGESA TP +} AGESA_TP; + +///Ids Feat description +typedef enum { + IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update + IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate + IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate + IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control + IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size + IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock + IDS_FEAT_DCT_ALLCKE, ///< Feat for all CKE + IDS_FEAT_DCT_ALLCS, ///< Feat for all CS + IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode + IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length + IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down + IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down + IDS_FEAT_HDTOUT, ///< Feat for hdt out + IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config + IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature + IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control + IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping + IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS + IDS_FEAT_COMMON, ///< Common Feat + IDS_FEAT_END = 0xFF ///< End of Common feat +} IDS_FEAT; + +///Ids IDT table function ID +typedef enum { + IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000, ///< Function ID for saving IDTR for BSC + IDS_IDT_RESTORE_IDTR_FOR_BSC, ///< Function ID for restoring IDTR for BSC + IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, ///< Function ID for updating exception vector +} IDS_IDT_FUNC_ID; + +typedef IDS_STATUS IDS_COMMON_FUNC ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC; + +/// Data Structure of IDS Feature block +typedef struct _IDS_FAMILY_FEAT_STRUCT { + IDS_FEAT IdsFeat; ///< Ids Feat ID + BOOLEAN IsBsp; ///< swith for Bsp check + AGESA_IDS_OPTION IdsOption; ///< IDS option + UINT64 CpuFamily; ///< + PIDS_COMMON_FUNC pf_idsoption; ///> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF) + +#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ + PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \ + , Bit7Map + +#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \ + PSO_CKE_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map + +#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \ + PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map + +#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ + PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map + +#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \ + PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel + +#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \ + PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel + +#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \ + PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel + +#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \ + PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket + +#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \ + PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \ + BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24) + +#define DRAM_TECHNOLOGY(SocketID, MemTechType) \ + PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24) + +#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ + Byte6Seed, Byte7Seed, ByteEccSeed) \ + PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ + Byte6Seed, Byte7Seed, ByteEccSeed + +#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ + Byte6Seed, Byte7Seed, ByteEccSeed) \ + PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \ + Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \ + Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8) + +#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \ + PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE + +#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \ + PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE + +#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \ + PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE + +#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \ + PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth + +#define MOTHER_BOARD_LAYERS(Layers) \ + PSO_MOTHER_BOARD_LAYERS, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Layers + +#define MAX_NUMBER_PSO_TABLES 13 +/*---------------------------------------------------------------------------------------- + * CONDITIONAL OVERRIDE TABLE MACROS + *---------------------------------------------------------------------------------------- + */ +#define CONDITION_AND \ + PSO_CONDITION_AND, 0 + +#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \ + PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk + +#define COND_SPD(Byte, Mask, Value) \ + PSO_CONDITION_SPD, 3, Byte, Mask, Value + +#define COND_REG(Access, Offset, Mask, Value) \ + PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \ + ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \ + ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF) + +#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \ + PSO_ACTION_ODT, 9, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \ + Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt + +#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \ + PSO_ACTION_ADDRTMG, 10, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ + (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF) + +#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \ + PSO_ACTION_ODCCONTROL, 10, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ + (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF) + +#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \ + PSO_ACTION_SLEWRATE, 10, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ + (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF) + +#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \ + PSO_ACTION_SPEEDLIMIT, 9, \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \ + (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \ + (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \ + (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF) + + +#define MEMCLK_DIS_MAP_SIZE 13 +#define CKE_TRI_MAP_SIZE 9 +#define ODT_TRI_MAP_SIZE 9 +#define CS_TRI_MAP_SIZE 13 +#define NUMBER_OF_DIMMS_SUPPORTED_SIZE 6 +#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED_SIZE 6 +#define NUMBER_OF_CHIP_SELECTS_SUPPORTED_SIZE 6 +#define NUMBER_OF_CHANNELS_SUPPORTED_SIZE 6 +#define OVERRIDE_DDR_BUS_SPEED_SIZE 13 +#define DRAM_TECHNOLOGY_SIZE 9 +#define SOLDERED_DOWN_SODIMM_TYPE_SIZE 6 +#define MEMORY_POWER_POLICY_OVERRIDE_SIZE 6 +#define MOTHER_BOARD_LAYERS_SIZE 6 + + + +/*---------------------------------------------------------------------------------------- + * END OF CONDITIONAL OVERRIDE TABLE MACROS + *---------------------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------------------- + * TABLE DRIVEN OVERRIDE MACROS + *---------------------------------------------------------------------------------------- + */ +/// Configuration sub-descriptors +typedef enum { + CONFIG_GENERAL, ///< CONFIG_GENERAL + CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT + CONFIG_RC2IBT, ///< CONFIG_RC2IBT + CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE +} Config_Type; + +// ==================== +// Configuration Macros +// ==================== +#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \ + PSO_TBLDRV_CONFIG, 9, \ + CONFIG_GENERAL, \ + DimmPerCH, DimmVolt, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF) + +#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \ + PSO_TBLDRV_CONFIG, 7, \ + CONFIG_SPEEDLIMIT, \ + DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm + +#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \ + PSO_TBLDRV_CONFIG, 10, \ + CONFIG_RC2IBT, \ + DimmPerCH, DimmVolt, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ + NumOfReg + +//================== +// Overriding Macros +//================== +#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \ + PSO_TBLDRV_SPEEDLIMIT, 6, \ + (SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \ + (SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \ + (SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF) + +#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \ + PSO_TBLDRV_ODT_RTTNOM, 2, \ + TgtCS, RttNom + +#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \ + PSO_TBLDRV_ODT_RTTWR, 2, \ + TgtCS, RttWr + +#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \ + PSO_TBLDRV_ODTPATTERN, 16, \ + ((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \ + ((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \ + ((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \ + ((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF) + +#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \ + PSO_TBLDRV_ADDRTMG, 4, \ + ((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF) + +#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \ + PSO_TBLDRV_ODCCTRL, 4, \ + ((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF) + +#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \ + PSO_TBLDRV_SLOWACCMODE, 1, \ + SlowAccMode + +#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \ + PSO_TBLDRV_RC2_IBT, 2, \ + TgtDimm, IBT + +#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \ + PSO_TBLDRV_CONFIG, 1, \ + CONFIG_DONT_CARE, \ + PSO_TBLDRV_MR0_CL, 3, \ + RegValOfTcl, MR0CL13, MR0CL0 + +#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \ + PSO_TBLDRV_CONFIG, 1, \ + CONFIG_DONT_CARE, \ + PSO_TBLDRV_MR0_WR, 2, \ + RegValOfTwr, MR0WR + +#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \ + PSO_TBLDRV_CONFIG, 1, \ + CONFIG_DONT_CARE, \ + PSO_TBLDRV_RC10_OPSPEED, 5, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + MR10OPSPEED + +#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \ + PSO_TBLDRV_LRDIMM_IBT, 4, \ + F0RC8, F1RC0, F1RC1, F1RC2 + +#define TBLDRV_CONFIG_ENTRY_2D_TRAINING(Training2dMode) \ + PSO_TBLDRV_2D_TRAINING, 1, \ + Training2dMode + +//============================ +// Macros for removing entries +//============================ +#define INVALID_CONFIG_FLAG 0x8000 + +#define TBLDRV_INVALID_CONFIG \ + PSO_TBLDRV_INVALID_TYPE, 0 + +/*---------------------------------------------------------------------------------------- + * END OF TABLE DRIVEN OVERRIDE MACROS + *---------------------------------------------------------------------------------------- + */ + +#endif // _PLATFORM_MEMORY_CONFIGURATION_H_ diff --git a/src/vendorcode/amd/pi/00670F00/Include/Topology.h b/src/vendorcode/amd/pi/00670F00/Include/Topology.h new file mode 100644 index 0000000000..099142eb82 --- /dev/null +++ b/src/vendorcode/amd/pi/00670F00/Include/Topology.h @@ -0,0 +1,86 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Topology interface definitions. + * + * Contains AMD AGESA internal interface for topology related data which + * is consumed by code other than Topology Services init. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _TOPOLOGY_H_ +#define _TOPOLOGY_H_ + +// Defines for limiting data structure maximum allocation and limit checking. +#define MAX_NODES 1 +#define MAX_SOCKETS MAX_NODES +#define MAX_DIES 1 + +/** + * Socket and Module to Node Map Item. + * Provide the Node Id and core id range for each module in each processor. + */ +typedef struct { + UINT8 Node; ///< The module's Node id. + UINT8 LowCore; ///< The lowest processor core id for this module. + UINT8 HighCore; ///< The highest processor core id for this module. + UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module. + UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module. + UINT8 TripleCoreComputeUnits;///< The value of TripleCore for this processor module. + UINT8 QuadCoreComputeUnits; ///< The value of QuadCore for this processor module. +} SOCKET_DIE_TO_NODE_ITEM; + +/** + * Socket and Module to Node Map. + * This type is a pointer to the actual map, it can be used for a struct item or + * for typecasting a heap buffer pointer. + */ +typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES]; + +/** + * Node id to Socket Die Map Item. + */ +typedef struct { + UINT8 Socket; ///< socket of the processor containing the Node. + UINT8 Die; ///< the module in the processor which is Node. +} NODE_TO_SOCKET_DIE_ITEM; + +/** + * Node id to Socket Die Map. + */ +typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES]; + +#endif // _TOPOLOGY_H_ -- cgit v1.2.3