From 78790c872c8bae4d0fc2cc4614fa9619c69116cd Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Wed, 26 Apr 2023 19:42:50 +0800 Subject: vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vaule Add UPD edp_panel_t9_ms for eDP panel sequence adjustment. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74788 Reviewed-by: Matt DeVillier Reviewed-by: Jason Glenesk Reviewed-by: Martin Roth Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- src/vendorcode/amd/fsp/mendocino/FspmUpd.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/vendorcode/amd/fsp') diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h index b3d6dc39d9..e2622dde44 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h @@ -102,7 +102,8 @@ typedef struct __packed { /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; /** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1; /** Offset 0x04EA**/ uint8_t edp_panel_t8_ms; - /** Offset 0x04EB**/ uint8_t UnusedUpdSpace2[277]; + /** Offset 0x04EB**/ uint8_t edp_panel_t9_ms; + /** Offset 0x04EC**/ uint8_t UnusedUpdSpace2[276]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; -- cgit v1.2.3