From 177a402b6eb554cf3ad1dce12bc558582877cba3 Mon Sep 17 00:00:00 2001 From: Nikolai Vyssotski Date: Fri, 4 Jun 2021 10:35:15 -0500 Subject: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB EDK2 mandates HOB to be in increments of qword (8). This HOB has 13 elements which causes it be padded with 4 bytes of garbage. This results in coreboot failing intermittently with invalid data. Add "number of entries" field to specify the number of valid entries in the table. BUG=b:190153208 Cq-depend: chrome-internal:3889619 TEST=verify HOB is present and correct size (13) is reported Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Signed-off-by: Nikolai Vyssotski Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/vendorcode/amd/fsp/cezanne/FspGuids.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/vendorcode/amd/fsp') diff --git a/src/vendorcode/amd/fsp/cezanne/FspGuids.h b/src/vendorcode/amd/fsp/cezanne/FspGuids.h index c26daa5a42..0eca78e711 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspGuids.h +++ b/src/vendorcode/amd/fsp/cezanne/FspGuids.h @@ -14,7 +14,7 @@ 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) #define AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID \ - GUID_INIT(0x00D54AA7, 0x0002, 0x47F5, \ - 0x00, 0x78, 0x08, 0x57, 0x00, 0x00, 0xA4, 0x11) + GUID_INIT(0X6D5CD69D, 0XFB24, 0X4461, \ + 0XAA, 0X32, 0X8E, 0XE1, 0XB3, 0X3, 0X31, 0X9C ) #endif /* __FSP_GUIDS__ */ -- cgit v1.2.3