From 799fed98ea57fc9632b7bf95b3f1d79519cbdd15 Mon Sep 17 00:00:00 2001 From: Kerry She Date: Sat, 1 Jan 2011 17:44:07 +0000 Subject: Add AMD SB800 southbridge CIMx code. The main CIMx code is in a src/vendorcode directory and should not be changed with regard to coding style etc. in order to remain easily syncable with the "upstream" AMD code. Signed-off-by: Kerry She Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/vendorcode/amd/cimx/sb800/SBDEF.h | 252 ++++++++++++++++++++++++++++++++++ 1 file changed, 252 insertions(+) create mode 100644 src/vendorcode/amd/cimx/sb800/SBDEF.h (limited to 'src/vendorcode/amd/cimx/sb800/SBDEF.h') diff --git a/src/vendorcode/amd/cimx/sb800/SBDEF.h b/src/vendorcode/amd/cimx/sb800/SBDEF.h new file mode 100644 index 0000000000..bedb61e5dd --- /dev/null +++ b/src/vendorcode/amd/cimx/sb800/SBDEF.h @@ -0,0 +1,252 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +//AMD Library Routines (AMDLIB.C) +UINT8 getNumberOfCpuCores (OUT VOID); +UINT32 readAlink (IN UINT32 Index); +VOID writeAlink (IN UINT32 Index, IN UINT32 Data); +VOID rwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask); + +//AMD Library Routines (LEGACY.C) +UINT32 GetFixUp (OUT VOID); + +//AMD Library Routines (IOLIB.C) +VOID ReadIO (IN UINT16 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID WriteIO (IN UINT16 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID RWIO (IN UINT16 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); + + + +//AMD Library Routines (MEMLIB.C) +VOID ReadMEM (IN UINT32 Address, IN UINT8 OpFlag, IN VOID* Value); +VOID WriteMEM (IN UINT32 Address, IN UINT8 OpFlag, IN VOID* Value); +VOID RWMEM (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); + +//AMD Library Routines (PCILIB.C) +VOID ReadPCI (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID WritePCI (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID RWPCI (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); + +//AMD Library Routines (SBPELIB.C) +/** + * Read Southbridge Revision ID cie Base + * + * + * @retval 0xXXXXXXXX Revision ID + * + */ +UINT8 getRevisionID (OUT VOID); + +/** + * programPciByteTable - Program PCI register by table (8 bits data) + * + * + * + * @param[in] pPciByteTable - Table data pointer + * @param[in] dwTableSize - Table length + * + */ +VOID programPciByteTable (IN REG8MASK* pPciByteTable, IN UINT16 dwTableSize); + +/** + * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data) + * + * + * + * @param[in] pAcpiTbl - Table data pointer + * + */ +VOID programSbAcpiMmioTbl (IN AcpiRegWrite *pAcpiTbl); + +/** + * getChipSysMode - Get Chip status + * + * + * @param[in] Value - Return Chip strap status + * StrapStatus [15.0] - SB800 chip Strap Status + * @li 0001 - Not USED FWH + * @li 0002 - Not USED LPC ROM + * @li 0004 - EC enabled + * @li 0008 - Reserved + * @li 0010 - Internal Clock mode + * + */ +VOID getChipSysMode (IN VOID* Value); + +/** + * Read Southbridge CIMx configuration structure pointer + * + * + * + * @retval 0xXXXXXXXX CIMx configuration structure pointer. + * + */ +AMDSBCFG* getConfigPointer (OUT VOID); + +//AMD Library Routines (PMIOLIB.C) +/** + * Read PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * + */ +VOID ReadPMIO (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * + */ +VOID WritePMIO (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * RWPMIO - Read/Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * + */ +VOID RWPMIO (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask); + +//AMD Library Routines (PMIO2LIB.C) + +/** + * Read PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * + */ +VOID ReadPMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * Write PMIO 2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * + */ +VOID WritePMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * RWPMIO2 - Read/Write PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * + */ +VOID RWPMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask); +//AMD Library Routines (ECLIB.C) +// ECLIB Routines + +// #ifndef NO_EC_SUPPORT + +/** + * EnterEcConfig - Force EC into Config mode + * + * + * + * + */ +VOID EnterEcConfig (VOID); + +/** + * ExitEcConfig - Force EC exit Config mode + * + * + * + * + */ +VOID ExitEcConfig (VOID); + +/** + * ReadEC8 - Read EC register data + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Read Data Buffer + * + */ +VOID ReadEC8 (IN UINT8 Address, IN UINT8* Value); + +/** + * WriteEC8 - Write date into EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Write Data Buffer + * + */ +VOID WriteEC8 (IN UINT8 Address, IN UINT8* Value); + +/** + * RWEC8 - Read/Write EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] AndMask - Data And Mask 8 bits + * @param[in] OrMask - Data OR Mask 8 bits + * + */ +VOID RWEC8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask); + +/** + * IsZoneFuncEnable - check every zone support function with BitMap from user define + * + */ +BOOLEAN IsZoneFuncEnable ( UINT16 Flag, UINT8 func, UINT8 Zone); + +VOID sbECfancontrolservice (IN AMDSBCFG* pConfig); +VOID SBIMCFanInitializeS3 (VOID); +VOID GetSbAcpiMmioBase (OUT UINT32* AcpiMmioBase); +VOID GetSbAcpiPmBase (OUT UINT16* AcpiPmBase); + +// #endif + -- cgit v1.2.3