From e18e6427d0f3261f9ec361d4418b8fe1dd7cc469 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 3 Jun 2017 20:03:18 -0600 Subject: src: change coreboot to lowercase MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Patrick Georgi --- src/vendorcode/amd/cimx/sb700/SBPort.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/vendorcode/amd/cimx/sb700/SBPort.c') diff --git a/src/vendorcode/amd/cimx/sb700/SBPort.c b/src/vendorcode/amd/cimx/sb700/SBPort.c index 6c5740bf37..d1484812b9 100644 --- a/src/vendorcode/amd/cimx/sb700/SBPort.c +++ b/src/vendorcode/amd/cimx/sb700/SBPort.c @@ -222,7 +222,7 @@ void sbPowerOnInit (AMDSBCFG *pConfig){ if (dbVar0 > 4) { dbVar0 = 0; } - //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0); + //KZ [061811]-It's used wrong BIOS SIZE for coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0); if (pConfig->Spi33Mhz) //spi reg0c[13:12] to 01h to run spi 33Mhz in system bios -- cgit v1.2.3