From 704ccafb392212cffc3810197da5cb2b619f1ba6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 16 May 2022 14:55:46 +0200 Subject: vendorcode/amd/agesa/f14: Fix improper use of .data AGESA has a lot of code in the .data section which is for initialized data, that in fact should be .rodata. This adds the 'CONST' keyword everywhere it is needed. TEST: See in the .elf file (e.g. using readelf) that there is nothing in .data section. Change-Id: I657d09f05070f5a88a4a162872c961db869a8df3 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/64399 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Stefan Reinauer --- .../agesa/f14/Config/OptionCpuFeaturesInstall.h | 2 +- .../amd/agesa/f14/Config/OptionFamily14hInstall.h | 10 ++--- .../amd/agesa/f14/Config/OptionGnbInstall.h | 14 +++---- .../amd/agesa/f14/Config/OptionMemoryInstall.h | 46 +++++++++++----------- .../agesa/f14/Config/OptionMultiSocketInstall.h | 2 +- .../amd/agesa/f14/Config/OptionPstateInstall.h | 4 +- .../amd/agesa/f14/Config/PlatformInstall.h | 6 +-- .../amd/agesa/f14/Include/OptionMemory.h | 6 +-- src/vendorcode/amd/agesa/f14/Proc/CPU/S3.h | 12 +++--- .../amd/agesa/f14/Proc/Common/AmdInitEarly.c | 2 +- .../GnbPcieInitLibV1/PcieTopologyServices.c | 2 +- .../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c | 6 +-- .../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h | 4 +- .../GNB/Modules/GnbPcieTrainingV1/PcieTraining.c | 6 +-- .../f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h | 9 ++--- .../amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c | 8 ++-- .../amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h | 12 +++--- .../GNB/PCIe/Family/0x14/F14PcieWrapperServices.c | 2 +- .../Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h | 2 +- .../amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c | 3 +- .../amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c | 2 +- .../amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c | 4 +- .../amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c | 10 ++--- src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c | 4 +- src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h | 4 +- .../amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c | 7 ++-- src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h | 5 +-- 27 files changed, 92 insertions(+), 102 deletions(-) (limited to 'src/vendorcode/amd/agesa') diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionCpuFeaturesInstall.h index d4dc2b3e93..c5519326e0 100644 --- a/src/vendorcode/amd/agesa/f14/Config/OptionCpuFeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/OptionCpuFeaturesInstall.h @@ -58,7 +58,7 @@ #include "OptionLowPwrPstateInstall.h" #include "OptionPreserveMailboxInstall.h" -CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] = +CONST CPU_FEATURE_DESCRIPTOR* ROMDATA CONST SupportedCpuFeatureList[] = { OPTION_HW_C1E_FEAT OPTION_MSG_BASED_C1E_FEAT diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionFamily14hInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionFamily14hInstall.h index 10065cfbb8..2750ac366f 100644 --- a/src/vendorcode/amd/agesa/f14/Config/OptionFamily14hInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/OptionFamily14hInstall.h @@ -93,7 +93,7 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled; extern CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable; #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F14OnRegisterTables[] = + CONST REGISTER_TABLE ROMDATA * CONST F14OnRegisterTables[] = { #if BASE_FAMILY_PCI == TRUE &F14PciRegisterTable, @@ -351,7 +351,7 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled; #define F14_ON_UCODE_119 &CpuF14MicrocodePatch05000119, #endif - CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[] = + CONST MICROCODE_PATCHES ROMDATA * CONST CpuF14OnMicroCodePatchArray[] = { F14_ON_UCODE_119 F14_ON_UCODE_29 @@ -416,7 +416,7 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled; */ #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F14UnknownRegisterTables[] = + CONST REGISTER_TABLE ROMDATA * CONST F14UnknownRegisterTables[] = { #if BASE_FAMILY_PCI == TRUE &F14PciRegisterTable, @@ -644,7 +644,7 @@ CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14UnknownServices = #endif #if BRAND_STRING1 == TRUE - CONST CPU_BRAND_TABLE ROMDATA *F14BrandIdString1Tables[] = + CONST CPU_BRAND_TABLE ROMDATA * CONST F14BrandIdString1Tables[] = { F14_FT1_BRANDSTRING1 }; @@ -653,7 +653,7 @@ CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14UnknownServices = #endif #if BRAND_STRING2 == TRUE - CONST CPU_BRAND_TABLE ROMDATA *F14BrandIdString2Tables[] = + CONST CPU_BRAND_TABLE ROMDATA *CONST F14BrandIdString2Tables[] = { F14_FT1_BRANDSTRING2 }; diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h index 26acb3f279..f77c7baaa9 100644 --- a/src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h @@ -119,7 +119,7 @@ #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard #endif -GNB_BUILD_OPTIONS GnbBuildOptions = { +CONST GNB_BUILD_OPTIONS GnbBuildOptions = { CFG_IGFX_AS_PCIE_EP, CFG_LCLK_DEEP_SLEEP_EN, CFG_LCLK_DPM_EN, @@ -190,7 +190,7 @@ GNB_BUILD_OPTIONS GnbBuildOptions = { #define OPTION_PCIEINITATEARLY_ENTRY #endif //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { + CONST OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { OPTION_NBINITATEARLY_ENTRY OPTION_F12NBSMUINITFEATURE_ENTRY OPTION_F14NBSMUINITFEATURE_ENTRY @@ -254,14 +254,14 @@ GNB_BUILD_OPTIONS GnbBuildOptions = { #define OPTION_PCIEINITATPOST_ENTRY #endif //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { + CONST OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { OPTION_PCIEINITATPOSTEARLY_ENTRY OPTION_GFXCONFIGPOSTINTERFACE_ENTRY OPTION_GFXINITATPOST_ENTRY {0, NULL} }; - OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { + CONST OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { OPTION_NBINITATPOST_ENTRY OPTION_PCIEINITATPOST_ENTRY {0, NULL} @@ -344,7 +344,7 @@ GNB_BUILD_OPTIONS GnbBuildOptions = { #endif //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = { + CONST OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = { OPTION_NBFUSETABLEFEATURE_ENTRY OPTION_NBINITATENVT_ENTRY OPTION_PCIEINITATENV_ENTRY @@ -445,7 +445,7 @@ GNB_BUILD_OPTIONS GnbBuildOptions = { #define OPTION_NBINITATLATEPOST_ENTRY #endif //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = { + CONST OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = { OPTION_GFXINITATMIDPOST_ENTRY OPTION_GFXINTEGRATEDINFOTABLE_ENTRY OPTION_GNBCABLESAFEENTRY_ENTRY @@ -471,7 +471,7 @@ GNB_BUILD_OPTIONS GnbBuildOptions = { #define OPTION_PCIEALIBFEATURE_ENTRY #endif //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = { + CONST OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = { OPTION_PCIEALIBFEATURE_ENTRY {0, NULL} }; diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h index 600ae9b4e8..367ad62226 100644 --- a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h @@ -171,7 +171,7 @@ BOOLEAN MemFS3DefConstructorRet ( #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef, #endif - MEM_FLOW_CFG* memFlowControlInstalled[] = { + MEM_FLOW_CFG* CONST memFlowControlInstalled[] = { MEM_MAIN_FLOW_CONTROL_PTR_ON NULL }; @@ -367,7 +367,7 @@ BOOLEAN MemFS3DefConstructorRet ( #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet #endif - MEM_FEAT_BLOCK_NB MemFeatBlockOn = { + CONST MEM_FEAT_BLOCK_NB MemFeatBlockOn = { MEM_FEAT_BLOCK_NB_STRUCT_VERSION, MemFDefRet, MEM_FEATURE_BANK_INTERLEAVE, @@ -399,7 +399,7 @@ BOOLEAN MemFS3DefConstructorRet ( * MAIN FEATURE BLOCK *--------------------------------------------------------------------------------------------------- */ - MEM_FEAT_BLOCK_MAIN MemFeatMain = { + CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = { MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION, MEM_MAIN_FEATURE_TRAINING, MEM_MAIN_FEATURE_DIMM_EXCLUDE, @@ -470,7 +470,7 @@ BOOLEAN MemFS3DefConstructorRet ( #else #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3ON = { + CONST MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3ON = { MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, TECH_TRAIN_ENTER_HW_TRN_DDR3, TECH_TRAIN_SW_WL_DDR3, @@ -513,7 +513,7 @@ BOOLEAN MemFS3DefConstructorRet ( #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 } - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { + CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON MEM_TECH_ENABLE_TRAINING_SEQUENCE_END }; @@ -525,7 +525,7 @@ BOOLEAN MemFS3DefConstructorRet ( */ #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control + OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = { // Training flow control NB_TRAIN_FLOW_DDR2, NB_TRAIN_FLOW_DDR3, }; @@ -535,7 +535,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ - MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed + MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = { // Types of technology installed MEM_TECH_CONSTRUCTOR_DDR3 NULL }; @@ -569,7 +569,7 @@ BOOLEAN MemFS3DefConstructorRet ( #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledON[MAX_FF_TYPES] = { PLAT_SP_ON_FF_SDIMM3 PLAT_SP_ON_FF_UDIMM3 NULL @@ -622,7 +622,7 @@ BOOLEAN MemFS3DefConstructorRet ( #define PSC_ON_SODIMM_DDR3 #endif - MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { + MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = { PSC_ON_UDIMM_DDR3 PSC_ON_RDIMM_DDR3 PSC_ON_SODIMM_DDR3 @@ -644,7 +644,7 @@ BOOLEAN MemFS3DefConstructorRet ( #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { + MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = { MEM_PSC_FLOW_BLOCK_END }; @@ -659,7 +659,7 @@ BOOLEAN MemFS3DefConstructorRet ( #else //#if (OPTION_LRDIMMS == FALSE) #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef #endif - MEM_TECH_LRDIMM memLrdimmSupported = { + CONST MEM_TECH_LRDIMM memLrdimmSupported = { MEM_TECH_LRDIMM_STRUCT_VERSION, MEM_TECH_FEATURE_LRDIMM_INIT }; @@ -670,7 +670,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ - MEM_FLOW_CFG* memFlowControlInstalled[] = { + MEM_FLOW_CFG* CONST memFlowControlInstalled[] = { NULL }; /*--------------------------------------------------------------------------------------------------- @@ -679,7 +679,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ - OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control + OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = { // Training flow control NULL, NULL, }; @@ -689,7 +689,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ - MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed + MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = { // Types of technology installed NULL }; @@ -699,13 +699,13 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ - UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; + CONST UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; /*--------------------------------------------------------------------------------------------------- * DEFAULT MAIN FEATURE BLOCK *--------------------------------------------------------------------------------------------------- */ - MEM_FEAT_BLOCK_MAIN MemFeatMain = { + CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = { 0 }; @@ -727,10 +727,10 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ #if OPTION_DDR3 - MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { + CONST MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { 0 }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { + CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { { 0 } }; #endif @@ -742,7 +742,7 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ #if (OPTION_MEMCTLR_ON == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledON[MAX_FF_TYPES] = { NULL }; #endif @@ -751,7 +751,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *---------------------------------------------------------------------- */ - MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { + MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = { NULL }; @@ -760,11 +760,11 @@ BOOLEAN MemFS3DefConstructorRet ( * *---------------------------------------------------------------------- */ - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { + MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = { NULL }; - MEM_TECH_LRDIMM memLrdimmSupported = { + CONST MEM_TECH_LRDIMM memLrdimmSupported = { MEM_TECH_LRDIMM_STRUCT_VERSION, NULL }; @@ -776,7 +776,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ -MEM_NB_SUPPORT memNBInstalled[] = { +CONST MEM_NB_SUPPORT memNBInstalled[] = { MEM_NB_SUPPORT_ON MEM_NB_SUPPORT_END }; diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionMultiSocketInstall.h index 244bbba996..d664725440 100644 --- a/src/vendorcode/amd/agesa/f14/Config/OptionMultiSocketInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/OptionMultiSocketInstall.h @@ -80,7 +80,7 @@ #endif /* Declare the instance of the DMI option configuration structure */ -OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = { +CONST OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = { MULTISOCKET_STRUCT_VERSION, GET_NUM_PM_STEPS, CORE0_PM_TASK, diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h index 19c8e9aa9b..e7c0a1615f 100644 --- a/src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h @@ -184,13 +184,13 @@ #endif /* Declare the instance of the PSTATE option configuration structure */ -OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { +CONST OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { PSTATE_STRUCT_VERSION, USER_PSTATE_OPTION_GATHER, USER_PSTATE_OPTION_LEVEL }; -OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = { +CONST OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = { PSTATE_STRUCT_VERSION, USER_SSDT_MAIN, USER_PSTATE_OPTION_MAIN, diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h index 2317daf23a..53b2d61d93 100644 --- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h @@ -51,7 +51,7 @@ * ****************************************************************************/ -VOLATILE AMD_MODULE_HEADER mCpuModuleID = { +CONST AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , Int32FromChar ('0', '0', '0', '0'), @@ -1288,7 +1288,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Generate the output structures (defaults tables) * ****************************************************************************/ -BUILD_OPT_CFG UserOptions = { +CONST BUILD_OPT_CFG UserOptions = { { // AGESA version string AGESA_CODE_SIGNATURE, // code header Signature AGESA_PACKAGE_STRING, // 8 character ID @@ -1444,7 +1444,7 @@ CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = #if IDSOPT_IDS_ENABLED == TRUE #if IDSOPT_TRACING_ENABLED == TRUE #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y) - CONST CHAR8 *BldOptDebugOutput[] = { + CONST CHAR8 * CONST BldOptDebugOutput[] = { #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE //Build Option Area MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS) diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h index 8866792aff..cc9c89ff6f 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h @@ -126,7 +126,7 @@ typedef BOOLEAN OPTION_MEM_FEATURE_MAIN ( typedef BOOLEAN MEM_NB_CONSTRUCTOR ( IN OUT MEM_NB_BLOCK *NBPtr, IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, + CONST IN MEM_FEAT_BLOCK_NB *FeatPtr, IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad IN UINT8 NodeID ); @@ -243,7 +243,7 @@ typedef struct _MEM_NB_SUPPORT { UINT16 MemNBSupportVersion; ///< Version of northbridge support. MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor. MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT. - MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block. + CONST MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block. MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor. MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification. } MEM_NB_SUPPORT; @@ -263,7 +263,7 @@ typedef struct _MEM_FEAT_TRAIN_SEQ { UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block. OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function. OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function. - MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block. + CONST MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block. } MEM_FEAT_TRAIN_SEQ; /** diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.h index b854345c76..fdcb54d415 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.h @@ -261,24 +261,24 @@ typedef struct { typedef struct { UINT16 Version; ///< Version of header UINT16 NumRegisters; ///< Number of registers in the list - PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers + CONST PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + CONST PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers } PCI_REGISTER_BLOCK_HEADER; /// S3 'conditional' PCI register list header. typedef struct { UINT16 Version; ///< Version of header UINT16 NumRegisters; ///< Number of registers in the list - CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers + CONST CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + CONST PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers } CPCI_REGISTER_BLOCK_HEADER; /// S3 MSR register list header. typedef struct { UINT16 Version; ///< Version of header UINT16 NumRegisters; ///< Number of registers in the list - MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers + CONST MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + CONST MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers } MSR_REGISTER_BLOCK_HEADER; /// S3 'conditional' MSR register list header. diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c index 5709a49392..403233292a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c @@ -76,7 +76,7 @@ RDATA_GROUP (G1_PEICC) * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */ -EXECUTION_CACHE_REGION InitExeCacheMap[] = +CONST EXECUTION_CACHE_REGION InitExeCacheMap[] = { {0x00000000, 0x00000000}, {0x00000000, 0x00000000}, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index 68a2dcd402..f067c03317 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -132,7 +132,7 @@ PcieTopologyPrepareForReconfig ( } -UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; +CONST UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; /*----------------------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c index 3911dbf356..ff425c5c16 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c @@ -135,7 +135,7 @@ BOOLEAN PcieUtilSearchArray ( IN UINT8 *Buf1, IN UINTN Buf1Length, - IN UINT8 *Buf2, + CONST IN UINT8 *Buf2, IN UINTN Buf2Length ) { @@ -143,7 +143,7 @@ PcieUtilSearchArray ( CurrentBuf1Ptr = Buf1; while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { UINT8 *SourceBufPtr; - UINT8 *PatternBufPtr; + CONST UINT8 *PatternBufPtr; UINTN PatternBufLength; SourceBufPtr = CurrentBuf1Ptr; PatternBufPtr = Buf2; @@ -375,7 +375,7 @@ PcieUtilGetWrapperLaneBitMap ( VOID PciePortProgramRegisterTable ( - IN PCIE_PORT_REGISTER_ENTRY *Table, + CONST IN PCIE_PORT_REGISTER_ENTRY *Table, IN UINTN Length, IN PCIe_ENGINE_CONFIG *Engine, IN BOOLEAN S3Save, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h index 7ddaf92753..1f86ea6ba2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h @@ -66,7 +66,7 @@ BOOLEAN PcieUtilSearchArray ( IN UINT8 *Buf1, IN UINTN Buf1Length, - IN UINT8 *Buf2, + CONST IN UINT8 *Buf2, IN UINTN Buf2Length ); @@ -112,7 +112,7 @@ PcieUtilGetWrapperLaneBitMap ( VOID PciePortProgramRegisterTable ( - IN PCIE_PORT_REGISTER_ENTRY *Table, + CONST IN PCIE_PORT_REGISTER_ENTRY *Table, IN UINTN Length, IN PCIe_ENGINE_CONFIG *Engine, IN BOOLEAN S3Save, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c index d546f90dfe..26d33b1ab1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c @@ -342,8 +342,8 @@ PcieTrainingDetectPresence ( } } -UINT8 FailPattern1 [] = {0x2a, 0x6}; -UINT8 FailPattern2 [] = {0x2a, 0x9}; +CONST UINT8 FailPattern1 [] = {0x2a, 0x6}; +CONST UINT8 FailPattern2 [] = {0x2a, 0x9}; /*----------------------------------------------------------------------------------------*/ /** @@ -862,4 +862,4 @@ PcieTrainingDebugDumpPortState ( CurrentEngine->Type.Port.TimeStamp ); } -) \ No newline at end of file +) diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h index 6f196c8e7a..6ae8dd85bf 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h @@ -47,7 +47,7 @@ #ifndef _F14NBSMUFIRMWARE_H_ #define _F14NBSMUFIRMWARE_H_ -UINT32 DataBlock0[] = { +CONST UINT32 DataBlock0[] = { 0x01060100, 0x68d699d6, 0xbdff018e, @@ -1410,7 +1410,7 @@ UINT32 DataBlock0[] = { 0x0001c004 }; -UINT32 DataBlock1[] = { +CONST UINT32 DataBlock1[] = { 0x3f903f90, 0x3f903f90, 0x3f903f90, @@ -1429,7 +1429,7 @@ UINT32 DataBlock1[] = { 0x08900890 }; -SMU_FIRMWARE_BLOCK FmBlockArray[] = { +CONST SMU_FIRMWARE_BLOCK FmBlockArray[] = { { 0x9000, 0x550, @@ -1442,7 +1442,7 @@ SMU_FIRMWARE_BLOCK FmBlockArray[] = { } }; -SMU_FIRMWARE_HEADER Fm = { +CONST SMU_FIRMWARE_HEADER Fm = { { 0x1, 0x601 }, @@ -1450,4 +1450,3 @@ SMU_FIRMWARE_HEADER Fm = { &FmBlockArray[0] }; #endif - diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c index bf1396de55..6e5d83daa2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c @@ -207,7 +207,7 @@ VOID NbSmuIndirectWriteEx ( IN UINT8 Address, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ) { @@ -271,7 +271,7 @@ VOID NbSmuIndirectWrite ( IN UINT8 Address, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ) { @@ -325,7 +325,7 @@ NbSmuIndirectWriteS3Script ( VOID NbSmuRcuRegisterWrite ( IN UINT16 Address, - IN UINT32 *Value, + CONST IN UINT32 *Value, IN UINT32 Count, IN BOOLEAN S3Save, IN AMD_CONFIG_PARAMS *StdHeader @@ -599,7 +599,7 @@ NbSmuSrbmRegisterWrite ( VOID NbSmuFirmwareDownload ( - IN SMU_FIRMWARE_HEADER *Firmware, + CONST SMU_FIRMWARE_HEADER *Firmware, IN AMD_CONFIG_PARAMS *StdHeader ) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h index 7d28024080..e2834cef3c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h @@ -68,14 +68,14 @@ typedef struct { typedef struct { UINT16 Address; ///< Block Address UINT16 Length; ///< Block length in DWORD - UINT32 *Data; ///< Pointer to data array + CONST UINT32 *Data; ///< Pointer to data array } SMU_FIRMWARE_BLOCK; /// Firmware header typedef struct { SMU_FIRMWARE_REV Revision; ///< Revision info UINT16 NumberOfBlock; ///< Number of blocks - SMU_FIRMWARE_BLOCK *BlockArray; ///< Pointer to block definition array + CONST SMU_FIRMWARE_BLOCK *BlockArray; ///< Pointer to block definition array } SMU_FIRMWARE_HEADER; /// SMU indirect register write data context @@ -107,7 +107,7 @@ VOID NbSmuIndirectWriteEx ( IN UINT8 Address, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -115,7 +115,7 @@ VOID NbSmuIndirectWrite ( IN UINT8 Address, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -129,7 +129,7 @@ NbSmuIndirectWriteS3Script ( VOID NbSmuRcuRegisterWrite ( IN UINT16 Address, - IN UINT32 *Value, + CONST IN UINT32 *Value, IN UINT32 Count, IN BOOLEAN S3Save, IN AMD_CONFIG_PARAMS *StdHeader @@ -195,7 +195,7 @@ NbSmuReadEfuseField ( VOID NbSmuFirmwareDownload ( - IN SMU_FIRMWARE_HEADER *Firmware, + CONST IN SMU_FIRMWARE_HEADER *Firmware, IN AMD_CONFIG_PARAMS *StdHeader ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c index 01feea4c7f..d676924f76 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c @@ -108,7 +108,7 @@ PcieOnGetGppConfigurationValue ( * T A B L E S *---------------------------------------------------------------------------------------- */ -PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = { +CONST PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = { { PHY_SPACE (0, 0, D0F0xE4_PHY_6440_ADDRESS), D0F0xE4_PHY_6440_RxInCalForce_MASK, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h index cb40989dc0..ce2508449a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h @@ -47,7 +47,7 @@ #define _ONTARIOCOMPLEXDATA_H_ STATIC -F14_COMPLEX_CONFIG ComplexData = { +CONST F14_COMPLEX_CONFIG ComplexData = { //Silicon { DESCRIPTOR_TERMINATE_LIST, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c index 318bb82566..3e2e53ef10 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c @@ -135,7 +135,7 @@ PciePortsVisibilityControl ( } -PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = { +CONST PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = { { D0F0xE4_CORE_0020_ADDRESS, D0F0xE4_CORE_0020_CiRcOrderingDis_MASK, @@ -372,4 +372,3 @@ PciePostInit ( IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus); return AgesaStatus; } - diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c index 39692869b2..63ff5f5d3f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c @@ -79,7 +79,7 @@ *---------------------------------------------------------------------------------------- */ -PCIE_PORT_REGISTER_ENTRY PortInitTable [] = { +CONST PCIE_PORT_REGISTER_ENTRY PortInitTable [] = { { DxF0xE4_x02_ADDRESS, DxF0xE4_x02_RegsLcAllowTxL1Control_MASK, diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c index 411caf843c..b06d8a314e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c @@ -91,7 +91,7 @@ BOOLEAN STATIC MemMSetCSRNb ( IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, + CONST IN PCI_SPECIAL_CASE *SpecialCases, IN PCI_ADDR PciAddr, IN UINT32 Value ); @@ -471,7 +471,7 @@ BOOLEAN STATIC MemMSetCSRNb ( IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, + CONST IN PCI_SPECIAL_CASE *SpecialCases, IN PCI_ADDR PciAddr, IN UINT32 Value ) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c index 7dc58d00bc..60d8e31829 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c @@ -133,7 +133,7 @@ MemS3ResumeConstructNBBlockON ( * *---------------------------------------------------------------------------- */ -PCI_SPECIAL_CASE PciSpecialCaseFuncON[] = { +CONST PCI_SPECIAL_CASE PciSpecialCaseFuncON[] = { {MemNS3GetCSRNb, MemNS3SetCSRNb}, {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}, {MemNS3DisNbPsDbgNb, MemNS3DisNbPsDbgNb}, @@ -144,7 +144,7 @@ PCI_SPECIAL_CASE PciSpecialCaseFuncON[] = { {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb} }; -PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorON[] = { +CONST PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorON[] = { {{0, 2, 0}, FUNC_2, 0x110, 0x00000708}, {{0, 0, 0}, FUNC_1, 0x40, 0x0FFF0003}, {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0000}, @@ -245,7 +245,7 @@ CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefON = { PciSpecialCaseFuncON }; -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorON[] = { +CONST CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorON[] = { // DCT0 {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, @@ -298,7 +298,7 @@ CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefON = { PciSpecialCaseFuncON }; -MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorON[] = { +CONST MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorON[] = { {{0, 0, 0}, 0xC0010010, 0x00000000007F0000}, {{0, 0, 0}, 0xC001001A, 0x0000000FFF800000}, {{0, 0, 0}, 0xC001001D, 0x0000000FFF800000}, @@ -312,7 +312,7 @@ CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefON = { NULL }; -VOID *MemS3RegListON[] = { +VOID * CONST MemS3RegListON[] = { (VOID *)&S3PciPreSelfRefON, NULL, NULL, diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c index a0703ccece..6f45fd8d96 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c @@ -117,7 +117,7 @@ BOOLEAN MemConstructNBBlockON ( IN OUT MEM_NB_BLOCK *NBPtr, IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, + CONST IN MEM_FEAT_BLOCK_NB *FeatPtr, IN MEM_SHARED_DATA *SharedPtr, IN UINT8 NodeID ) @@ -460,5 +460,3 @@ memNEnableTrainSequenceON ( } return Retval; } - - diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h index 8d71f3d342..30fc2fa76f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h @@ -83,7 +83,7 @@ BOOLEAN MemConstructNBBlockON ( IN OUT MEM_NB_BLOCK *NBPtr, IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, + CONST IN MEM_FEAT_BLOCK_NB *FeatPtr, IN MEM_SHARED_DATA *SharedPtr, IN UINT8 NodeID ); @@ -252,5 +252,3 @@ MemNResetRxFifoPtrON ( IN OUT VOID *OptParam ); #endif /* _MNON_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c index f1fa73e47a..ae60fd5f69 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c @@ -102,7 +102,7 @@ RDATA_GROUP (G1_PEICC) * Sweep Table For Byte Training without insertion delay * */ -DQS_POS_SWEEP_TABLE SweepTableByte[] = +CONST DQS_POS_SWEEP_TABLE SweepTableByte[] = { // Begin End Inc/Dec Step EndResult Edge { 0x00, 0x1F, INC_DELAY, 4, 0xFFFF, LEFT_EDGE}, /// For Left Edge, start from 0 and Increment to 0x1F by 4 until all PASS @@ -114,7 +114,7 @@ DQS_POS_SWEEP_TABLE SweepTableByte[] = * Sweep Table For Byte Training with insertion delay * */ -DQS_POS_SWEEP_TABLE InsSweepTableByte[] = +CONST DQS_POS_SWEEP_TABLE InsSweepTableByte[] = { // Begin End Inc/Dec Step EndResult Edge { 0x00, -0x20, DEC_DELAY, -4, 0xFE00, LEFT_EDGE}, /// For Left Edge, start from 0 and Decrement to -0x20 by -4 until all FAIL @@ -402,7 +402,7 @@ MemTTrainDQSEdgeDetect ( { MEM_NB_BLOCK *NBPtr; DIE_STRUCT *MCTPtr; - DQS_POS_SWEEP_TABLE *SweepTablePtr; + CONST DQS_POS_SWEEP_TABLE *SweepTablePtr; UINT8 SweepTableSize; SWEEP_INFO SweepData; BOOLEAN Status; @@ -893,4 +893,3 @@ MemTDataEyeSave ( ChanPtr->WrDatDlys[Dimm] = EyeCenter + ChanPtr->WrDqsDlys[Dimm]; } } - diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h index a17906a448..eec43b050a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h @@ -465,7 +465,7 @@ typedef struct _MEM_NB_BLOCK { CH_DEF_STRUCT *ChannelPtr; ///< point to current channel data SPD_DEF_STRUCT *SPDPtr; ///< Point to SPD data for current DCT. struct _MEM_TECH_BLOCK *TechPtr; ///< point to technology block. - struct _MEM_FEAT_BLOCK_NB *FeatPtr; ///< point to NB Specific feature block. + CONST struct _MEM_FEAT_BLOCK_NB *FeatPtr; ///< point to NB Specific feature block. struct _MEM_SHARED_DATA *SharedPtr; ///< Pointer to Memory scratchpad area SPD_DEF_STRUCT *AllNodeSPDPtr; ///< Point to SPD data for the system. DIE_STRUCT *AllNodeMCTPtr; ///< point to all Node's MCT structs @@ -1384,6 +1384,3 @@ MemNBfAfExcludeDimmClientNb ( ); #endif /* _MN_H_ */ - - - -- cgit v1.2.3