From d91ddc8d3181b8ab23726c8e744093f39473c202 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 30 Jul 2015 11:17:40 -0700 Subject: vendorcode/amd: 64bit fixes Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/11081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/vendorcode/amd/agesa/f16kb/Include/Ids.h | 2 +- .../amd/agesa/f16kb/Include/OptionIdsInstall.h | 24 +++++------ .../amd/agesa/f16kb/Include/gcc-intrin.h | 46 +++++++++++----------- .../amd/agesa/f16kb/Legacy/Proc/Dispatcher.c | 10 ++--- .../amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c | 2 +- .../amd/agesa/f16kb/Legacy/Proc/hobTransfer.c | 6 +-- src/vendorcode/amd/agesa/f16kb/Makefile.inc | 3 ++ .../f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c | 2 +- src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c | 4 +- .../amd/agesa/f16kb/Proc/CPU/cpuPostInit.c | 2 +- .../amd/agesa/f16kb/Proc/CPU/heapManager.c | 14 +++---- .../amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c | 2 +- .../amd/agesa/f16kb/Proc/GNB/Common/Gnb.h | 2 +- .../Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c | 6 +-- .../amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c | 12 +++--- 15 files changed, 70 insertions(+), 67 deletions(-) (limited to 'src/vendorcode/amd/agesa/f16kb') diff --git a/src/vendorcode/amd/agesa/f16kb/Include/Ids.h b/src/vendorcode/amd/agesa/f16kb/Include/Ids.h index 69bb6da0ff..53477cb866 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/Ids.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/Ids.h @@ -888,7 +888,7 @@ typedef enum { //vv- for debug reference only /// Function entry for HDT script to call typedef struct _SCRIPT_FUNCTION { - UINT32 FuncAddr; ///< Function address in ROM + UINTN FuncAddr; ///< Function address in ROM CHAR8 FuncName[40]; ///< Function name } SCRIPT_FUNCTION; diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h index b5a566f522..fe875004a2 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h @@ -74,29 +74,29 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE #if (AGESA_ENTRY_INIT_POST == TRUE) #include CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINT32) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, - { (UINT32) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, - { (UINT32) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} + { (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, + { (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, + { (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} }; #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE) #include CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"}, - { (UINT32) (UINT64) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"}, - { (UINT32) (UINT64) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"} + { (UINTN) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"}, + { (UINTN) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"}, + { (UINTN) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"} }; #else CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}, - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}, - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"} + { (UINTN) CommonReturnFalse, "DefRet()"}, + { (UINTN) CommonReturnFalse, "DefRet()"}, + { (UINTN) CommonReturnFalse, "DefRet()"} }; #endif #else CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINT32) CommonReturnFalse, "DefRet()"}, - { (UINT32) CommonReturnFalse, "DefRet()"}, - { (UINT32) CommonReturnFalse, "DefRet()"} + { (UINTN) CommonReturnFalse, "DefRet()"}, + { (UINTN) CommonReturnFalse, "DefRet()"}, + { (UINTN) CommonReturnFalse, "DefRet()"} }; #endif diff --git a/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h index 7d90f8bb5a..9ae45c3ee2 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h @@ -27,11 +27,11 @@ */ #if defined (__GNUC__) - +#include /* I/O intrin functions. */ -static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port) { - unsigned char value; + uint8_t value; __asm__ __volatile__ ( "in %1, %0" @@ -42,9 +42,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned return value; } -static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port) { - unsigned short value; + uint16_t value; __asm__ __volatile__ ( "in %1, %0" @@ -55,9 +55,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne return value; } -static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port) { - unsigned long value; + uint32_t value; __asm__ __volatile__ ( "in %1, %0" @@ -68,7 +68,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne } -static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data) +static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -77,7 +77,7 @@ static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short P ); } -static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data) +static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -86,7 +86,7 @@ static __inline__ __attribute__((always_inline)) void __outword(unsigned short P ); } -static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data) +static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -95,7 +95,7 @@ static __inline__ __attribute__((always_inline)) void __outdword(unsigned short ); } -static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insb" @@ -104,7 +104,7 @@ static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned sh ); } -static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insw" @@ -113,7 +113,7 @@ static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned sh ); } -static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insl" @@ -122,7 +122,7 @@ static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsb" @@ -131,7 +131,7 @@ static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsw" @@ -140,7 +140,7 @@ static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsl" @@ -525,7 +525,7 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source) } static __inline__ __attribute__((always_inline)) void -__writefsbyte(const unsigned long Offset, const unsigned char Data) +__writefsbyte(const unsigned long Offset, const uint8_t Data) { __asm__ ("movb %[Data], %%fs:%a[Offset]" : @@ -533,7 +533,7 @@ __writefsbyte(const unsigned long Offset, const unsigned char Data) } static __inline__ __attribute__((always_inline)) void -__writefsword(const unsigned long Offset, const unsigned short Data) +__writefsword(const unsigned long Offset, const uint16_t Data) { __asm__ ("movw %[Data], %%fs:%a[Offset]" : @@ -541,14 +541,14 @@ __writefsword(const unsigned long Offset, const unsigned short Data) } static __inline__ __attribute__((always_inline)) void -__writefsdword(const unsigned long Offset, const unsigned long Data) +__writefsdword(const unsigned long Offset, const uint32_t Data) { __asm__ ("movl %[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) unsigned char +static __inline__ __attribute__((always_inline)) uint8_t __readfsbyte(const unsigned long Offset) { unsigned char value; @@ -558,7 +558,7 @@ __readfsbyte(const unsigned long Offset) return value; } -static __inline__ __attribute__((always_inline)) unsigned short +static __inline__ __attribute__((always_inline)) uint16_t __readfsword(const unsigned long Offset) { unsigned short value; @@ -568,11 +568,11 @@ __readfsword(const unsigned long Offset) return value; } -static __inline__ __attribute__((always_inline)) unsigned long +static __inline__ __attribute__((always_inline)) uint32_t __readfsdword(unsigned long Offset) { unsigned long value; - __asm__ ("movl %%fs:%a[Offset], %[value]" + __asm__ ("mov %%fs:%a[Offset], %[value]" : [value] "=r" (value) : [Offset] "ir" (Offset)); return value; diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c index 782a52376a..f41deda1d0 100644 --- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c +++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c @@ -82,8 +82,8 @@ AmdAgesaDispatcher ( IMAGE_ENTRY ImageEntry; MODULE_ENTRY ModuleEntry; DISPATCH_TABLE *Entry; - UINT32 ImageStart; - UINT32 ImageEnd; + UINTN ImageStart; + UINTN ImageEnd; CONST AMD_IMAGE_HEADER* AltImagePtr; Status = AGESA_UNSUPPORTED; @@ -104,7 +104,7 @@ AmdAgesaDispatcher ( // 2. Try next dispatcher if possible, and we have not already got status back if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) { - ModuleEntry = (MODULE_ENTRY) (UINT32) mCpuModuleID.NextBlock->ModuleDispatcher; + ModuleEntry = (MODULE_ENTRY) mCpuModuleID.NextBlock->ModuleDispatcher; if (ModuleEntry != NULL) { Status = (*ModuleEntry) (ConfigPtr); } @@ -116,10 +116,10 @@ AmdAgesaDispatcher ( ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr; ImageEnd = ImageStart + 4; // Locate/test image base that matches this component - AltImagePtr = LibAmdLocateImage ((VOID *) (UINT32)ImageStart, (VOID *) (UINT32)ImageEnd, 4096, (CHAR8 *) AGESA_ID); + AltImagePtr = LibAmdLocateImage ((VOID *)ImageStart, (VOID *)ImageEnd, 4096, (CHAR8 *) AGESA_ID); if (AltImagePtr != NULL) { //Invoke alternative Image - ImageEntry = (IMAGE_ENTRY) ((UINT32) AltImagePtr + AltImagePtr->EntryPointAddress); + ImageEntry = (IMAGE_ENTRY) ((UINTN) AltImagePtr + AltImagePtr->EntryPointAddress); Status = (*ImageEntry) (ConfigPtr); } } diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c index 990c0a7894..c00619f06e 100644 --- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c +++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c @@ -436,7 +436,7 @@ AgesaFchOemCallout ( ) { AGESA_STATUS Status; - Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINT32)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader); + Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINTN)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader); return Status; } diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c index 7f03e13e7e..d282bdb48a 100644 --- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c @@ -212,7 +212,7 @@ CopyHeapToTempRamAtPost ( TotalSize = sizeof (HEAP_MANAGER); SizeOfNodeData = 0; AlignTo16ByteInTempMem = 0; - BaseAddressInCache = (UINT8 *)(UINT32) StdHeader->HeapBasePtr; + BaseAddressInCache = (UINT8 *)(UINTN) StdHeader->HeapBasePtr; HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache; HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset; HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); @@ -315,8 +315,8 @@ CopyHeapToMainRamAtPost ( TotalSize = sizeof (HEAP_MANAGER); SizeOfNodeData = 0; AlignTo16ByteInMainMem = 0; - BaseAddressInTempMem = (UINT8 *)(UINT32) StdHeader->HeapBasePtr; - HeapManagerInTempMem = (HEAP_MANAGER *)(UINT32) StdHeader->HeapBasePtr; + BaseAddressInTempMem = (UINT8 *)(UINTN) StdHeader->HeapBasePtr; + HeapManagerInTempMem = (HEAP_MANAGER *)(UINTN) StdHeader->HeapBasePtr; HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset; HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset); diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 5ce7aee583..e2338026a4 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -79,8 +79,11 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/RDWR2DTRAINING AGESA_INC += -I$(src)/southbridge/amd/agesa/hudson CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing +CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing + export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c index 6494c69407..60b1bddf36 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c @@ -261,5 +261,5 @@ GetGlobalCpuFeatureListAddress ( AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR; - *Address = (UINT64 *)(UINT32)(AddressValue); + *Address = (UINT64 *)(UINTN)(AddressValue); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c index 7feb3faee2..4b6128e245 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c @@ -215,7 +215,7 @@ SaveDeviceContext ( UINT64 EndAddress; VOID *OrMask; - StartAddress = (UINT64)(UINT32) DeviceList; + StartAddress = (UINTN) DeviceList; Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; @@ -279,7 +279,7 @@ SaveDeviceContext ( break; } } - EndAddress = (UINT64)(UINT32) OrMask; + EndAddress = (UINTN) OrMask; *ActualBufferSize = (UINT32) (EndAddress - StartAddress); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c index 605e0c4325..f1217a32c8 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c @@ -202,7 +202,7 @@ GetPstateGatherDataAddressAtPost ( AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR; - *Ptr = (UINT64 *)(UINT32)(AddressValue); + *Ptr = (UINT64 *)(UINTN)(AddressValue); return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c index 42a6afa10f..24ee886c98 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c @@ -158,7 +158,7 @@ HeapManagerInit ( GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); - HeapBufferPtr = (UINT8 *)(UINT32) StdHeader->HeapBasePtr; + HeapBufferPtr = (UINT8 *)(UINTN) StdHeader->HeapBasePtr; // Check whether the heap manager is already initialized LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader); @@ -328,14 +328,14 @@ HeapAllocateBuffer ( // Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; + StdHeader->HeapBasePtr = (UINTN)BaseAddress; } // Allocate @@ -473,14 +473,14 @@ HeapDeallocateBuffer ( // Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; + StdHeader->HeapBasePtr = (UINTN)BaseAddress; } OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; @@ -602,14 +602,14 @@ HeapLocateBuffer ( // Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; + StdHeader->HeapBasePtr = (UINTN)BaseAddress; } OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset; CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c index 5b30e55e20..093ab970b3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c @@ -119,7 +119,7 @@ AmdS3LateRestore ( ASSERT (S3LateParams != NULL); BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage; - S3LateParams->StdHeader.HeapBasePtr = (UINT32) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset]; + S3LateParams->StdHeader.HeapBasePtr = (UINTN) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset]; ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0); IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h index c01fd5ef98..8261a3d924 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h @@ -75,7 +75,7 @@ #define OFF 0 -#define PVOID UINT32 +#define PVOID UINTN #define STRING_TO_UINT32(a, b, c, d) ((UINT32) ((d << 24) | (c << 16) | (b << 8) | a)) diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c index 66cf992243..aee94676e9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c @@ -189,8 +189,8 @@ GfxSamuInit ( // Load boot control structure SamuBootControl = (SAMU_BOOT_CONTROL *)AlignedControlXBuffer; SamuBootControl->BootControl = 0x3; - SamuBootControl->KernelAddrLo = (UINT32) (AlignedPatchYBuffer); - SamuBootControl->KernelAddrHi = 0; //(UINT32) ((((UINT64) AlignedPatchYBuffer) >> 32) & 0xFF); + SamuBootControl->KernelAddrLo = (UINTN)AlignedPatchYBuffer; + SamuBootControl->KernelAddrHi = ((((UINT64)(UINTN)AlignedPatchYBuffer) >> 32) & 0xFF); if (SamuUseF1dPatch == TRUE) { SamuBootControl->TweakSelect = 0xBB027E1F; SamuBootControl->KeySelect = 0x8E174F83; @@ -209,7 +209,7 @@ GfxSamuInit ( // Write (physical address of boot control structure)>>8 into SAM_SAB_INIT_TLB_CONFIG (Location X >> 8) GMMx22008 = 0x4; GnbRegisterWriteKB (GnbHandle, 0x12, 0x22008, &GMMx22008, 0, GnbLibGetHeader (Gfx)); - GMMx2200C = ((UINT32) ((UINT32) AlignedControlXBuffer)) >> 8; + GMMx2200C = ((UINTN) AlignedControlXBuffer) >> 8; GnbRegisterWriteKB (GnbHandle, 0x12, 0x2200C, &GMMx2200C, 0, GnbLibGetHeader (Gfx)); // Write 0x0 to SAM_RST_HOST_SOFT_RESET diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c index bde0514528..d4d2685750 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c @@ -252,14 +252,14 @@ AmdIdsHdtOutInit ( HdtoutHeader.DataIndex = 0; HdtoutHeader.PrintCtrl = HDTOUT_PRINTCTRL_ON; HdtoutHeader.NumBreakpointUnit = 0; - HdtoutHeader.FuncListAddr = (UINT32) IDS_FUNCLIST_ADDR; + HdtoutHeader.FuncListAddr = (UINTN)IDS_FUNCLIST_ADDR; HdtoutHeader.StatusStr[0] = 0; HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_ON; HdtoutHeader.EnableMask = 0; HdtoutHeader.ConsoleFilter = IDS_DEBUG_PRINT_MASK; // Trigger HDTOUT breakpoint to get inputs from script - IdsOutPort (HDTOUT_INIT, (UINT32) &HdtoutHeader, 0); + IdsOutPort (HDTOUT_INIT, (UINTN) &HdtoutHeader, 0); // Disable AP HDTOUT if set BspOnlyFlag if (HdtoutHeader.BspOnlyFlag == HDTOUT_BSP_ONLY) { if (!IsBsp (StdHeader, &IgnoreSts)) { @@ -299,7 +299,7 @@ AmdIdsHdtOutInit ( } while ((HdtoutHeader.BufferSize & 0x8000) == 0); // If the buffer have been successfully allocated? if ((HdtoutHeader.BufferSize & 0x8000) == 0) { - LibAmdWriteCpuReg (DR3_REG, (UINT32) AllocHeapParams.BufferPtr); + LibAmdWriteCpuReg (DR3_REG, (UINTN)AllocHeapParams.BufferPtr); LibAmdMemCopy (AllocHeapParams.BufferPtr, &HdtoutHeader, sizeof (HdtoutHeader) - 2, StdHeader); } else { /// Clear DR3_REG @@ -327,7 +327,7 @@ AmdIdsHdtOutBufferFlush ( if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, StdHeader)) { if ((HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) && (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON)) { - IdsOutPort (HDTOUT_PRINT, (UINT32) HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex); + IdsOutPort (HDTOUT_PRINT, (UINTN)HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex); HdtoutHeaderPtr->DataIndex = 0; } } @@ -355,10 +355,10 @@ AmdIdsHdtOutExitCoreTask ( if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, StdHeader)) { if ((HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) && (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON)) { - IdsOutPort (HDTOUT_PRINT, (UINT32) HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex); + IdsOutPort (HDTOUT_PRINT, (UINTN)HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex); } } - IdsOutPort (HDTOUT_EXIT, (UINT32) HdtoutHeaderPtr, 0); + IdsOutPort (HDTOUT_EXIT, (UINTN)HdtoutHeaderPtr, 0); AmdIdsHdtOutRegisterRestore (StdHeader); -- cgit v1.2.3