From acd13985b50adbdb3a5ea8178e59de20986da01b Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 13 Jul 2017 22:48:22 +0300 Subject: vendorcode/amd/agesa: Sync irrelevant differences MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After modifications: f12 and f14 are identical f10 is f14 with invd -> wbinvd modification added to HOOK_F10 f15 is f10 with invd -> wbinvd modification added to HOOK_F15 f15tn is f15 modified to use with TN / KV / KM Change-Id: I4006fe09c134e5b51f3ee3772d6d150321d27b57 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20577 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: Marshall Dawson --- src/vendorcode/amd/agesa/f16kb/gcccar.inc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/vendorcode/amd/agesa/f16kb') diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index 87e609087b..592ee6d00e 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -42,7 +42,12 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ + +#ifdef __x86_64__ +CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */ +#else CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ +#endif APIC_BASE_ADDRESS = 0x0000001B APIC_BSC = 8 /* Boot Strap Core */ @@ -1298,4 +1303,3 @@ ClearTheStack: # Stack base is in SS, stack pointer is xor %eax, %eax .endm - -- cgit v1.2.3