From 2e0d9447db22183e2d3393d84e221e8bb1613d45 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 25 Jan 2014 15:59:31 +0100 Subject: src/vendorcode/amd: correct spelling of MTRR Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/4806 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/vendorcode/amd/agesa/f16kb/Legacy') diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c index d282bdb48a..a52c721955 100644 --- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c @@ -141,7 +141,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -172,14 +172,14 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x40000; MsrData &= 0xFFFFFFFFFFF7FFFF; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region // Get family specific cache Info GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); -- cgit v1.2.3