From 7b6d412dbc4e5c11d3dd7890abf0edf279b3f504 Mon Sep 17 00:00:00 2001 From: WANG Siyuan Date: Wed, 31 Jul 2013 16:55:26 +0800 Subject: vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7 The platform initialization (PI) code v1.0.0.7 for Kabini has some enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH bug fix (RTC) and so on. Use the name Kabini instead of Kerala everywhere. Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0 as used in `AGESA_VERSION_STRING`. Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248 Signed-off-by: WANG Siyuan Signed-off-by: WANG Siyuan Reviewed-on: http://review.coreboot.org/3935 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith --- .../amd/agesa/f16kb/Include/KabiniFt3Install.h | 144 +++++++++++++++++++++ .../amd/agesa/f16kb/Include/KeralaInstall.h | 143 -------------------- .../agesa/f16kb/Include/OptionFamily16hInstall.h | 24 ++-- .../amd/agesa/f16kb/Include/OptionFchInstall.h | 10 ++ .../amd/agesa/f16kb/Include/OptionMemoryInstall.h | 48 ++++--- .../amd/agesa/f16kb/Include/PlatformInstall.h | 6 +- 6 files changed, 202 insertions(+), 173 deletions(-) create mode 100644 src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h delete mode 100644 src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h (limited to 'src/vendorcode/amd/agesa/f16kb/Include') diff --git a/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h b/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h new file mode 100644 index 0000000000..a28dd5e23e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h @@ -0,0 +1,144 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build options for a Kabini platform solution + * + * This file generates the defaults tables for the "Kabini" platform solution + * set of processors. The documented build options are imported from a user + * controlled file for processing. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 69377 $ @e \$Date: 2012-05-08 03:52:23 -0500 (Tue, 08 May 2012) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ + // This is the delivery package title, "KabiniPI " + // This string MUST be exactly 16 characters long +#define AGESA_PACKAGE_STRING {'K', 'a', 'b', 'i', 'n', 'i', 'P', 'I', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' '} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '0', '.', '0', '.', '7', ' ', ' ', ' ', ' '} + + +// The Kabini FT3 solution is defined to be family 0x16 models 0x00 - 0x0F in the FT3 sockets. +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE + +#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT + #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE + #undef INSTALL_FT3_SOCKET_SUPPORT + #define INSTALL_FT3_SOCKET_SUPPORT FALSE + #endif +#endif + + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000ul +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0ul +#define DFLT_HPET_BASE_ADDRESS 0xFED00000ul +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000ul +#define DFLT_AZALIA_SSID 0x780D1022ul +#define DFLT_SMBUS_SSID 0x780B1022ul +#define DFLT_IDE_SSID 0x780C1022ul +#define DFLT_SATA_AHCI_SSID 0x78011022ul +#define DFLT_SATA_IDE_SSID 0x78001022ul +#define DFLT_SATA_RAID5_SSID 0x78031022ul +#define DFLT_SATA_RAID_SSID 0x78021022ul +#define DFLT_EHCI_SSID 0x78081022ul +#define DFLT_OHCI_SSID 0x78071022ul +#define DFLT_LPC_SSID 0x780E1022ul +#define DFLT_SD_SSID 0x78061022ul +#define DFLT_XHCI_SSID 0x78121022ul +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +#define OPTION_MICROSERVER TRUE +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + diff --git a/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h deleted file mode 100644 index 6b16a6c37a..0000000000 --- a/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h +++ /dev/null @@ -1,143 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Kerala platform solution - * - * This file generates the defaults tables for the "Kerala" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 69377 $ @e \$Date: 2012-05-08 03:52:23 -0500 (Tue, 08 May 2012) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "KabiniPI " - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'K', 'a', 'b', 'i', 'n', 'i', 'P', 'I'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '1', '.', '0', ' ', ' ', ' ', ' '} - - -// The Kerala solution is defined to be family 0x16 models 0x00 - 0x0F in the FT3 sockets. -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000ul -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0ul -#define DFLT_HPET_BASE_ADDRESS 0xFED00000ul -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000ul -#define DFLT_AZALIA_SSID 0x780D1022ul -#define DFLT_SMBUS_SSID 0x780B1022ul -#define DFLT_IDE_SSID 0x780C1022ul -#define DFLT_SATA_AHCI_SSID 0x78011022ul -#define DFLT_SATA_IDE_SSID 0x78001022ul -#define DFLT_SATA_RAID5_SSID 0x78031022ul -#define DFLT_SATA_RAID_SSID 0x78021022ul -#define DFLT_EHCI_SSID 0x78081022ul -#define DFLT_OHCI_SSID 0x78071022ul -#define DFLT_LPC_SSID 0x780E1022ul -#define DFLT_SD_SSID 0x78061022ul -#define DFLT_XHCI_SSID 0x78121022ul -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h index 92dae540fa..ae9e3ad352 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h @@ -127,6 +127,7 @@ extern F_PERFORM_EARLY_INIT_ON_CORE F16SetBrandIdRegistersAtEarly; extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly; + extern F_PERFORM_EARLY_INIT_ON_CORE F16KbLoadMicrocodePatchAtEarly; CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitBeforeApLaunchOnCoreTable[] = { @@ -143,7 +144,7 @@ {SetRegistersFromTablesAfterApLaunch, PERFORM_EARLY_ANY_CONDITION}, {F16SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, #if OPTION_EARLY_SAMPLES == FALSE - {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {F16KbLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, #endif {NULL, 0} }; @@ -208,25 +209,24 @@ #endif #if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) - #define F16_KB_UCODE_002A - #define F16_KB_UCODE_0106 + #define F16_KB_UCODE_7000 + #define F16_KB_UCODE_7001 #if AGESA_ENTRY_INIT_EARLY == TRUE #if OPTION_EARLY_SAMPLES == TRUE + extern CONST UINT8 ROMDATA CpuF16KbId7000MicrocodePatch[]; + #undef F16_KB_UCODE_7000 + #define F16_KB_UCODE_7000 CpuF16KbId7000MicrocodePatch, #endif - extern CONST UINT8 ROMDATA arr1[]; - #undef F16_KB_UCODE_002A - #define F16_KB_UCODE_002A arr1, - - extern CONST UINT8 ROMDATA arr2[]; - #undef F16_KB_UCODE_0106 - #define F16_KB_UCODE_0106 arr2, + extern CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch[]; + #undef F16_KB_UCODE_7001 + #define F16_KB_UCODE_7001 CpuF16KbId7001MicrocodePatch, #endif CONST UINT8 ROMDATA *CpuF16KbMicroCodePatchArray[] = { - F16_KB_UCODE_0106 - F16_KB_UCODE_002A + F16_KB_UCODE_7001 + F16_KB_UCODE_7000 NULL }; diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h index 4c927af308..4725504159 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h @@ -241,6 +241,7 @@ #define FCH_NO_GPP_SUPPORT TRUE #define FCH_NO_PCIB_SUPPORT TRUE #define FCH_NO_PCIE_SUPPORT TRUE + #define BLDOPT_RTC_WORKAROUND TRUE #else #error FCH_SUPPORT: No chip type selected. #endif @@ -929,6 +930,7 @@ InstallFchInitLatePcie, InstallFchInitLatePcib, InstallFchInitLateSpi, + InstallFchInitMidUsbEhci, InstallFchInitLateUsb, InstallFchInitLateUsbEhci, InstallFchInitLateUsbOhci, @@ -1011,6 +1013,14 @@ #endif +#define DFLT_RTC_WORKAROUND FALSE +#ifdef BLDOPT_RTC_WORKAROUND + #undef CFG_FCH_RTC_WORKAROUND + #define CFG_FCH_RTC_WORKAROUND BLDOPT_RTC_WORKAROUND +#else + #undef CFG_FCH_RTC_WORKAROUND + #define CFG_FCH_RTC_WORKAROUND DFLT_RTC_WORKAROUND +#endif CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = { FP_FCH_INIT_RESET, diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h index 07becd2691..1aaa027303 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h @@ -1263,16 +1263,34 @@ BOOLEAN MemFS3DefConstructorRet ( #define PSC_TBL_KB_ODT_TRI_FT3 &KBSODdr3ODTTriEntFT3, extern PSC_TBL_ENTRY KBSODdr3CSTriEntFT3; #define PSC_TBL_KB_CS_TRI_FT3 &KBSODdr3CSTriEntFT3, + #undef PSC_TBL_KB_UDIMM3_S2D_FT3 + #ifndef extern_S2DTblEntUFT3 + #define extern_S2DTblEntUFT3 + extern PSC_TBL_ENTRY S2DTblEntUFT3; + #endif + #define PSC_TBL_KB_UDIMM3_S2D_FT3 &S2DTblEntUFT3, #endif #if OPTION_UDIMMS - extern PSC_TBL_ENTRY KBMaxFreqTblEntU; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ &KBMaxFreqTblEntU, - extern PSC_TBL_ENTRY KBDramTermTblEntU; - #define PSC_TBL_KB_UDIMM3_DRAM_TERM &KBDramTermTblEntU, - extern PSC_TBL_ENTRY KBSAOTblEntU3; - #define PSC_TBL_KB_UDIMM3_SAO &KBSAOTblEntU3, + #if (OPTION_MICROSERVER == TRUE) + extern PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntMicroSrvU6L, + #else + extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntU6L, + #endif + extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L &KBMaxFreqTblEntU4L, + #if OPTION_FT3_SOCKET_SUPPORT + extern PSC_TBL_ENTRY KBDramTermTblEntUFT3; + #define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 &KBDramTermTblEntUFT3, + extern PSC_TBL_ENTRY KBSAOTblEntU3FT3; + #define PSC_TBL_KB_UDIMM3_SAO_FT3 &KBSAOTblEntU3FT3, + #endif #undef PSC_TBL_KB_UDIMM3_S2D_FT3 - extern PSC_TBL_ENTRY S2DTblEntUFT3; + #ifndef extern_S2DTblEntUFT3 + #define extern_S2DTblEntUFT3 + extern PSC_TBL_ENTRY S2DTblEntUFT3; + #endif #define PSC_TBL_KB_UDIMM3_S2D_FT3 &S2DTblEntUFT3, #endif #if OPTION_SODIMMS @@ -1299,10 +1317,6 @@ BOOLEAN MemFS3DefConstructorRet ( #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L &KBMaxFreqTblEntSoDwnPlusSODIMM6L, extern PSC_TBL_ENTRY KBMaxFreqTblEntSoDwn; #define PSC_TBL_KB_SODWN_MAX_FREQ &KBMaxFreqTblEntSoDwn, - extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntU6L, - extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L &KBMaxFreqTblEntU4L, #undef PSC_TBL_KB_SODIMM3_S2D_FT3 #define PSC_TBL_KB_SODIMM3_S2D_FT3 #endif @@ -1334,8 +1348,8 @@ BOOLEAN MemFS3DefConstructorRet ( #ifndef PSC_TBL_KB_UDIMM3_MAX_FREQ_4L #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L #endif - #ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM - #define PSC_TBL_KB_UDIMM3_DRAM_TERM + #ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 + #define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 #endif #ifndef PSC_TBL_KB_SODIMM3_DRAM_TERM #define PSC_TBL_KB_SODIMM3_DRAM_TERM @@ -1355,8 +1369,8 @@ BOOLEAN MemFS3DefConstructorRet ( #ifndef PSC_TBL_KB_SODWN_SAO #define PSC_TBL_KB_SODWN_SAO #endif - #ifndef PSC_TBL_KB_UDIMM3_SAO - #define PSC_TBL_KB_UDIMM3_SAO + #ifndef PSC_TBL_KB_UDIMM3_SAO_FT3 + #define PSC_TBL_KB_UDIMM3_SAO_FT3 #endif #ifndef PSC_TBL_KB_CLK_DIS_FT3 #define PSC_TBL_KB_CLK_DIS_FT3 @@ -1384,7 +1398,7 @@ BOOLEAN MemFS3DefConstructorRet ( }; PSC_TBL_ENTRY* memPSCTblDramTermArrayKB[] = { - PSC_TBL_KB_UDIMM3_DRAM_TERM + PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 PSC_TBL_KB_SODIMM3_DRAM_TERM PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM PSC_TBL_KB_SODWN_DRAM_TERM @@ -1401,7 +1415,7 @@ BOOLEAN MemFS3DefConstructorRet ( PSC_TBL_KB_SODIMM3_SAO PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO PSC_TBL_KB_SODWN_SAO - PSC_TBL_KB_UDIMM3_SAO + PSC_TBL_KB_UDIMM3_SAO_FT3 PSC_TBL_END }; diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h index 136b0f4c85..1295888f99 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h @@ -360,6 +360,9 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { #define OPTION_MEM_RESTORE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE + #ifndef OPTION_MICROSERVER + #define OPTION_MICROSERVER FALSE + #endif #endif #endif @@ -1811,7 +1814,8 @@ FCH_PLATFORM_POLICY FchUserOptions = { CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl - CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl + CFG_FCH_GPIO_CONTROL_LIST, // *CfgFchGpioControl + CFG_FCH_RTC_WORKAROUND // CfgFchRtcWorkaround }; BUILD_OPT_CFG UserOptions = { -- cgit v1.2.3