From 8d3640d22610eeb9a21c803d75c698e681a1dc62 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 16 May 2022 12:27:36 +0200 Subject: vendorcode/amd/agesa/f15tn: Fix all improper use of .data AGESA has a lot of code in the .data section which is for initialized data, that in fact should be .rodata. This adds the 'CONST' keyword everywhere it is needed. TEST: See in the .elf file (e.g. using readelf) that there is nothing in .data section. Change-Id: I9593c24f764319f66a64715d91175f64edf10608 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/64386 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Stefan Reinauer --- src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h | 10 ++++---- src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c | 6 ++--- .../agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h | 3 +-- .../amd/agesa/f15tn/Proc/Common/AmdInitEarly.c | 2 +- .../amd/agesa/f15tn/Proc/Common/S3SaveState.c | 4 +-- .../amd/agesa/f15tn/Proc/Common/S3SaveState.h | 4 +-- .../amd/agesa/f15tn/Proc/Fch/Common/FchDef.h | 7 +++--- .../amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c | 4 +-- .../amd/agesa/f15tn/Proc/Fch/Common/PciLib.c | 4 +-- .../Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c | 3 +-- .../Fch/Interface/Family/Hudson2/ResetDefHudson2.c | 4 +-- .../amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c | 5 ++-- .../Spi/Family/Hudson2/Hudson2LpcResetService.c | 2 +- .../amd/agesa/f15tn/Proc/GNB/Common/Gnb.h | 4 +-- .../amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h | 4 +-- .../f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c | 7 +++--- .../f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h | 4 +-- .../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c | 2 +- .../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h | 2 +- .../Modules/GnbFamTranslation/GnbPcieTranslation.c | 29 +++++++++++----------- .../GNB/Modules/GnbFamTranslation/GnbTranslation.c | 4 +-- .../Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h | 2 +- .../Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h | 20 +++++++-------- .../Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c | 4 +-- .../Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h | 2 +- .../Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h | 4 +-- .../f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c | 6 ++--- .../Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c | 3 +-- .../Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c | 3 +-- .../Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c | 6 ++--- .../GnbPcieInitLibV1/PcieTopologyServices.c | 2 +- .../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c | 6 ++--- .../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h | 4 +-- .../GNB/Modules/GnbPcieTrainingV1/PcieTraining.c | 6 ++--- .../f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c | 2 +- .../amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c | 8 +++--- .../amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c | 4 +-- .../amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c | 16 ++++++------ src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c | 5 ++-- .../amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c | 7 +++--- src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h | 2 +- 41 files changed, 106 insertions(+), 120 deletions(-) (limited to 'src/vendorcode/amd/agesa/f15tn/Proc') diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h index 126c4cf3e6..1b820ac98c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h @@ -260,23 +260,23 @@ typedef struct { typedef struct { UINT16 Version; ///< Version of header UINT16 NumRegisters; ///< Number of registers in the list - PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers + CONST PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + CONST PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers } PCI_REGISTER_BLOCK_HEADER; /// S3 'conditional' PCI register list header. typedef struct { UINT16 Version; ///< Version of header UINT16 NumRegisters; ///< Number of registers in the list - CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers + CONST CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + CONST PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers } CPCI_REGISTER_BLOCK_HEADER; /// S3 MSR register list header. typedef struct { UINT16 Version; ///< Version of header UINT16 NumRegisters; ///< Number of registers in the list - MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + CONST MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers } MSR_REGISTER_BLOCK_HEADER; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c index 530931cebc..2bef0633fc 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c @@ -118,12 +118,12 @@ STATIC *GetNextRegisterTable ( IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN TABLE_CORE_SELECTOR Selector, - IN OUT REGISTER_TABLE ***RegisterTableHandle, + CONST IN OUT REGISTER_TABLE ***RegisterTableHandle, OUT UINTN *NumberOfEntries, IN AMD_CONFIG_PARAMS *StdHeader ) { - REGISTER_TABLE **NextTable; + CONST REGISTER_TABLE **NextTable; TABLE_ENTRY_FIELDS *Entries; ASSERT ((FamilySpecificServices != NULL) && (StdHeader != NULL)); @@ -814,7 +814,7 @@ SetRegistersFromTables ( TABLE_ENTRY_FIELDS *Entries; TABLE_CORE_SELECTOR Selector; TABLE_ENTRY_TYPE EntryType; - REGISTER_TABLE **TableHandle; + CONST REGISTER_TABLE **TableHandle; UINTN NumberOfEntries; UINTN CurrentEntryCount; TABLE_ENTRY_TYPE_DESCRIPTOR *TypeImplementer; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h index f7d3b86220..603853abef 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h @@ -851,7 +851,7 @@ struct _CPU_SPECIFIC_SERVICES { // See t PF_NEXT_LINK_HAS_HTFPY_FEATS NextLinkHasHtPhyFeats; ///< Method: Iterate over HT Links matching features, for HT PHY entries. PF_SET_HT_PHY_REGISTER SetHtPhyRegister; ///< Method: Set an Ht Phy register based on table entry. PF_GET_NEXT_HT_LINK_FEATURES GetNextHtLinkFeatures; ///< Method: Iterate over HT links, returning link features. - REGISTER_TABLE **RegisterTableList; ///< Public Data: The available register tables. + CONST REGISTER_TABLE **RegisterTableList; ///< Public Data: The available register tables. TABLE_ENTRY_TYPE_DESCRIPTOR *TableEntryTypeDescriptors; ///< Public Data: implemented register table entry types. PACKAGE_HTLINK_MAP PackageLinkMap; ///< Public Data: translate northbridge HT links to package level links, or NULL. CORE_PAIR_MAP *CorePairMap; ///< Public Data: translate compute unit core pairing, or NULL. @@ -1004,4 +1004,3 @@ GetEmptyArray ( ); #endif // _CPU_FAMILY_TRANSLATION_H_ - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c index 181b1fa2bf..a0a16baac7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c @@ -74,7 +74,7 @@ RDATA_GROUP (G1_PEICC) * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */ -EXECUTION_CACHE_REGION InitExeCacheMap[] = +CONST EXECUTION_CACHE_REGION InitExeCacheMap[] = { {0x00000000, 0x00000000}, {0x00000000, 0x00000000}, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c index 94f5e12a27..d800dd75f0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c @@ -243,7 +243,7 @@ S3SaveStateSaveWriteOp ( IN ACCESS_WIDTH Width, IN UINT64 Address, IN UINT32 Count, - IN VOID *Buffer + CONST IN VOID *Buffer ) { S3_SAVE_TABLE_HEADER *S3SaveTablePtr; @@ -616,7 +616,7 @@ S3SaveDebugOpcodeString ( VOID S3SaveDebugPrintHexArray ( IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *Array, + CONST IN VOID *Array, IN UINT32 Count, IN ACCESS_WIDTH Width ) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h index a2bdedb3e9..9b09d8701c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h @@ -192,7 +192,7 @@ S3ScriptGetS3SaveTable ( VOID S3SaveDebugPrintHexArray ( IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *Array, + CONST IN VOID *Array, IN UINT32 Count, IN ACCESS_WIDTH Width ); @@ -210,7 +210,7 @@ S3SaveStateSaveWriteOp ( IN ACCESS_WIDTH Width, IN UINT64 Address, IN UINT32 Count, - IN VOID *Buffer + CONST IN VOID *Buffer ); AGESA_STATUS diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h index 00283de4d9..7967b1dc4b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h @@ -52,12 +52,12 @@ VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader); VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader); VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); -VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); +VOID ProgramFchSciMapTbl (CONST IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); +VOID ProgramFchGpioTbl (CONST IN GPIO_CONTROL *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader); @@ -454,4 +454,3 @@ BOOLEAN IsLpcRom (OUT VOID); VOID SbSleepTrapControl (IN BOOLEAN SleepTrap); #endif - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c index 2960bde389..81a9cc32d8 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c @@ -137,7 +137,7 @@ ProgramFchAcpiMmioTbl ( */ VOID ProgramFchSciMapTbl ( - IN SCI_MAP_CONTROL *pSciMapTbl, + CONST IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock ) { @@ -175,7 +175,7 @@ ProgramFchSciMapTbl ( */ VOID ProgramFchGpioTbl ( - IN GPIO_CONTROL *pGpioTbl, + CONST IN GPIO_CONTROL *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock ) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c index 6d286e8e02..c479a5c6a1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c @@ -63,7 +63,7 @@ VOID WritePci ( IN UINT32 Address, IN UINT8 OpFlag, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ) { @@ -90,5 +90,3 @@ RwPci ( rMask = ~Mask; LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader); } - - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c index 33adf862db..c5ad31ab61 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c @@ -55,7 +55,7 @@ * * */ -ACPI_REG_WRITE FchInitResetAcpiMmioTable[] = +CONST ACPI_REG_WRITE FchInitResetAcpiMmioTable[] = { {00, 00, 0xB0, 0xAC}, /// Signature {MISC_BASE >> 8, FCH_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12] @@ -138,4 +138,3 @@ ProgramFchHwAcpiResetP ( LocalCfgPtr->SataClkMode = 0x0a; } } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c index ba267c3b53..9f299a8ff4 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c @@ -75,7 +75,7 @@ CONST FCH_RESET_INTERFACE ROMDATA FchResetInterfaceDefault = { * InitReset Phase Data Block Default (Failsafe) *---------------------------------------------------------------- */ -FCH_RESET_DATA_BLOCK InitResetCfgDefault = { +CONST FCH_RESET_DATA_BLOCK InitResetCfgDefault = { NULL, // StdHeader {0}, // FchReset @@ -154,5 +154,3 @@ FCH_RESET_DATA_BLOCK InitResetCfgDefault = { }, NULL // OemResetProgrammingTablePtr }; - - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c index bdb214df42..b78dd40214 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c @@ -51,7 +51,7 @@ * * */ -REG8_MASK FchInitResetPcibPciTable[] = +CONST REG8_MASK FchInitResetPcibPciTable[] = { // // P2P Bridge (Bus 0, Dev 20, Func 4) @@ -98,7 +98,7 @@ FchInitResetPcib ( * * */ -REG8_MASK FchInitResetPcibPort80EnableTable[] = +CONST REG8_MASK FchInitResetPcibPort80EnableTable[] = { // // P2P Bridge (Bus 0, Dev 20, Func 4) @@ -133,4 +133,3 @@ FchInitResetPcibPort80Enable ( StdHeader ); } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c index 107e181394..e5358663e3 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c @@ -54,7 +54,7 @@ * * */ -REG8_MASK FchInitHudson2ResetLpcPciTable[] = +CONST REG8_MASK FchInitHudson2ResetLpcPciTable[] = { // // LPC Device (Bus 0, Dev 20, Func 3) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h index b93e164ac4..ea9e922089 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h @@ -148,8 +148,8 @@ typedef enum { typedef struct _GNB_SERVICE { GNB_SERVICE_ID ServiceId; ///< Service ID UINT64 Family; ///< CPU family - VOID *ServiceProtocol; ///< Service protocol - struct _GNB_SERVICE *NextService; ///< Pointer to next service + CONST VOID *ServiceProtocol; ///< Service protocol + CONST struct _GNB_SERVICE *NextService; ///< Pointer to next service } GNB_SERVICE; #define GNB_STRINGIZE(x) #x diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h index e8194f8202..357484ddbf 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h @@ -191,7 +191,7 @@ typedef struct { /// Table Register Entry typedef struct { - PCIE_PORT_REGISTER_ENTRY *Table; ///< Table + CONST PCIE_PORT_REGISTER_ENTRY *Table; ///< Table UINT32 Length; ///< Length } PCIE_PORT_REGISTER_TABLE_HEADER; @@ -204,7 +204,7 @@ typedef struct { /// Table Register Entry typedef struct { - PCIE_HOST_REGISTER_ENTRY *Table; ///< Table + CONST PCIE_HOST_REGISTER_ENTRY *Table; ///< Table UINT32 Length; ///< Length } PCIE_HOST_REGISTER_TABLE_HEADER; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c index 69137a0cbb..5ea3444cbb 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c @@ -151,7 +151,7 @@ GnbLibPciIndirectWrite ( IN UINT32 Address, IN UINT32 IndirectAddress, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN VOID *Config ) { @@ -501,11 +501,11 @@ AGESA_STATUS GnbLibLocateService ( IN GNB_SERVICE_ID ServiceId, IN UINT8 SocketId, - IN VOID **ServiceProtocol, + CONST IN VOID **ServiceProtocol, IN AMD_CONFIG_PARAMS *StdHeader ) { - GNB_SERVICE *SeviceEntry; + CONST GNB_SERVICE *SeviceEntry; CPU_LOGICAL_ID LogicalId; SeviceEntry = ServiceTable; GetLogicalIdOfSocket (SocketId, &LogicalId, StdHeader); @@ -518,4 +518,3 @@ GnbLibLocateService ( } return AGESA_UNSUPPORTED; } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h index 04a1b5c464..6a98ee3184 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h @@ -62,7 +62,7 @@ GnbLibPciIndirectWrite ( IN UINT32 Address, IN UINT32 IndirectAddress, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN VOID *Config ); @@ -159,7 +159,7 @@ AGESA_STATUS GnbLibLocateService ( IN GNB_SERVICE_ID ServiceId, IN UINT8 SocketId, - IN VOID **ServiceProtocol, + CONST IN VOID **ServiceProtocol, IN AMD_CONFIG_PARAMS *StdHeader ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c index e8467d3680..c99baee6a1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c @@ -86,7 +86,7 @@ VOID GnbLibPciWrite ( IN UINT32 Address, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h index 7fc88cf374..7915d97b4d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h @@ -49,7 +49,7 @@ VOID GnbLibPciWrite ( IN UINT32 Address, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c index c9713f5852..356b7b1f76 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c @@ -99,7 +99,7 @@ PcieFmConfigureEnginesLaneAllocation ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); - Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId); @@ -135,7 +135,7 @@ PcieFmGetCoreConfigurationValue ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); - Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieInitService->PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, ConfigurationValue); @@ -170,7 +170,7 @@ PcieFmCheckPortPciDeviceMapping ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine); @@ -203,7 +203,7 @@ PcieFmDebugGetCoreConfigurationString ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieDebugService->PcieFmDebugGetCoreConfigurationString (Wrapper, ConfigurationValue); @@ -233,7 +233,7 @@ PcieFmDebugGetWrapperNameString ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieDebugService->PcieFmDebugGetWrapperNameString (Wrapper); @@ -264,7 +264,7 @@ PcieFmDebugGetHostRegAddressSpaceString ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Silicon->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieDebugService->PcieFmDebugGetHostRegAddressSpaceString (Silicon, AddressFrame); @@ -299,7 +299,7 @@ PcieFmCheckPortPcieLaneCanBeMuxed ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmCheckPortPcieLaneCanBeMuxed (PortDescriptor, Engine); @@ -330,7 +330,7 @@ PcieFmMapPortPciAddress ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmMapPortPciAddress (Engine); @@ -358,7 +358,7 @@ PcieFmGetComplexDataLength ( { AGESA_STATUS Status; PCIe_FAM_CONFIG_SERVICES *PcieConfigService; - Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmGetComplexDataLength (SocketId, Length, StdHeader); @@ -388,7 +388,7 @@ PcieFmBuildComplexConfiguration ( { AGESA_STATUS Status; PCIe_FAM_CONFIG_SERVICES *PcieConfigService; - Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); @@ -419,7 +419,7 @@ PcieFmGetLinkSpeedCap ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieInitService->PcieFmGetLinkSpeedCap (Flags, Engine); @@ -449,7 +449,7 @@ PcieFmGetNativePhyLaneBitmap ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieInitService->PcieFmGetNativePhyLaneBitmap (PhyLaneBitmap, Engine); @@ -479,7 +479,7 @@ PcieFmSetLinkSpeedCap ( PCIe_FAM_INIT_SERVICES *PcieInitService; Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); - Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { PcieInitService->PcieFmSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); @@ -505,11 +505,10 @@ PcieFmGetSbConfigInfo ( { AGESA_STATUS Status; PCIe_FAM_CONFIG_SERVICES *PcieConfigService; - Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmGetSbConfigInfo (SocketId, SbPort, StdHeader); } return Status; } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c index 8097e6413e..79de6df3fa 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c @@ -91,7 +91,7 @@ GnbFmCheckIommuPresent ( { AGESA_STATUS Status; GNB_FAM_IOMMU_SERVICES *GnbIommuConfigService; - Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader); + Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbIommuConfigService, StdHeader); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return GnbIommuConfigService->GnbFmCheckIommuPresent (GnbHandle, StdHeader); @@ -121,7 +121,7 @@ GnbFmCreateIvrsEntry ( { AGESA_STATUS Status; GNB_FAM_IOMMU_SERVICES *GnbIommuConfigService; - Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader); + Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbIommuConfigService, StdHeader); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return GnbIommuConfigService->GnbFmCreateIvrsEntry (GnbHandle, Type, Ivrs, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h index 93381e3608..bb029a348f 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h @@ -45,7 +45,7 @@ #ifndef _GNBCACWEIGHTSTABLETN_H_ #define _GNBCACWEIGHTSTABLETN_H_ -UINT32 CacWeightsTN[] = { +CONST UINT32 CacWeightsTN[] = { 0xD65, 0x289A, 0x289A, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h index 1be9d7cafc..dc7cb1556c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h @@ -66,7 +66,7 @@ extern F_PCIEFMMAPPORTPCIADDRESS PcieMapPortPciAddressTN; extern F_PCIEFMCHECKPORTPCIELANECANBEMUXED PcieCheckPortPcieLaneCanBeMuxedTN; extern F_PCIEFMGETSBCONFIGINFO PcieGetSbConfigInfoTN; - PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolTN = { +CONST PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolTN = { PcieGetComplexDataLengthTN, PcieBuildComplexConfigurationTN, PcieConfigureEnginesLaneAllocationTN, @@ -76,7 +76,7 @@ PcieGetSbConfigInfoTN }; - GNB_SERVICE GnbPcieCongigServicesTN = { + CONST GNB_SERVICE GnbPcieCongigServicesTN = { GnbPcieFamConfigService, AMD_FAMILY_TN, &GnbPcieConfigProtocolTN, @@ -92,14 +92,14 @@ extern F_PCIEFMGETNATIVEPHYLANEBITMAP PcieGetNativePhyLaneBitmapTN; extern F_PCIEFMSETLINKSPEEDCAP PcieSetLinkSpeedCapV4; - PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolTN = { + CONST PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolTN = { PcieGetCoreConfigurationValueTN, PcieGetLinkSpeedCapTN, PcieGetNativePhyLaneBitmapTN, PcieSetLinkSpeedCapV4 }; - GNB_SERVICE GnbPcieInitServicesTN = { + CONST GNB_SERVICE GnbPcieInitServicesTN = { GnbPcieFamInitService, AMD_FAMILY_TN, &GnbPcieInitProtocolTN, @@ -116,13 +116,13 @@ extern F_PCIEFMDEBUGGETWRAPPERNAMESTRING PcieDebugGetWrapperNameStringTN; extern F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING PcieDebugGetCoreConfigurationStringTN; - PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolTN = { + CONST PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolTN = { PcieDebugGetHostRegAddressSpaceStringTN, PcieDebugGetWrapperNameStringTN, PcieDebugGetCoreConfigurationStringTN }; - GNB_SERVICE GnbPcieDebugServicesTN = { + CONST GNB_SERVICE GnbPcieDebugServicesTN = { GnbPcieFamDebugService, AMD_FAMILY_TN, &GnbPcieDebugProtocolTN, @@ -138,12 +138,12 @@ extern F_GNB_REGISTER_ACCESS GnbRegisterReadServiceTN; extern F_GNB_REGISTER_ACCESS GnbRegisterWriteServiceTN; - GNB_REGISTER_SERVICE GnbRegiterAccessProtocol = { + CONST GNB_REGISTER_SERVICE GnbRegiterAccessProtocol = { GnbRegisterReadServiceTN, GnbRegisterWriteServiceTN }; - GNB_SERVICE GnbRegisterAccessServicesTN = { + CONST GNB_SERVICE GnbRegisterAccessServicesTN = { GnbRegisterAccessService, AMD_FAMILY_TN, &GnbRegiterAccessProtocol, @@ -155,12 +155,12 @@ extern F_GNBFMCREATEIVRSENTRY GnbCreateIvrsEntryTN; extern F_GNBFMCHECKIOMMUPRESENT GnbCheckIommuPresentTN; - GNB_FAM_IOMMU_SERVICES GnbIommuConfigProtocolTN = { + CONST GNB_FAM_IOMMU_SERVICES GnbIommuConfigProtocolTN = { GnbCheckIommuPresentTN, GnbCreateIvrsEntryTN }; - GNB_SERVICE GnbIommuConfigServicesTN = { + CONST GNB_SERVICE GnbIommuConfigServicesTN = { GnbIommuService, AMD_FAMILY_TN, &GnbIommuConfigProtocolTN, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c index f8e885cc48..fa6dafd48c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c @@ -242,7 +242,7 @@ GnbDctAdditionalDataWriteTN ( IN UINT8 DctCfgSel, IN UINT8 MemPsSel, IN UINT32 Flags, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ) { @@ -816,7 +816,7 @@ AGESA_STATUS GnbRegisterWriteTN ( IN UINT8 RegisterSpaceType, IN UINT32 Address, - IN VOID *Value, + CONST IN VOID *Value, IN UINT32 Flags, IN AMD_CONFIG_PARAMS *StdHeader ) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h index d28c614292..3d5497ea09 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h @@ -49,7 +49,7 @@ AGESA_STATUS GnbRegisterWriteTN ( IN UINT8 RegisterSpaceType, IN UINT32 Address, - IN VOID *Value, + CONST IN VOID *Value, IN UINT32 Flags, IN AMD_CONFIG_PARAMS *StdHeader ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h index 1ce5fa2bc9..39581d6a7b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h @@ -45,7 +45,7 @@ #ifndef _GNBSMUFIRMWARETN_H_ #define _GNBSMUFIRMWARETN_H_ -UINT32 FirmwareTNHeader [] = { +CONST UINT32 FirmwareTNHeader [] = { 0x554D535F, 0x554D535F, 0x0000F030, @@ -60,7 +60,7 @@ UINT32 FirmwareTNHeader [] = { 0x00000000, }; -UINT32 FirmwareTN[] = { +CONST UINT32 FirmwareTN[] = { 0x000a000e, 0x00000040, 0x00003bc0, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c index 6b855ae984..8196b79f8a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c @@ -82,7 +82,7 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ -GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN [] = { +CONST GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN [] = { GNB_ENTRY_RMW ( D0F0x98_x07_TYPE, D0F0x98_x07_ADDRESS, @@ -99,7 +99,7 @@ GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN [] = { GNB_ENTRY_TERMINATE }; -GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN [] = { +CONST GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN [] = { // Config GFX to legacy mode initially GNB_ENTRY_RMW ( D0F0x64_x1D_TYPE, @@ -284,7 +284,7 @@ GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN [] = { GNB_ENTRY_TERMINATE }; -GNB_TABLE ROMDATA GnbEarlyInitTableTN [] = { +CONST GNB_TABLE ROMDATA GnbEarlyInitTableTN [] = { GNB_ENTRY_WR ( D0F0x04_TYPE, D0F0x04_ADDRESS, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c index 60ea236c61..705afda46e 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c @@ -73,7 +73,7 @@ */ -TN_COMPLEX_CONFIG ComplexDataTN = { +CONST TN_COMPLEX_CONFIG ComplexDataTN = { //Silicon { { @@ -461,4 +461,3 @@ TN_COMPLEX_CONFIG ComplexDataTN = { {0, 0, 0, 0, 0, 0} } }; - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c index da962d52e3..3f81825311 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c @@ -946,7 +946,7 @@ PcieGetNativePhyLaneBitmapTN ( return PhyLaneBitmap; } -STATIC PCIe_PORT_DESCRIPTOR DefaultSbPortTN = { +STATIC CONST PCIe_PORT_DESCRIPTOR DefaultSbPortTN = { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0) @@ -972,4 +972,3 @@ PcieGetSbConfigInfoTN ( LibAmdMemCopy (SbPort, &DefaultSbPortTN, sizeof (DefaultSbPortTN), StdHeader); return AGESA_SUCCESS; } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c index a58e918a22..832faba250 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c @@ -75,7 +75,7 @@ *---------------------------------------------------------------------------------------- */ -STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { +STATIC CONST PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { { WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS), D0F0xE4_WRAP_8016_CalibAckLatency_MASK, @@ -113,7 +113,7 @@ CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN = { ARRAY_SIZE(PcieInitEarlyTable) }; -STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { +STATIC CONST PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { { D0F0xE4_CORE_0020_ADDRESS, D0F0xE4_CORE_0020_CiRcOrderingDis_MASK | @@ -164,7 +164,7 @@ CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN = { }; -STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { +STATIC CONST PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { { DxF0xE4_x02_ADDRESS, DxF0xE4_x02_RegsLcAllowTxL1Control_MASK, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index ddcbccbe55..1a09d58f35 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -154,7 +154,7 @@ PcieTopologyPrepareForReconfig ( } -UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; +CONST UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; /*----------------------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c index 4e3f2847c1..fde8852559 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c @@ -148,7 +148,7 @@ BOOLEAN PcieUtilSearchArray ( IN UINT8 *Buf1, IN UINTN Buf1Length, - IN UINT8 *Buf2, + CONST IN UINT8 *Buf2, IN UINTN Buf2Length ) { @@ -156,7 +156,7 @@ PcieUtilSearchArray ( CurrentBuf1Ptr = Buf1; while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { UINT8 *SourceBufPtr; - UINT8 *PatternBufPtr; + CONST UINT8 *PatternBufPtr; UINTN PatternBufLength; SourceBufPtr = CurrentBuf1Ptr; PatternBufPtr = Buf2; @@ -522,7 +522,7 @@ PcieUtilGetWrapperLaneBitMap ( VOID PciePortProgramRegisterTable ( - IN PCIE_PORT_REGISTER_ENTRY *Table, + CONST IN PCIE_PORT_REGISTER_ENTRY *Table, IN UINTN Length, IN PCIe_ENGINE_CONFIG *Engine, IN BOOLEAN S3Save, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h index 5ed4fc46cc..e9669e87d0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h @@ -65,7 +65,7 @@ BOOLEAN PcieUtilSearchArray ( IN UINT8 *Buf1, IN UINTN Buf1Length, - IN UINT8 *Buf2, + CONST IN UINT8 *Buf2, IN UINTN Buf2Length ); @@ -109,7 +109,7 @@ PcieUtilGetWrapperLaneBitMap ( VOID PciePortProgramRegisterTable ( - IN PCIE_PORT_REGISTER_ENTRY *Table, + CONST IN PCIE_PORT_REGISTER_ENTRY *Table, IN UINTN Length, IN PCIe_ENGINE_CONFIG *Engine, IN BOOLEAN S3Save, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c index f8a35cc58d..a40dbade52 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c @@ -354,9 +354,9 @@ PcieTrainingDetectPresence ( } } -UINT8 FailPattern1 [] = {0x2a, 0x6}; -UINT8 FailPattern2 [] = {0x2a, 0x9}; -UINT8 FailPattern3 [] = {0x2a, 0xb}; +CONST UINT8 FailPattern1 [] = {0x2a, 0x6}; +CONST UINT8 FailPattern2 [] = {0x2a, 0x9}; +CONST UINT8 FailPattern3 [] = {0x2a, 0xb}; /*----------------------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c index f8faa3633f..ea572b981c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c @@ -125,7 +125,7 @@ GnbProcessTable ( WriteAccFlags |= GNB_REG_ACC_FLAG_S3SAVE; } - Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (VOID **)&GnbRegisterAccessProtocol, StdHeader); + Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbRegisterAccessProtocol, StdHeader); ASSERT (Status == AGESA_SUCCESS); while (*EntryPointer != GnbEntryTerminate) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c index 2449ff9c07..be184c9a4b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c @@ -384,7 +384,7 @@ MemFS3GetPciDeviceRegisterList ( { AGESA_STATUS RetVal; S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; + CONST VOID *RegisterHeader; LOCATE_HEAP_PTR LocHeap; AGESA_BUFFER_PARAMS LocBufferParams; LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; @@ -434,7 +434,7 @@ MemFS3GetCPciDeviceRegisterList ( { AGESA_STATUS RetVal; S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; + CONST VOID *RegisterHeader; LOCATE_HEAP_PTR LocHeap; AGESA_BUFFER_PARAMS LocBufferParams; @@ -484,7 +484,7 @@ MemFS3GetMsrDeviceRegisterList ( { AGESA_STATUS RetVal; S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; + CONST VOID *RegisterHeader; LOCATE_HEAP_PTR LocHeap; AGESA_BUFFER_PARAMS LocBufferParams; @@ -534,7 +534,7 @@ MemFS3GetCMsrDeviceRegisterList ( { AGESA_STATUS RetVal; S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; + CONST VOID *RegisterHeader; LOCATE_HEAP_PTR LocHeap; AGESA_BUFFER_PARAMS LocBufferParams; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c index 346489220e..b306933824 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c @@ -84,7 +84,7 @@ BOOLEAN STATIC MemMSetCSRNb ( IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, + CONST IN PCI_SPECIAL_CASE *SpecialCases, IN PCI_ADDR PciAddr, IN UINT32 Value ); @@ -532,7 +532,7 @@ BOOLEAN STATIC MemMSetCSRNb ( IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, + CONST IN PCI_SPECIAL_CASE *SpecialCases, IN PCI_ADDR PciAddr, IN UINT32 Value ) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c index c14ab4a8cc..8fe87d0280 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c @@ -96,7 +96,7 @@ AGESA_STATUS STATIC MemNS3GetDeviceRegLstTN ( IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader + CONST OUT VOID **RegisterHeader ); VOID @@ -189,7 +189,7 @@ MemS3ResumeConstructNBBlockTN ( * *---------------------------------------------------------------------------- */ -PCI_SPECIAL_CASE PciSpecialCaseFuncTN[] = { +CONST PCI_SPECIAL_CASE PciSpecialCaseFuncTN[] = { {MemNS3GetCSRTN, MemNS3SetCSRTN}, {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}, {MemNS3GetNBPStateDepRegUnb, MemNS3SetNBPStateDepRegUnb}, @@ -207,7 +207,7 @@ PCI_SPECIAL_CASE PciSpecialCaseFuncTN[] = { { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ForceNBP0Unb} }; -PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorTN[] = { +CONST PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorTN[] = { {{14,3, 1}, DO_NOT_CARE, 0, 0}, {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFF8E7}, {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF0703}, @@ -233,7 +233,7 @@ CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefTN = { PciSpecialCaseFuncTN }; -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorTN[] = { +CONST CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorTN[] = { // DCT 0 {{7, 0, 1}, DCT0, 0x40, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, {{7, 0, 1}, DCT0, 0x44, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, @@ -515,7 +515,7 @@ CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefTN = { PciSpecialCaseFuncTN }; -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorTN[] = { +CONST CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorTN[] = { // DCT0 {{12, 2, 1}, DCT1, BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, {{1, 2, 1}, DCT0, BFRx4thStgEn, 0, DCT0_MASK, ANY_DIMM_MASK}, @@ -802,7 +802,7 @@ CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefTN = { PciSpecialCaseFuncTN }; -MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorTN[] = { +CONST MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorTN[] = { {{0, 0, 0}, 0xC0010010, 0x00000000007F0000}, {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, @@ -816,7 +816,7 @@ CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefTN = { NULL }; -VOID *MemS3RegListTN[] = { +CONST VOID * CONST MemS3RegListTN[] = { (VOID *)&S3PciPreSelfRefTN, NULL, (VOID *)&S3CPciPreSelfRefTN, @@ -992,7 +992,7 @@ AGESA_STATUS STATIC MemNS3GetDeviceRegLstTN ( IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader + CONST OUT VOID **RegisterHeader ) { if (RegisterLstID >= (sizeof (MemS3RegListTN) / sizeof (VOID *))) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c index 2f6ef5db61..d195ce3b6b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c @@ -93,7 +93,7 @@ BOOLEAN STATIC MemPPSCGen ( IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables + CONST IN MEM_PSC_TABLE_BLOCK *EntryOfTables ); BOOLEAN @@ -551,7 +551,7 @@ BOOLEAN STATIC MemPPSCGen ( IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables + CONST IN MEM_PSC_TABLE_BLOCK *EntryOfTables ) { UINT8 i; @@ -1216,4 +1216,3 @@ MemPCheckTblDrvOverrideConfigSpeedLimit ( return FALSE; } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c index 46e591aa5a..1706b7ef36 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c @@ -101,7 +101,7 @@ RDATA_GROUP (G1_PEICC) * Sweep Table For Byte Training without insertion delay * */ -DQS_POS_SWEEP_TABLE SweepTableByte[] = +CONST DQS_POS_SWEEP_TABLE SweepTableByte[] = { // Begin End Inc/Dec Step EndResult Edge { 0x00, 0x1F, INC_DELAY, 4, 0xFFFF, LEFT_EDGE}, /// For Left Edge, start from 0 and Increment to 0x1F by 4 until all PASS @@ -113,7 +113,7 @@ DQS_POS_SWEEP_TABLE SweepTableByte[] = * Sweep Table For Byte Training with insertion delay * */ -DQS_POS_SWEEP_TABLE InsSweepTableByte[] = +CONST DQS_POS_SWEEP_TABLE InsSweepTableByte[] = { // Begin End Inc/Dec Step EndResult Edge { 0x00, -0x20, DEC_DELAY, -4, 0xFE00, LEFT_EDGE}, /// For Left Edge, start from 0 and Decrement to -0x20 by -4 until all FAIL @@ -400,7 +400,7 @@ MemTTrainDQSEdgeDetect ( { MEM_NB_BLOCK *NBPtr; DIE_STRUCT *MCTPtr; - DQS_POS_SWEEP_TABLE *SweepTablePtr; + CONST DQS_POS_SWEEP_TABLE *SweepTablePtr; UINT8 SweepTableSize; SWEEP_INFO SweepData; BOOLEAN Status; @@ -903,4 +903,3 @@ MemTDataEyeSave ( return TRUE; } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h index 657c8dfe41..08a07568fb 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h @@ -98,7 +98,7 @@ typedef struct _S3_MEM_NB_BLOCK { UINT16 (*MemS3GetRegLstPtr) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get register list pointer for both PCI and MSR register BOOLEAN (*MemS3Resume) (struct _S3_MEM_NB_BLOCK *S3NBPtr, UINT8 NodeID);///< Exit Self Refresh VOID (*MemS3RestoreScrub) (MEM_NB_BLOCK *NBPtr, UINT8 NodeID);///< Restore scrubber base - AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, VOID **RegisterHeader); ///< Get register list for a device + AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, CONST VOID **RegisterHeader); ///< Get register list for a device } S3_MEM_NB_BLOCK; /// Header for heap space to store the special case register. -- cgit v1.2.3