From 7d94cf93eec15dfb8eef9cd044fe39319d4ee9bc Mon Sep 17 00:00:00 2001 From: zbao Date: Mon, 2 Jul 2012 14:19:14 +0800 Subject: AGESA F15tn: AMD family15 AGESA code for Trinity AMD AGESA code for trinity. Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592 Signed-off-by: Zheng Bao Signed-off-by: zbao Reviewed-on: http://review.coreboot.org/1155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h | 83 + .../f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c | 548 + .../f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h | 193 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c | 157 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h | 92 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c | 186 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h | 96 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c | 149 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h | 93 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c | 152 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h | 100 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c | 430 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h | 186 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c | 183 + .../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h | 100 + .../Modules/GnbFamTranslation/GnbPcieTranslation.c | 542 + .../GNB/Modules/GnbFamTranslation/GnbTranslation.c | 157 + .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c | 160 + .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c | 259 + .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h | 98 + .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c | 140 + .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c | 163 + .../Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h | 78 + .../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c | 211 + .../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h | 83 + .../Modules/GnbGfxInitLibV1/GfxEnumConnectors.c | 636 + .../Modules/GnbGfxInitLibV1/GfxEnumConnectors.h | 91 + .../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 1013 ++ .../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h | 278 + .../GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c | 225 + .../GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h | 107 + .../Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c | 493 + .../Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c | 595 + .../Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h | 121 + .../Modules/GnbInitTN/GfxIntegratedInfoTableTN.c | 922 ++ .../f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c | 478 + .../f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h | 134 + .../Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c | 304 + .../Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c | 155 + .../f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c | 1096 ++ .../GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c | 353 + .../GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h | 87 + .../Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h | 175 + .../Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c | 888 ++ .../Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c | 197 + .../Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c | 1000 ++ .../Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h | 105 + .../f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h | 78 + .../Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h | 200 + .../Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c | 289 + .../Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c | 574 + .../Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c | 128 + .../Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c | 1334 ++ .../Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h | 101 + .../Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h | 14126 +++++++++++++++++++ .../f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c | 1121 ++ .../Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h | 242 + .../Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h | 1065 ++ .../Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c | 119 + .../Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl | 196 + .../Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c | 119 + .../Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c | 491 + .../Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h | 160 + .../Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c | 1002 ++ .../Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c | 810 ++ .../Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c | 122 + .../f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c | 639 + .../f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h | 110 + .../Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c | 283 + .../Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c | 498 + .../Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c | 383 + .../Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h | 81 + .../Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c | 258 + .../Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c | 361 + .../Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h | 81 + .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.c | 168 + .../f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c | 267 + .../f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h | 117 + .../Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c | 203 + .../GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c | 432 + .../GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h | 126 + .../GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c | 620 + .../GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h | 149 + .../Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c | 578 + .../Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h | 109 + .../GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl | 136 + .../GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl | 111 + .../GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl | 73 + .../GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl | 787 ++ .../GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl | 88 + .../GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl | 289 + .../GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl | 109 + .../GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl | 825 ++ .../f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c | 445 + .../f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h | 90 + .../Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c | 353 + .../Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h | 81 + .../Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c | 162 + .../Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h | 101 + .../Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h | 81 + .../GNB/Modules/GnbPcieConfig/PcieConfigData.c | 561 + .../GNB/Modules/GnbPcieConfig/PcieConfigData.h | 84 + .../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c | 827 ++ .../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h | 248 + .../GNB/Modules/GnbPcieConfig/PcieInputParser.c | 275 + .../GNB/Modules/GnbPcieConfig/PcieInputParser.h | 110 + .../GNB/Modules/GnbPcieConfig/PcieMapTopology.c | 672 + .../GNB/Modules/GnbPcieConfig/PcieMapTopology.h | 84 + .../Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h | 87 + .../Modules/GnbPcieInitLibV1/PcieAspmBlackList.c | 179 + .../Modules/GnbPcieInitLibV1/PcieAspmBlackList.h | 82 + .../Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c | 218 + .../Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h | 82 + .../GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c | 334 + .../GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h | 100 + .../GNB/Modules/GnbPcieInitLibV1/PciePifServices.c | 654 + .../GNB/Modules/GnbPcieInitLibV1/PciePifServices.h | 147 + .../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c | 257 + .../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h | 121 + .../Modules/GnbPcieInitLibV1/PciePortServices.c | 533 + .../Modules/GnbPcieInitLibV1/PciePortServices.h | 145 + .../GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c | 424 + .../GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h | 101 + .../GNB/Modules/GnbPcieInitLibV1/PcieService.esl | 87 + .../Modules/GnbPcieInitLibV1/PcieSiliconServices.c | 284 + .../Modules/GnbPcieInitLibV1/PcieSiliconServices.h | 99 + .../GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl | 244 + .../GNB/Modules/GnbPcieInitLibV1/PcieSmuVidReq.esl | 107 + .../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c | 122 + .../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h | 82 + .../GnbPcieInitLibV1/PcieTopologyServices.c | 804 ++ .../GnbPcieInitLibV1/PcieTopologyServices.h | 168 + .../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c | 688 + .../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h | 158 + .../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c | 324 + .../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h | 154 + .../Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h | 79 + .../Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c | 322 + .../Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.h | 81 + .../Modules/GnbPcieInitLibV4/PciePortServicesV4.c | 215 + .../Modules/GnbPcieInitLibV4/PciePortServicesV4.h | 91 + .../GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c | 328 + .../GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h | 86 + .../GNB/Modules/GnbPcieInitLibV4/PcieServiceV4.esl | 89 + .../Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl | 105 + .../Modules/GnbPcieInitLibV4/PcieSmuVidReqV4.esl | 124 + .../GnbPcieInitLibV4/PcieWrapperServicesV4.c | 277 + .../GnbPcieInitLibV4/PcieWrapperServicesV4.h | 104 + .../Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h | 78 + .../GNB/Modules/GnbPcieTrainingV1/PcieTraining.c | 907 ++ .../GNB/Modules/GnbPcieTrainingV1/PcieTraining.h | 90 + .../Modules/GnbPcieTrainingV1/PcieWorkarounds.c | 402 + .../Modules/GnbPcieTrainingV1/PcieWorkarounds.h | 82 + .../Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c | 178 + .../Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c | 146 + .../Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h | 82 + .../f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c | 159 + .../f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h | 105 + .../f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c | 169 + .../f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c | 155 + .../f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c | 384 + .../f15tn/Proc/GNB/Modules/GnbTable/GnbTable.h | 265 + 162 files changed, 60312 insertions(+) create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h create mode 100644 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src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.h (limited to 'src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules') diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h new file mode 100644 index 0000000000..82842b5d48 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h @@ -0,0 +1,83 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBCOMMONLIB_H_ +#define _GNBCOMMONLIB_H_ + +#include "GnbLib.h" +#include "GnbLibCpuAcc.h" +#include "GnbLibHeap.h" +#include "GnbLibIoAcc.h" +#include "GnbLibMemAcc.h" +#include "GnbLibPci.h" +#include "GnbLibPciAcc.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c new file mode 100644 index 0000000000..e79dfb7a60 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c @@ -0,0 +1,548 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "cpuServices.h" +#include "Gnb.h" +#include "GnbLib.h" +#include "GnbLibIoAcc.h" +#include "GnbLibPciAcc.h" +#include "GnbLibMemAcc.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_SERVICE *ServiceTable; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read GNB indirect registers + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] Width Width + * @param[out] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *Config + ) +{ + UINT32 IndexOffset; + IndexOffset = LibAmdAccessWidth (Width); + GnbLibPciWrite (Address, Width, &IndirectAddress, Config); + GnbLibPciRead (Address + IndexOffset, Width, Value, Config); +} +/*----------------------------------------------------------------------------------------*/ +/** + * Read GNB indirect registers field + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[out] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectReadField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + OUT UINT32 *Value, + IN VOID *Config + ) +{ + UINT32 Mask; + GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, Value, Config); + Mask = (1 << FieldWidth) - 1; + *Value = (*Value >> FieldOffset) & Mask; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write GNB indirect registers + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] Width Width + * @param[in] Value Pointer to value + * @param[in] Config Pointer to standard header + */ + +VOID +GnbLibPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *Config + ) +{ + UINT32 IndexOffset; + IndexOffset = LibAmdAccessWidth (Width); + GnbLibPciWrite (Address, Width, &IndirectAddress, Config); + GnbLibPciWrite (Address + IndexOffset, Width, Value, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write GNB indirect registers field + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[in] Value Pointer to value + * @param[in] S3Save Save for S3 (TRUE/FALSE) + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectWriteField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN VOID *Config + ) +{ + UINT32 Data; + UINT32 Mask; + GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, &Data, Config); + Mask = (1 << FieldWidth) - 1; + Data &= (~(Mask << FieldOffset)); + Data |= ((Value & Mask) << FieldOffset); + GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write GNB indirect registers field + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] Width Width + * @param[in] Mask And Mask + * @param[in] Value Or Value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectRMW ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibPciIndirectRead ( + Address, + IndirectAddress, + (Width >= AccessS3SaveWidth8) ? (Width - (AccessS3SaveWidth8 - AccessWidth8)) : Width, + &Data, + Config + ); + Data = (Data & Mask) | Value; + GnbLibPciIndirectWrite (Address, IndirectAddress, Width, &Data, Config); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write PCI registers + * + * + * + * @param[in] Address PCI address + * @param[in] Width Access width + * @param[in] Mask AND Mask + * @param[in] Value OR Value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciRMW ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibPciRead (Address, Width, &Data, Config); + Data = (Data & Mask) | Value; + GnbLibPciWrite (Address, Width, &Data, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write I/O registers + * + * + * + * @param[in] Address I/O Port + * @param[in] Width Access width + * @param[in] Mask AND Mask + * @param[in] Value OR Mask + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibIoRMW ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibIoRead (Address, Width, &Data, Config); + Data = (Data & Mask) | Value; + GnbLibIoWrite (Address, Width, &Data, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Indirect IO block read + * + * + * + * @param[in] IndexPort Index Port + * @param[in] DataPort Data Port + * @param[in] Width Access width + * @param[in] IndexAddress Index Address + * @param[in] Count Count + * @param[in] Buffer Buffer + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibIndirectIoBlockRead ( + IN UINT16 IndexPort, + IN UINT16 DataPort, + IN ACCESS_WIDTH Width, + IN UINT32 IndexAddress, + IN UINT32 Count, + IN VOID *Buffer, + IN VOID *Config + ) +{ + UINT32 Index; + + for (Index = IndexAddress; Index < (IndexAddress + Count); Index++) { + GnbLibIoWrite (IndexPort, Width, &Index, Config); + GnbLibIoRead (DataPort, Width, Buffer, Config); + Buffer = (VOID *) ((UINT8 *) Buffer + LibAmdAccessWidth (Width)); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get IOAPIC ID + * + * + * + * @param[in] IoApicBaseAddress IO APIC base address + * @param[in] Config Pointer to standard header + */ +UINT8 +GnbLiGetIoapicId ( + IN UINT64 IoApicBaseAddress, + IN VOID *Config + ) +{ + UINT32 Value; + Value = 0x0; + GnbLibMemWrite (IoApicBaseAddress, AccessWidth32, &Value, Config); + GnbLibMemRead (IoApicBaseAddress + 0x10, AccessWidth32, &Value, Config); + return (UINT8) (Value >> 24); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write MMIO registers + * + * + * + * @param[in] Address Physical address + * @param[in] Width Access width + * @param[in] Mask AND Mask + * @param[in] Value OR Value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibMemRMW ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibMemRead (Address, Width, &Data, Config); + Data = (Data & Mask) | Value; + GnbLibMemWrite (Address, Width, &Data, Config); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Claculate power of number + * + * + * + * @param[in] Value Number + * @param[in] Power Power + */ + +UINT32 +GnbLibPowerOf ( + IN UINT32 Value, + IN UINT32 Power + ) +{ + UINT32 Result; + if (Power == 0) { + return 1; + } + Result = Value; + while ((--Power) > 0) { + Result *= Value; + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Search buffer for pattern + * + * + * @param[in] Buf1 Pointer to source buffer which will be subject of search + * @param[in] Buf1Length Length of the source buffer + * @param[in] Buf2 Pointer to pattern buffer + * @param[in] Buf2Length Length of the pattern buffer + * @retval Pointer on first accurance of Buf2 in Buf1 or NULL + */ + +VOID* +GnbLibFind ( + IN UINT8 *Buf1, + IN UINTN Buf1Length, + IN UINT8 *Buf2, + IN UINTN Buf2Length + ) +{ + UINT8 *CurrentBuf1Ptr; + CurrentBuf1Ptr = Buf1; + while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { + UINT8 *SourceBufPtr; + UINT8 *PatternBufPtr; + UINTN PatternBufLength; + SourceBufPtr = CurrentBuf1Ptr; + PatternBufPtr = Buf2; + PatternBufLength = Buf2Length; + while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0)); + if (PatternBufLength == 0) { + return CurrentBuf1Ptr; + } + CurrentBuf1Ptr++; + } + return NULL; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump buffer to HDTOUT + * + * + * @param[in] Buffer Buffer pointer + * @param[in] Count Count of data elements + * @param[in] DataWidth DataWidth 1 - Byte; 2 - Word; 3 - DWORD; 4 - QWORD + * @param[in] LineWidth Number of data item per line + */ +VOID +GnbLibDebugDumpBuffer ( + IN VOID *Buffer, + IN UINT32 Count, + IN UINT8 DataWidth, + IN UINT8 LineWidth + ) +{ + UINT32 Index; + UINT32 DataItemCount; + ASSERT (LineWidth != 0); + ASSERT (DataWidth >= 1 && DataWidth <= 4); + DataItemCount = 0; + for (Index = 0; Index < Count; ) { + switch (DataWidth) { + case 1: + IDS_HDT_CONSOLE (GNB_TRACE, "%02x ", *((UINT8 *) Buffer + Index)); + Index += 1; + break; + case 2: + IDS_HDT_CONSOLE (GNB_TRACE, "%04x ", *(UINT16 *) ((UINT8 *) Buffer + Index)); + Index += 2; + break; + case 3: + IDS_HDT_CONSOLE (GNB_TRACE, "%08x ", *(UINT32 *) ((UINT8 *) Buffer + Index)); + Index += 4; + break; + case 4: + IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4)); + Index += 8; + break; + default: + IDS_HDT_CONSOLE (GNB_TRACE, "ERROR! Incorrect Data Width\n"); + return; + } + if (++DataItemCount >= LineWidth) { + IDS_HDT_CONSOLE (GNB_TRACE, "\n"); + DataItemCount = 0; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump buffer to HDTOUT + * + * + * @param[in] ServiceId Service ID + * @param[in] SocketId Socket ID + * @param[in] ServiceProtocol Service protocol + * @param[in] StdHeader Standard Configuration Header + */ +AGESA_STATUS +GnbLibLocateService ( + IN GNB_SERVICE_ID ServiceId, + IN UINT8 SocketId, + IN VOID **ServiceProtocol, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GNB_SERVICE *SeviceEntry; + CPU_LOGICAL_ID LogicalId; + SeviceEntry = ServiceTable; + GetLogicalIdOfSocket (SocketId, &LogicalId, StdHeader); + while (SeviceEntry != NULL) { + if (SeviceEntry->ServiceId == ServiceId && (LogicalId.Family & SeviceEntry->Family) != 0) { + *ServiceProtocol = SeviceEntry->ServiceProtocol; + return AGESA_SUCCESS; + } + SeviceEntry = SeviceEntry->NextService; + } + return AGESA_UNSUPPORTED; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h new file mode 100644 index 0000000000..ffbeba60af --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h @@ -0,0 +1,193 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBLIB_H_ +#define _GNBLIB_H_ + +#define IOC_WRITE_ENABLE 0x80 + +VOID +GnbLibPciIndirectReadField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + OUT UINT32 *Value, + IN VOID *Config + ); + +VOID +GnbLibPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *Config + ); + +VOID +GnbLibPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *Config + ); + +VOID +GnbLibPciIndirectRMW ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + +VOID +GnbLibPciIndirectWriteField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN VOID *Config + ); + + +VOID +GnbLibPciRMW ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + +VOID +GnbLibIoRMW ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + + +UINT32 +GnbLibPowerOf ( + IN UINT32 Value, + IN UINT32 Power + ); + +VOID* +GnbLibFind ( + IN UINT8 *Buf1, + IN UINTN Buf1Length, + IN UINT8 *Buf2, + IN UINTN Buf2Length + ); + +VOID +GnbLibIndirectIoBlockRead ( + IN UINT16 IndexPort, + IN UINT16 DataPort, + IN ACCESS_WIDTH Width, + IN UINT32 IndexAddress, + IN UINT32 Count, + IN VOID *Buffer, + IN VOID *Config + ); + +UINT8 +GnbLiGetIoapicId ( + IN UINT64 IoApicBaseAddress, + IN VOID *Config + ); + +VOID +GnbLibDebugDumpBuffer ( + IN VOID *Buffer, + IN UINT32 Count, + IN UINT8 DataWidth, + IN UINT8 LineWidth + ); + +AGESA_STATUS +GnbLibLocateService ( + IN GNB_SERVICE_ID ServiceId, + IN UINT8 SocketId, + IN VOID **ServiceProtocol, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c new file mode 100644 index 0000000000..39259f7e4d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c @@ -0,0 +1,157 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access various CPU registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "GnbLibCpuAcc.h" +#include "GnbLibPciAcc.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read CPU (DCT) indirect registers + * + * + * + * @param[in] Address PCI address of DCT register + * @param[in] IndirectAddress Offset of DCT register + * @param[out] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibCpuPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + OUT UINT32 *Value, + IN VOID *Config + ) +{ + UINT32 OffsetRegisterValue; + GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); + do { + GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); + } while ((OffsetRegisterValue & BIT31) == 0); + GnbLibPciRead (Address + 4, AccessWidth32, Value, Config); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Write CPU (DCT) indirect registers + * + * + * + * @param[in] Address PCI address of DCT register + * @param[in] IndirectAddress Offset of DCT register + * @param[in] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibCpuPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT32 *Value, + IN VOID *Config + ) +{ + UINT32 OffsetRegisterValue; + OffsetRegisterValue = IndirectAddress | BIT30; + GnbLibPciWrite (Address + 4, AccessWidth32, Value, Config); + GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); + do { + GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); + } while ((OffsetRegisterValue & BIT31) == 0); +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h new file mode 100644 index 0000000000..4eea7b8be1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h @@ -0,0 +1,92 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access various CPU registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _CPUACCLIB_H_ +#define _CPUACCLIB_H_ + +VOID +GnbLibCpuPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT32 *Value, + IN VOID *Config + ); + +VOID +GnbLibCpuPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + OUT UINT32 *Value, + IN VOID *Config + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c new file mode 100644 index 0000000000..aa243de9ef --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c @@ -0,0 +1,186 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access heap. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "heapManager.h" +#include "GnbLibPciAcc.h" +#include "GnbLibHeap.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------*/ +/** + * Allocates space for a new buffer in the heap + * + * + * @param[in] Handle Buffer handle + * @param[in] Length Buffer length + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer allocation fail + * + */ + +VOID * +GnbAllocateHeapBuffer ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + AllocHeapParams.RequestedBufferSize = (UINT32) Length; + AllocHeapParams.BufferHandle = Handle; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + return NULL; + } + return AllocHeapParams.BufferPtr; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Allocates space for a new buffer in the heap and clear it + * + * + * @param[in] Handle Buffer handle + * @param[in] Length Buffer length + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer allocation fail + * + */ + +VOID * +GnbAllocateHeapBufferAndClear ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + VOID *Buffer; + Buffer = GnbAllocateHeapBuffer (Handle, Length, StdHeader); + if (Buffer != NULL) { + LibAmdMemFill (Buffer, 0x00, Length, StdHeader); + } + return Buffer; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Locates a previously allocated buffer on the heap. + * + * + * @param[in] Handle Buffer handle + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer handle not found + * + */ + +VOID * +GnbLocateHeapBuffer ( + IN UINT32 Handle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + LOCATE_HEAP_PTR LocHeapParams; + LocHeapParams.BufferHandle = Handle; + Status = HeapLocateBuffer (&LocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + return NULL; + } + return LocHeapParams.BufferPtr; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h new file mode 100644 index 0000000000..61a618a900 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h @@ -0,0 +1,96 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access heap. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBHEAPLIB_H_ +#define _GNBHEAPLIB_H_ + +VOID * +GnbAllocateHeapBuffer ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID * +GnbLocateHeapBuffer ( + IN UINT32 Handle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID * +GnbAllocateHeapBufferAndClear ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c new file mode 100644 index 0000000000..b5341f87bd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c @@ -0,0 +1,149 @@ +/* $NoKeywords:$ */ +/** + * @file + * +* Service procedure to access I/O registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "GnbLibIoAcc.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------------------*/ +/** + * Write I/O Port + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[in] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibIoWrite ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ) +{ + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_IO_WRITE (StdHeader, Address, Width, Value); + } + LibAmdIoWrite (Width, Address, Value, StdHeader); +} +/** + * Read IO port + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[out] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibIoRead ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ) +{ + LibAmdIoRead (Width, Address, Value, StdHeader); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h new file mode 100644 index 0000000000..0066fad004 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h @@ -0,0 +1,93 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access I/O registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _IOACCLIB_H_ +#define _IOACCLIB_H_ + + +VOID +GnbLibIoWrite ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ); + +VOID +GnbLibIoRead ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c new file mode 100644 index 0000000000..affdb10218 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c @@ -0,0 +1,152 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access MMIO registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "GnbLibMemAcc.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Write Memory/MMIO registers + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[in] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibMemWrite ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ) +{ + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_MEM_WRITE (StdHeader, Address, Width, Value); + } + LibAmdMemWrite (Width, Address, Value, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read Memory/MMIO registers + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[out] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibMemRead ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ) +{ + LibAmdMemRead (Width, Address, Value, StdHeader); +} + + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h new file mode 100644 index 0000000000..e0179d2669 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h @@ -0,0 +1,100 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access MMIO registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _MEMACCLIB_H_ +#define _MEMACCLIB_H_ + +VOID +GnbLibMemWrite ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ); + +VOID +GnbLibMemRead ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ); + +VOID +GnbLibMemRMW ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c new file mode 100644 index 0000000000..1353342a54 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c @@ -0,0 +1,430 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various PCI service routines. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +#include "AGESA.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbLibPciAcc.h" +#include "GnbLibPci.h" +#include "GnbLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device present + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is present + * @retval FALSE Device is not present + */ + +BOOLEAN +GnbLibPciIsDevicePresent ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 DeviceId; + GnbLibPciRead (Address, AccessWidth32, &DeviceId, StdHeader); + if (DeviceId == 0xffffffff) { + return FALSE; + } else { + return TRUE; + } +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device is bridge + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is a bridge + * @retval FALSE Device is not a bridge + */ + +BOOLEAN +GnbLibPciIsBridgeDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Header; + GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader); + if ((Header & 0x7f) == 1) { + return TRUE; + } else { + return FALSE; + } +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device is multifunction + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is a multifunction device. + * @retval FALSE Device is a single function device. + * + */ +BOOLEAN +GnbLibPciIsMultiFunctionDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Header; + GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader); + if ((Header & 0x80) != 0) { + return TRUE; + } else { + return FALSE; + } +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device is PCIe device + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is a PCIe device + * @retval FALSE Device is not a PCIe device + * + */ + +BOOLEAN +GnbLibPciIsPcieDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (GnbLibFindPciCapability (Address, PCIE_CAP_ID, StdHeader) != 0 ) { + return TRUE; + } else { + return FALSE; + } +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Find PCI capability pointer + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] CapabilityId PCI capability ID + * @param[in] StdHeader Standard configuration header + * @retval Register address of capability pointer + * + */ + +UINT8 +GnbLibFindPciCapability ( + IN UINT32 Address, + IN UINT8 CapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 CapabilityPtr; + UINT8 CurrentCapabilityId; + CapabilityPtr = 0x34; + if (!GnbLibPciIsDevicePresent (Address, StdHeader)) { + return 0; + } + while (CapabilityPtr != 0) { + GnbLibPciRead (Address | CapabilityPtr, AccessWidth8 , &CapabilityPtr, StdHeader); + if (CapabilityPtr != 0) { + GnbLibPciRead (Address | CapabilityPtr , AccessWidth8 , &CurrentCapabilityId, StdHeader); + if (CurrentCapabilityId == CapabilityId) { + break; + } + CapabilityPtr++; + } + } + return CapabilityPtr; +} +/*----------------------------------------------------------------------------------------*/ +/* + * Find PCIe extended capability pointer + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] ExtendedCapabilityId Extended PCIe capability ID + * @param[in] StdHeader Standard configuration header + * @retval Register address of extended capability pointer + * + */ + +#if 0 /* Not used */ +UINT16 +GnbLibFindPcieExtendedCapability ( + IN UINT32 Address, + IN UINT16 ExtendedCapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 CapabilityPtr; + UINT32 ExtendedCapabilityIdBlock; + if (GnbLibPciIsPcieDevice (Address, StdHeader)) { + GnbLibPciRead (Address | 0x100 , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader); + if ((ExtendedCapabilityIdBlock != 0) && ((UINT16)ExtendedCapabilityIdBlock != 0xffff)) { + do { + CapabilityPtr = (UINT16) ((ExtendedCapabilityIdBlock >> 20) & 0xfff); + if ((UINT16)ExtendedCapabilityIdBlock == ExtendedCapabilityId) { + return CapabilityPtr; + } + GnbLibPciRead (Address | CapabilityPtr , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader); + } while (((ExtendedCapabilityIdBlock >> 20) & 0xfff) != 0); + } + } + return 0; +} +#endif +/*----------------------------------------------------------------------------------------*/ +/* + * Scan range of device on PCI bus. + * + * + * + * @param[in] Start Start address to start scan from + * @param[in] End End address of scan + * @param[in] ScanData Supporting data + * + */ +/*----------------------------------------------------------------------------------------*/ +VOID +GnbLibPciScan ( + IN PCI_ADDR Start, + IN PCI_ADDR End, + IN GNB_PCI_SCAN_DATA *ScanData + ) +{ + UINTN Bus; + UINTN Device; + UINTN LastDevice; + UINTN Function; + UINTN LastFunction; + PCI_ADDR PciDevice; + SCAN_STATUS Status; + + for (Bus = Start.Address.Bus; Bus <= End.Address.Bus; Bus++) { + Device = (Bus == Start.Address.Bus) ? Start.Address.Device : 0x00; + LastDevice = (Bus == End.Address.Bus) ? End.Address.Device : 0x1F; + for ( ; Device <= LastDevice; Device++) { + if ((Bus == Start.Address.Bus) && (Device == Start.Address.Device)) { + Function = Start.Address.Function; + } else { + Function = 0x0; + } + PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0); + if (!GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) { + continue; + } + if (GnbLibPciIsMultiFunctionDevice (PciDevice.AddressValue, ScanData->StdHeader)) { + if ((Bus == End.Address.Bus) && (Device == End.Address.Device)) { + LastFunction = Start.Address.Function; + } else { + LastFunction = 0x7; + } + } else { + LastFunction = 0x0; + } + for ( ; Function <= LastFunction; Function++) { + PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0); + if (GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) { + Status = ScanData->GnbScanCallback (PciDevice, ScanData); + if ((Status & SCAN_SKIP_FUNCTIONS) != 0) { + Function = LastFunction + 1; + } + if ((Status & SCAN_SKIP_DEVICES) != 0) { + Device = LastDevice + 1; + } + if ((Status & SCAN_SKIP_BUSES) != 0) { + Bus = End.Address.Bus + 1; + } + } + } + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Scan all subordinate buses + * + * + * @param[in] Bridge PCI bridge address + * @param[in,out] ScanData Scan configuration data + * + */ +VOID +GnbLibPciScanSecondaryBus ( + IN PCI_ADDR Bridge, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + PCI_ADDR StartRange; + PCI_ADDR EndRange; + UINT8 SecondaryBus; + GnbLibPciRead (Bridge.AddressValue | 0x19, AccessWidth8, &SecondaryBus, ScanData->StdHeader); + if (SecondaryBus != 0) { + StartRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0); + EndRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0x1f, 0x7, 0); + GnbLibPciScan (StartRange, EndRange, ScanData); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get PCIe device type + * + * + * + * @param[in] Device PCI address of device. + * @param[in] StdHeader Northbridge configuration structure pointer. + * + * @retval PCIE_DEVICE_TYPE + */ + /*----------------------------------------------------------------------------------------*/ + +PCIE_DEVICE_TYPE +GnbLibGetPcieDeviceType ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + UINT8 Value; + + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 0x2) , AccessWidth8, &Value, StdHeader); + return Value >> 4; + } + return PcieNotPcieDevice; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Save config space area + * + * + * + * @param[in] Address PCI address of device. + * @param[in] StartRegisterAddress Start register address. + * @param[in] EndRegisterAddress End register address. + * @param[in] Width Acess width. + * @param[in] StdHeader Standard header. + * + */ + /*----------------------------------------------------------------------------------------*/ + +VOID +GnbLibS3SaveConfigSpace ( + IN UINT32 Address, + IN UINT16 StartRegisterAddress, + IN UINT16 EndRegisterAddress, + IN ACCESS_WIDTH Width, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 Index; + UINT16 Delta; + UINT16 Length; + Length = (StartRegisterAddress < EndRegisterAddress) ? (EndRegisterAddress - StartRegisterAddress) : (StartRegisterAddress - EndRegisterAddress); + Delta = LibAmdAccessWidth (Width); + for (Index = 0; Index <= Length; Index = Index + Delta) { + GnbLibPciRMW ( + Address | ((StartRegisterAddress < EndRegisterAddress) ? (StartRegisterAddress + Index) : (StartRegisterAddress - Index)), + Width, + 0xffffffff, + 0x0, + StdHeader + ); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h new file mode 100644 index 0000000000..a0825cfa12 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h @@ -0,0 +1,186 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various PCI service routines. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBLIBPCI_H_ +#define _GNBLIBPCI_H_ + +#define PCIE_CAP_ID 0x10 +#define IOMMU_CAP_ID 0x0F + +/// PCIe device type +typedef enum { + PcieDeviceEndPoint, ///< Endpoint + PcieDeviceLegacyEndPoint, ///< Legacy endpoint + PcieDeviceRootComplex = 4, ///< Root complex + PcieDeviceUpstreamPort, ///< Upstream port + PcieDeviceDownstreamPort, ///< Downstream Port + PcieDevicePcieToPcix, ///< PCIe to PCI/PCIx bridge + PcieDevicePcixToPcie, ///< PCI/PCIx to PCIe bridge + PcieNotPcieDevice = 0xff ///< unknown device +} PCIE_DEVICE_TYPE; + +typedef UINT32 SCAN_STATUS; + +#define SCAN_SKIP_FUNCTIONS 0x1 +#define SCAN_SKIP_DEVICES 0x2 +#define SCAN_SKIP_BUSES 0x4 +#define SCAN_SUCCESS 0x0 + +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (GNB_PCI_SCAN_DATA); + +typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +///Scan supporting data +struct _GNB_PCI_SCAN_DATA { + GNB_SCAN_CALLBACK GnbScanCallback; ///< Callback for each found device + AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header +}; + +#define PCIE_CAP_ID 0x10 +#define PCIE_LINK_CAP_REGISTER 0x0C +#define PCIE_LINK_CTRL_REGISTER 0x10 +#define PCIE_DEVICE_CAP_REGISTER 0x04 +#define PCIE_DEVICE_CTRL_REGISTER 0x08 +#define PCIE_ASPM_L1_SUPPORT_CAP BIT11 + +#define MAX_PAYLOAD_128 0x0 ///< Max allowed payload size 128 bytes +#define MAX_PAYLOAD_256 0x1 ///< Max allowed payload size 256 bytes +#define MAX_PAYLOAD_512 0x2 ///< Max allowed payload size 512 bytes +#define MAX_PAYLOAD_1024 0x3 ///< Max allowed payload size 1024 bytes +#define MAX_PAYLOAD_2048 0x4 ///< Max allowed payload size 2048 bytes +#define MAX_PAYLOAD_4096 0x5 ///< Max allowed payload size 4096 bytes +#define MAX_PAYLOAD 0x5 ///< Max allowed payload size according to spec is 101b (4096 bytes) + +BOOLEAN +GnbLibPciIsDevicePresent ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbLibPciIsBridgeDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbLibPciIsMultiFunctionDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbLibPciIsPcieDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLibFindPciCapability ( + IN UINT32 Address, + IN UINT8 CapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibPciScan ( + IN PCI_ADDR Start, + IN PCI_ADDR End, + IN GNB_PCI_SCAN_DATA *ScanData + ); + +VOID +GnbLibPciScanSecondaryBus ( + IN PCI_ADDR Bridge, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +PCIE_DEVICE_TYPE +GnbLibGetPcieDeviceType ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibS3SaveConfigSpace ( + IN UINT32 Address, + IN UINT16 StartRegisterAddress, + IN UINT16 EndRegisterAddress, + IN ACCESS_WIDTH Width, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c new file mode 100644 index 0000000000..ccb2078120 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c @@ -0,0 +1,183 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "GnbLibPciAcc.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCI registers + * + * + * + * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) + * @param[in] Width Access width + * @param[in] Value Pointer to value + * @param[in] StdHeader Pointer to standard header + */ +VOID +GnbLibPciWrite ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PciAddress.AddressValue = Address; + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_PCI_WRITE (StdHeader, PciAddress, Width, Value); + } + LibAmdPciWrite (Width, PciAddress, Value, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PCI registers + * + * + * + * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) + * @param[in] Width Access width + * @param[out] Value Pointer to value + * @param[in] StdHeader Pointer to standard header + */ + +VOID +GnbLibPciRead ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PciAddress.AddressValue = Address; + LibAmdPciRead (Width, PciAddress, Value, StdHeader); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Poll PCI reg + * + * + * + * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) + * @param[in] Width Access width + * @param[in] Data Data to compare + * @param[in] DataMask AND mask + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibPciPoll ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Data, + IN VOID *DataMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PciAddress.AddressValue = Address; + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_PCI_POLL (StdHeader, PciAddress, Width, Data, DataMask, 0xffffffff); + } + LibAmdPciPoll (Width, PciAddress, Data, DataMask, 0xffffffff, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h new file mode 100644 index 0000000000..a921bf13bd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h @@ -0,0 +1,100 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBLIBPCIACC_H_ +#define _GNBLIBPCIACC_H_ + +VOID +GnbLibPciWrite ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibPciRead ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibPciPoll ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Data, + IN VOID *DataMask, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c new file mode 100644 index 0000000000..d6936d4f24 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c @@ -0,0 +1,542 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific function translation + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] EngineType Engine Type + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_UNSUPPORTED No more configuration available for given engine type + * @retval AGESA_ERROR Requested configuration not supported + */ +AGESA_STATUS +PcieFmConfigureEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId); + } + return AGESA_ERROR; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration value + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] CoreId Core ID + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value (for core configuration) + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Core configuration value can not be determined + */ +AGESA_STATUS +PcieFmGetCoreConfigurationValue ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieInitService->PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, ConfigurationValue); + } + return AGESA_ERROR; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if engine can be remapped to Device/function number requested by user + * defined engine descriptor + * + * Function only called if requested device/function does not much native device/function + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieFmCheckPortPciDeviceMapping ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine); + } + return FALSE; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration string + * + * Debug function for logging configuration + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] ConfigurationValue Configuration value + * @retval Configuration string + */ + +CONST CHAR8* +PcieFmDebugGetCoreConfigurationString ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_DEBUG_SERVICES *PcieDebugService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieDebugService->PcieFmDebugGetCoreConfigurationString (Wrapper, ConfigurationValue); + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get wrapper name + * + * Debug function for logging wrapper name + * + * @param[in] Wrapper Pointer to internal configuration data area + * @retval Wrapper Name string + */ + +CONST CHAR8* +PcieFmDebugGetWrapperNameString ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_DEBUG_SERVICES *PcieDebugService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieDebugService->PcieFmDebugGetWrapperNameString (Wrapper); + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get register address name + * + * Debug function for logging register trace + * + * @param[in] Silicon Silicon config descriptor + * @param[in] AddressFrame Address Frame + * @retval Register address name + */ +CONST CHAR8* +PcieFmDebugGetHostRegAddressSpaceString ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_DEBUG_SERVICES *PcieDebugService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Silicon->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieDebugService->PcieFmDebugGetHostRegAddressSpaceString (Silicon, AddressFrame); + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if the lane can be muxed by link width requested by user + * defined engine descriptor + * + * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). + * Check Engine StartCoreLane could be aligned by user requested link width x2. + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Lane can be muxed + * @retval FALSE Lane can NOT be muxed + */ + +BOOLEAN +PcieFmCheckPortPcieLaneCanBeMuxed ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmCheckPortPcieLaneCanBeMuxed (PortDescriptor, Engine); + } + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Map engine to specific PCI device address + * + * + * + * @param[in] Engine Pointer to engine configuration + * @retval AGESA_ERROR Fail to map PCI device address + * @retval AGESA_SUCCESS Successfully allocate PCI address + */ + +AGESA_STATUS +PcieFmMapPortPciAddress ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmMapPortPciAddress (Engine); + } + return AGESA_ERROR; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get total number of silicons/wrappers/engines for this complex + * + * + * + * @param[in] SocketId Socket ID. + * @param[out] Length Length of configuration info block + * @param[out] StdHeader Standard Configuration Header + * @retval AGESA_SUCCESS Configuration data length is correct + */ +AGESA_STATUS +PcieFmGetComplexDataLength ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmGetComplexDataLength (SocketId, Length, StdHeader); + } + return Status; +} + + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Build configuration + * + * + * @param[in] SocketId Socket ID. + * @param[out] Buffer Pointer to buffer to build internal complex data structure + * @param[out] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieFmBuildComplexConfiguration ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get max link speed capability supported by this port + * + * + * + * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX + * @param[in] Engine Pointer to engine config descriptor + * @retval PcieGen1/PcieGen2 Max supported link gen capability + */ +PCIE_LINK_SPEED_CAP +PcieFmGetLinkSpeedCap ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieInitService->PcieFmGetLinkSpeedCap (Flags, Engine); + } + return PcieGen1; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get native PHY lane bitmap + * + * + * @param[in] PhyLaneBitmap Package PHY lane bitmap + * @param[in] Engine Standard configuration header. + * @retval Native PHY lane bitmap + */ +UINT32 +PcieFmGetNativePhyLaneBitmap ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieInitService->PcieFmGetNativePhyLaneBitmap (PhyLaneBitmap, Engine); + } + return 0x0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set current link speed + * + * + * @param[in] LinkSpeedCapability Link Speed Capability + * @param[in] Engine Pointer to engine configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieFmSetLinkSpeedCap ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + PcieInitService->PcieFmSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get SB port info + * + * + * @param[out] SocketId Socket ID + * @param[out] SbPort Pointer to SB configuration descriptor + * @param[in] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS SB configuration determined successfully + */ +AGESA_STATUS +PcieFmGetSbConfigInfo ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmGetSbConfigInfo (SocketId, SbPort, StdHeader); + } + return Status; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c new file mode 100644 index 0000000000..2ac05a2c60 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c @@ -0,0 +1,157 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific function translation + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbFamServices.h" +#include "GnbCommonLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if IOMMU unit present and enabled + * + * + * + * + * @param[in] GnbHandle Gnb handle + * @param[in] StdHeader Standard configuration header + * + */ +BOOLEAN +GnbFmCheckIommuPresent ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GNB_FAM_IOMMU_SERVICES *GnbIommuConfigService; + Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return GnbIommuConfigService->GnbFmCheckIommuPresent (GnbHandle, StdHeader); + } + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVRS entry + * + * + * @param[in] GnbHandle Gnb handle + * @param[in] Type Entry type + * @param[in] Ivrs IVRS table pointer + * @param[in] StdHeader Standard configuration header + * + */ + +AGESA_STATUS +GnbFmCreateIvrsEntry ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GNB_FAM_IOMMU_SERVICES *GnbIommuConfigService; + Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return GnbIommuConfigService->GnbFmCreateIvrsEntry (GnbHandle, Type, Ivrs, StdHeader); + } + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c new file mode 100644 index 0000000000..e142ac7d0d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c @@ -0,0 +1,160 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbGfxConfig.h" +#include "GfxConfigLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxConfigEnvInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Update GFX config info at ENV + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxConfigEnvInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + AMD_ENV_PARAMS *EnvParamsPtr; + GFX_PLATFORM_CONFIG *Gfx; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Enter\n"); + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader; + Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex; + Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum; + Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate; + Gfx->LvdsPowerOnSeqDigonToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDigonToDe; + Gfx->LvdsPowerOnSeqDeToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToVaryBl; + Gfx->LvdsPowerOnSeqDeToDigon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToDigon; + Gfx->LvdsPowerOnSeqVaryBlToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToDe; + Gfx->LvdsPowerOnSeqOnToOffDelay = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqOnToOffDelay; + Gfx->LvdsPowerOnSeqVaryBlToBlon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToBlon; + Gfx->LvdsPowerOnSeqBlonToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqBlonToVaryBl; + Gfx->LvdsMaxPixelClockFreq = EnvParamsPtr->GnbEnvConfiguration.LvdsMaxPixelClockFreq; + Gfx->LcdBitDepthControlValue = EnvParamsPtr->GnbEnvConfiguration.LcdBitDepthControlValue; + Gfx->Lvds24bbpPanelMode = EnvParamsPtr->GnbEnvConfiguration.Lvds24bbpPanelMode; + Gfx->LvdsMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscControl.Value; + Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum; + Gfx->GnbRemoteDisplaySupport = EnvParamsPtr->GnbEnvConfiguration.GnbRemoteDisplaySupport; + Gfx->gfxplmcfg0 = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscVoltAdjustment; + Gfx->DisplayMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.DisplayMiscControl.Value; + GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader); + } + GNB_DEBUG_CODE ( + GfxConfigDebugDump (Gfx); + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c new file mode 100644 index 0000000000..cdf477166c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c @@ -0,0 +1,259 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GfxConfigLib.h" +#include "GnbCommonLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable GMM Access + * + * + * + * @param[in,out] Gfx Pointer to GFX configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxEnableGmmAccess ( + IN OUT GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 Value; + + if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + + // Check if base address for GMM allocated + GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx)); + if (Gfx->GmmBase == 0) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + // Check if base address for FB allocated + GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); + if ((Value & 0xfffffff0) == 0) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + //Push CPU MMIO pci config to S3 script + GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); + // Turn on memory decoding on APC to enable access to GMM register space + if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) { + GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); + //Push APC pci config to S3 script + GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); + GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); + } + // Turn on memory decoding on GFX to enable access to GMM register space + GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); + //Push iGPU pci config to S3 script + GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); + GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); + return AGESA_SUCCESS; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get UMA info + * + * UMA info stored on heap by memory module + * + * @param[out] UmaInfo Pointer to UMA info structure + * @param[in] StdHeader Standard configuration header + */ + +VOID +GfxGetUmaInfo ( + OUT UMA_INFO *UmaInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UMA_INFO *MemUmaInfo; + + MemUmaInfo = GnbLocateHeapBuffer (AMD_UMA_INFO_HANDLE, StdHeader); + if (MemUmaInfo == NULL) { + LibAmdMemFill (UmaInfo, 0x00, sizeof (UMA_INFO), StdHeader); + UmaInfo->UmaMode = UMA_NONE; + } else { + LibAmdMemCopy (UmaInfo, MemUmaInfo, sizeof (UMA_INFO), StdHeader); + if ((UmaInfo->UmaBase == 0) || (UmaInfo->UmaSize == 0)) { + UmaInfo->UmaMode = UMA_NONE; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate UMA configuration data + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in,out] Gfx Pointer to GFX configuration + * @retval AGESA_STATUS Data located + * @retval AGESA_FATA Data not found + */ + +AGESA_STATUS +GfxLocateConfigData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT GFX_PLATFORM_CONFIG **Gfx + ) +{ + *Gfx = GnbLocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, StdHeader); + if (*Gfx == NULL) { + IDS_ERROR_TRAP; + return AGESA_FATAL; + } + (*Gfx)->StdHeader = /* (PVOID) */(UINT32) StdHeader; + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Debug dump + * + * + * + * @param[in] Gfx Pointer to GFX configuration + */ + +VOID +GfxConfigDebugDump ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config Start ------------->\n"); + IDS_HDT_CONSOLE (GFX_MISC, " HD Audio - %s\n", (Gfx->GnbHdAudio == 0) ? "Disabled" : "Enabled"); + IDS_HDT_CONSOLE (GFX_MISC, " DynamicRefreshRate - 0x%x\n", Gfx->DynamicRefreshRate); + IDS_HDT_CONSOLE (GFX_MISC, " LcdBackLightControl - 0x%x\n", Gfx->LcdBackLightControl); + IDS_HDT_CONSOLE (GFX_MISC, " AbmSupport - %s\n", (Gfx->AbmSupport == 0) ? "Disabled" : "Enabled"); + IDS_HDT_CONSOLE (GFX_MISC, " GmcClockGating - %s\n", (Gfx->GmcClockGating == 0) ? "Disabled" : "Enabled"); + IDS_HDT_CONSOLE (GFX_MISC, " GmcPowerGating - %s\n", + (Gfx->GmcPowerGating == GmcPowerGatingDisabled) ? "Disabled" : ( + (Gfx->GmcPowerGating == GmcPowerGatingStutterOnly) ? "GmcPowerGatingStutterOnly" : ( + (Gfx->GmcPowerGating == GmcPowerGatingWidthStutter) ? "GmcPowerGatingWidthStutter" : "Unknown")) + ); + IDS_HDT_CONSOLE (GFX_MISC, " UmaSteering - %s\n", + (Gfx->UmaSteering == excel993 ) ? "excel993" : ( + (Gfx->UmaSteering == excel992 ) ? "excel992" : "Unknown") + ); + IDS_HDT_CONSOLE (GFX_MISC, " iGpuVgaMode - %s\n", + (Gfx->iGpuVgaMode == iGpuVgaAdapter) ? "VGA" : ( + (Gfx->iGpuVgaMode == iGpuVgaNonAdapter) ? "Non VGA" : "Unknown") + ); + IDS_HDT_CONSOLE (GFX_MISC, " UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA"); + if (Gfx->UmaInfo.UmaMode != UMA_NONE) { + IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase); + IDS_HDT_CONSOLE (GFX_MISC, " UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize); + IDS_HDT_CONSOLE (GFX_MISC, " UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes); + } + IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config End --------------->\n"); + +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h new file mode 100644 index 0000000000..0c0aef794c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h @@ -0,0 +1,98 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GFXCONFIGLIB_H_ +#define _GFXCONFIGLIB_H_ + +VOID +GfxConfigDebugDump ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGetUmaInfo ( + OUT UMA_INFO *UmaInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GfxLocateConfigData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT GFX_PLATFORM_CONFIG **Gfx + ); + +AGESA_STATUS +GfxEnableGmmAccess ( + IN OUT GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c new file mode 100644 index 0000000000..f2323aa754 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c @@ -0,0 +1,140 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbGfxConfig.h" +#include "GfxConfigLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxConfigMidInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Update GFX config info at ENV + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxConfigMidInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + AMD_MID_PARAMS *MidParamsPtr; + GFX_PLATFORM_CONFIG *Gfx; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigMidInterface Enter\n"); + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + MidParamsPtr = (AMD_MID_PARAMS *) StdHeader; + Gfx->iGpuVgaMode = MidParamsPtr->GnbMidConfiguration.iGpuVgaMode; + } + GNB_DEBUG_CODE ( + GfxConfigDebugDump (Gfx); + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigMidInterface Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c new file mode 100644 index 0000000000..04efa71a53 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c @@ -0,0 +1,163 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GfxConfigLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxConfigPostInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Allocate UMA configuration data + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxConfigPostInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GFX_PLATFORM_CONFIG *Gfx; + AMD_POST_PARAMS *PostParamsPtr; + AGESA_STATUS Status; + PostParamsPtr = (AMD_POST_PARAMS *)StdHeader; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n"); + Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader); + ASSERT (Gfx != NULL); + if (Gfx != NULL) { + LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader); + if (GnbBuildOptions.IgfxModeAsPcieEp) { + Gfx->GfxControllerMode = GfxControllerPcieEndpointMode; + Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0); + } else { + Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode; + Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0); + } + Gfx->StdHeader = /* (PVOID) */(UINT32) StdHeader; + Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio; + Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport; + Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate; + Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl; + Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType; + Gfx->GmcClockGating = GnbBuildOptions.CfgGmcClockGating; + Gfx->GmcPowerGating = GnbBuildOptions.GmcPowerGating; + Gfx->UmaSteering = excel992 ; + GNB_DEBUG_CODE ( + GfxConfigDebugDump (Gfx); + ); + } else { + Status = AGESA_ERROR; + } + IDS_OPTION_HOOK (IDS_GNB_PLATFORMCFG_OVERRIDE, Gfx, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Exit [0x%x]\n", Status); + return Status; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h new file mode 100644 index 0000000000..b94ae4a9f4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h @@ -0,0 +1,78 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBGFXCONFIG_H_ +#define _GNBGFXCONFIG_H_ + +#include "GfxConfigLib.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c new file mode 100644 index 0000000000..cc16c333a1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c @@ -0,0 +1,211 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to collect discrete GFX card info + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GfxCardInfo.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + GFX_CARD_CARD_INFO *GfxCardInfo; + PCI_ADDR BaseBridge; + UINT8 BusNumber; +} GFX_SCAN_DATA; + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +SCAN_STATUS +GfxScanPcieDevice ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get information about all discrete GFX card in system + * + * + * + * @param[out] GfxCardInfo Pointer to GFX card info structure + * @param[in] StdHeader Standard configuration header + */ + +VOID +GfxGetDiscreteCardInfo ( + OUT GFX_CARD_CARD_INFO *GfxCardInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GFX_SCAN_DATA GfxScanData; + PCI_ADDR Start; + PCI_ADDR End; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Enter\n"); + Start.AddressValue = MAKE_SBDFO (0, 0, 2, 0, 0); + End.AddressValue = MAKE_SBDFO (0, 0, 0x1f, 7, 0); + GfxScanData.BusNumber = 5; + GfxScanData.ScanData.GnbScanCallback = GfxScanPcieDevice; + GfxScanData.ScanData.StdHeader = StdHeader; + GfxScanData.GfxCardInfo = GfxCardInfo; + GnbLibPciScan (Start, End, &GfxScanData.ScanData); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +SCAN_STATUS +GfxScanPcieDevice ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + UINT8 ClassCode; + UINT32 VendorId; + + IDS_HDT_CONSOLE (GFX_MISC, " Evaluate device [%d:%d:%d]\n", + Device.Address.Bus, Device.Address.Device, Device.Address.Function + ); + + if (GnbLibPciIsBridgeDevice (Device.AddressValue, ScanData->StdHeader)) { + UINT32 SaveBusConfiguration; + UINT32 Value; + + if (Device.Address.Bus == 0) { + ((GFX_SCAN_DATA *) ScanData)->BaseBridge = Device; + } + GnbLibPciRead (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader); + Value = (((0xFF << 8) | ((GFX_SCAN_DATA *) ScanData)->BusNumber) << 8) | Device.Address.Bus; + GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &Value, ScanData->StdHeader); + ((GFX_SCAN_DATA *) ScanData)->BusNumber++; + + GnbLibPciScanSecondaryBus (Device, ScanData); + + ((GFX_SCAN_DATA *) ScanData)->BusNumber--; + GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader); + return 0; + } + GnbLibPciRead (Device.AddressValue | 0x0b, AccessWidth8, &ClassCode, ScanData->StdHeader); + if (ClassCode == 3) { + IDS_HDT_CONSOLE (GFX_MISC, " Found GFX Card\n" + ); + + GnbLibPciRead (Device.AddressValue | 0x00, AccessWidth32, &VendorId, ScanData->StdHeader); + if (!GnbLibPciIsPcieDevice (Device.AddressValue, ScanData->StdHeader)) { + IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is PCI device\n" + ); + ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PciGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); + return 0; + } + if ((UINT16) VendorId == 0x1002) { + IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is AMD PCIe device\n" + ); + ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->AmdPcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); + } + ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); + } + return 0; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h new file mode 100644 index 0000000000..e90ea23694 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h @@ -0,0 +1,83 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to collect discrete GFX card info + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +#ifndef _GFXCARDINFO_H_ +#define _GFXCARDINFO_H_ + +VOID +GfxGetDiscreteCardInfo ( + OUT GFX_CARD_CARD_INFO *GfxCardInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c new file mode 100644 index 0000000000..1e89d03f19 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -0,0 +1,636 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Integrated Info Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieConfig.h" +#include "GnbGfxFamServices.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +typedef struct { + PCIE_CONNECTOR_TYPE ConnectorType; + UINT8 DisplayDeviceEnum; + UINT16 ConnectorEnum; + UINT16 EncoderEnum; + UINT8 ConnectorIndex; +} EXT_CONNECTOR_INFO; + +typedef struct { + UINT8 DisplayDeviceEnum; + UINT8 DeviceIndex; + UINT16 DeviceTag; + UINT16 DeviceAcpiEnum; +} EXT_DISPLAY_DEVICE_INFO; + +typedef struct { + AGESA_STATUS Status; + UINT8 DisplayDeviceEnum; + UINT8 RequestedPriorityIndex; + UINT8 CurrentPriorityIndex; + PCIe_ENGINE_CONFIG *Engine; +} CONNECTOR_ENUM_INFO; + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GfxIntegratedEnumConnectorsForDevice ( + IN UINT8 DisplayDeviceEnum, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxIntegratedDebugDumpDisplayPath ( + IN EXT_DISPLAY_PATH *DisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxIntegratedEnumerateAllConnectors ( + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxIntegratedCopyDisplayInfo ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPath, + OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +EXT_CONNECTOR_INFO ConnectorInfoTable[] = { + { + ConnectorTypeDP, + DEVICE_DFP, + CONNECTOR_DISPLAYPORT_ENUM, + ENCODER_NOT_PRESENT, + 0, + }, + { + ConnectorTypeEDP, + DEVICE_LCD, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeSingleLinkDVI, + DEVICE_DFP, + CONNECTOR_SINGLE_LINK_DVI_D_ENUM, + ENCODER_NOT_PRESENT, + 2 + }, + { + ConnectorTypeDualLinkDVI, + DEVICE_DFP, + CONNECTOR_DUAL_LINK_DVI_D_ENUM, + ENCODER_NOT_PRESENT, + 3 + }, + { + ConnectorTypeHDMI, + DEVICE_DFP, + CONNECTOR_HDMI_TYPE_A_ENUM, + ENCODER_NOT_PRESENT, + 4 + }, + { + ConnectorTypeTravisDpToVga, + DEVICE_CRT, + CONNECTOR_VGA_ENUM, + ENCODER_TRAVIS_ENUM_ID1, + 5 + }, + { + ConnectorTypeTravisDpToLvds, + DEVICE_LCD, + CONNECTOR_LVDS_ENUM, + ENCODER_TRAVIS_ENUM_ID2, + 6 + }, + { + ConnectorTypeNutmegDpToVga, + DEVICE_CRT, + CONNECTOR_VGA_ENUM, + ENCODER_ALMOND_ENUM_ID1, + 5 + }, + { + ConnectorTypeSingleLinkDviI, + DEVICE_DFP, + CONNECTOR_SINGLE_LINK_DVI_I_ENUM, + ENCODER_NOT_PRESENT, + 5 + }, + { + ConnectorTypeCrt, + DEVICE_CRT, + CONNECTOR_VGA_ENUM, + ENCODER_NOT_PRESENT, + 5 + }, + { + ConnectorTypeLvds, + DEVICE_LCD, + CONNECTOR_LVDS_ENUM, + ENCODER_NOT_PRESENT, + 6 + }, + { + ConnectorTypeEDPToLvds, + DEVICE_LCD, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeEDPToRealtecLvds, + DEVICE_LCD, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeAutoDetect, + DEVICE_LCD, + CONNECTOR_LVDS_eDP_ENUM, + ENCODER_TRAVIS_ENUM_ID2, + 7 + }, +}; + +UINT8 ConnectorNumerArray[] = { +// DP eDP SDVI-D DDVI-D HDMI VGA LVDS Auto (eDP, LVDS, Travis LVDS) + 6, 1, 6, 6, 6, 1, 1, 2 +}; +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] ConnectorType Connector type (see PCIe_DDI_DATA::ConnectorType). + * @retval Pointer to EXT_CONNECTOR_INFO + * @retval NULL if connector type unknown. + */ +STATIC EXT_CONNECTOR_INFO* +GfxIntegratedExtConnectorInfo ( + IN UINT8 ConnectorType + ) +{ + UINTN Index; + for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) { + if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) { + return &ConnectorInfoTable[Index]; + } + } + return NULL; +} + +EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = { + { + DEVICE_CRT, + 1, + ATOM_DEVICE_CRT1_SUPPORT, + 0x100, + }, + { + DEVICE_LCD, + 1, + ATOM_DEVICE_LCD1_SUPPORT, + 0x110, + }, + { + DEVICE_DFP, + 1, + ATOM_DEVICE_DFP1_SUPPORT, + 0x210, + }, + { + DEVICE_DFP, + 2, + ATOM_DEVICE_DFP2_SUPPORT, + 0x220, + }, + { + DEVICE_DFP, + 3, + ATOM_DEVICE_DFP3_SUPPORT, + 0x230, + }, + { + DEVICE_DFP, + 4, + ATOM_DEVICE_DFP4_SUPPORT, + 0x240, + }, + { + DEVICE_DFP, + 5, + ATOM_DEVICE_DFP5_SUPPORT, + 0x250, + }, + { + DEVICE_DFP, + 6, + ATOM_DEVICE_DFP6_SUPPORT, + 0x260, + } +}; +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] DisplayDeviceEnum Display device enum + * @param[in] DisplayDeviceIndex Display device index + * @retval Pointer to EXT_DISPLAY_DEVICE_INFO + * @retval NULL if can not get display device info + */ +STATIC EXT_DISPLAY_DEVICE_INFO* +GfxIntegratedExtDisplayDeviceInfo ( + IN UINT8 DisplayDeviceEnum, + IN UINT8 DisplayDeviceIndex + ) +{ + UINT8 Index; + UINT8 LastIndex; + LastIndex = 0xff; + for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) { + if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) { + LastIndex = Index; + if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) { + return &DisplayDeviceInfoTable[Index]; + } + } + } + if (DisplayDeviceEnum == DEVICE_LCD && LastIndex != 0xff) { + return &DisplayDeviceInfoTable[LastIndex]; + } + return NULL; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors + * + * + * + * @param[out] DisplayPathList Display path list + * @param[in,out] Pcie PCIe platform configuration info + * @param[in] Gfx Gfx configuration info + */ +AGESA_STATUS +GfxIntegratedEnumerateAllConnectors ( + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Enter\n"); + Status = GfxIntegratedEnumConnectorsForDevice ( + DEVICE_DFP, + DisplayPathList, + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxIntegratedEnumConnectorsForDevice ( + DEVICE_CRT, + DisplayPathList, + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxIntegratedEnumConnectorsForDevice ( + DEVICE_LCD, + DisplayPathList, + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Exit [0x%x]\n", Status); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] Engine Engine configuration info + * @param[in,out] Buffer Buffer pointer + * @param[in] Pcie PCIe configuration info + */ +VOID +STATIC +GfxIntegratedDdiInterfaceCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + CONNECTOR_ENUM_INFO *ConnectorEnumInfo; + EXT_CONNECTOR_INFO *ExtConnectorInfo; + ConnectorEnumInfo = (CONNECTOR_ENUM_INFO*) Buffer; + ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType); + if (ExtConnectorInfo == NULL) { + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo->Status); + PcieConfigDisableEngine (Engine); + return; + } + if (ExtConnectorInfo->DisplayDeviceEnum != ConnectorEnumInfo->DisplayDeviceEnum) { + //Not device type we are looking for + return; + } + if (Engine->Type.Ddi.DisplayPriorityIndex >= ConnectorEnumInfo->RequestedPriorityIndex && + Engine->Type.Ddi.DisplayPriorityIndex < ConnectorEnumInfo->CurrentPriorityIndex) { + ConnectorEnumInfo->CurrentPriorityIndex = Engine->Type.Ddi.DisplayPriorityIndex; + ConnectorEnumInfo->Engine = Engine; + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] DisplayDeviceEnum Display device list + * @param[out] DisplayPathList Display path list + * @param[in,out] Pcie PCIe configuration info + * @param[in] Gfx Gfx configuration info + */ +AGESA_STATUS +GfxIntegratedEnumConnectorsForDevice ( + IN UINT8 DisplayDeviceEnum, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT8 DisplayDeviceIndex; + CONNECTOR_ENUM_INFO ConnectorEnumInfo; + EXT_CONNECTOR_INFO *ExtConnectorInfo; + EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo; + AGESA_STATUS Status; + UINT8 ConnectorIdArray[sizeof (ConnectorNumerArray)]; + ConnectorEnumInfo.Status = AGESA_SUCCESS; + DisplayDeviceIndex = 1; + ConnectorEnumInfo.RequestedPriorityIndex = 0; + ConnectorEnumInfo.DisplayDeviceEnum = DisplayDeviceEnum; + LibAmdMemFill (ConnectorIdArray, 0x00, sizeof (ConnectorIdArray), GnbLibGetHeader (Gfx)); + do { + ConnectorEnumInfo.Engine = NULL; + ConnectorEnumInfo.CurrentPriorityIndex = 0xff; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, + GfxIntegratedDdiInterfaceCallback, + &ConnectorEnumInfo, + Pcie + ); + if (ConnectorEnumInfo.Engine == NULL) { + break; // No more connector support this + } + ConnectorEnumInfo.RequestedPriorityIndex = ConnectorEnumInfo.CurrentPriorityIndex + 1; + ExtConnectorInfo = GfxIntegratedExtConnectorInfo (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.ConnectorType); + ASSERT (ExtConnectorInfo != NULL); + ASSERT (ExtConnectorInfo->ConnectorIndex < sizeof (ConnectorIdArray)); + if (ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] >= ConnectorNumerArray[ExtConnectorInfo->ConnectorIndex]) { + //Run out of supported connectors + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); + PcieConfigDisableEngine (ConnectorEnumInfo.Engine); + continue; + } + ConnectorEnumInfo.Engine->Type.Ddi.ConnectorId = ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] + 1; + ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (DisplayDeviceEnum, DisplayDeviceIndex); + if (ExtDisplayDeviceInfo == NULL) { + //Run out of supported display device types + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); + Status = AGESA_ERROR; + PcieConfigDisableEngine (ConnectorEnumInfo.Engine); + } + + if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); + Status = AGESA_ERROR; + PcieConfigDisableEngine (ConnectorEnumInfo.Engine); + } + + ConnectorEnumInfo.Engine->Type.Ddi.DisplayDeviceId = DisplayDeviceIndex; + + Status = GfxFmMapEngineToDisplayPath (ConnectorEnumInfo.Engine, DisplayPathList, Gfx); + AGESA_STATUS_UPDATE (Status, ConnectorEnumInfo.Status); + if (Status != AGESA_SUCCESS) { + continue; + } + ConnectorIdArray[ExtConnectorInfo->ConnectorIndex]++; + DisplayDeviceIndex++; + } while (ConnectorEnumInfo.Engine != NULL); + return ConnectorEnumInfo.Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize display path for given engine + * + * + * + * @param[in] Engine Engine configuration info + * @param[out] DisplayPath Display path list + * @param[out] SecondaryDisplayPath Secondary display path list + * @param[in] Gfx Gfx configuration info + */ + +VOID +GfxIntegratedCopyDisplayInfo ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPath, + OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + EXT_CONNECTOR_INFO *ExtConnectorInfo; + EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo; + ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType); + ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (ExtConnectorInfo->DisplayDeviceEnum, Engine->Type.Ddi.DisplayDeviceId); + DisplayPath->usDeviceConnector = ExtConnectorInfo->ConnectorEnum | (Engine->Type.Ddi.ConnectorId << 8); + DisplayPath->usDeviceTag = ExtDisplayDeviceInfo->DeviceTag; + DisplayPath->usDeviceACPIEnum = ExtDisplayDeviceInfo->DeviceAcpiEnum; + DisplayPath->ucExtAUXDDCLutIndex = Engine->Type.Ddi.DdiData.AuxIndex; + DisplayPath->ucExtHPDPINLutIndex = Engine->Type.Ddi.DdiData.HdpIndex; + DisplayPath->ucChPNInvert = Engine->Type.Ddi.DdiData.LanePnInversionMask; + DisplayPath->usCaps = Engine->Type.Ddi.DdiData.Flags; + DisplayPath->usExtEncoderObjId = ExtConnectorInfo->EncoderEnum; + if (Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue == 0) { + DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B; + } else { + DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue; + } + GNB_DEBUG_CODE ( + GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx); + ); + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) { + if (SecondaryDisplayPath != NULL) { + SecondaryDisplayPath->usDeviceConnector = DisplayPath->usDeviceConnector; + } + GNB_DEBUG_CODE ( + GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx); + ); + + if (Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue == 0) { + DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B; + } else { + DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue; + } + } +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump display path settings + * + * + * + * @param[in] DisplayPath Display path + * @param[in] Gfx Gfx configuration + */ + +VOID +GfxIntegratedDebugDumpDisplayPath ( + IN EXT_DISPLAY_PATH *DisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + IDS_HDT_CONSOLE (GFX_MISC, " usDeviceConnector = 0x%x\n", + DisplayPath->usDeviceConnector + ); + IDS_HDT_CONSOLE (GFX_MISC, " usDeviceTag = 0x%x\n", + DisplayPath->usDeviceTag + ); + IDS_HDT_CONSOLE (GFX_MISC, " usDeviceACPIEnum = 0x%x\n", + DisplayPath->usDeviceACPIEnum + ); + IDS_HDT_CONSOLE (GFX_MISC, " usExtEncoderObjId = 0x%x\n", + DisplayPath->usExtEncoderObjId + ); + IDS_HDT_CONSOLE (GFX_MISC, " ucChannelMapping = 0x%x\n", + DisplayPath->ChannelMapping.ucChannelMapping + ); + IDS_HDT_CONSOLE (GFX_MISC, " ucChPNInvert = 0x%x\n", + DisplayPath->ucChPNInvert + ); + IDS_HDT_CONSOLE (GFX_MISC, " usCaps = 0x%x\n", + DisplayPath->usCaps + ); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h new file mode 100644 index 0000000000..0527f33bb8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h @@ -0,0 +1,91 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Integrated Info Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GFXENUMCONNECTORS_H_ +#define _GFXENUMCONNECTORS_H_ + + +VOID +GfxIntegratedCopyDisplayInfo ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPath, + OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxIntegratedEnumerateAllConnectors ( + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c new file mode 100644 index 0000000000..462fa72c01 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -0,0 +1,1013 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Integrated Info Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbFuseTable.h" +#include "GnbGfxFamServices.h" +#include "GnbCommonLib.h" +#include "GfxPowerPlayTable.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +/// Software state +typedef struct { + BOOLEAN Valid; ///< State valid + UINT16 Classification; ///< State classification + UINT32 CapsAndSettings; ///< State capability and settings + UINT16 Classification2; ///< State classification2 + UINT32 Vclk; ///< UVD VCLK + UINT32 Dclk; ///< UVD DCLK + UINT8 NumberOfDpmStates; ///< Number of DPM states + UINT8 DpmSatesArray[MAX_NUM_OF_DPM_STATES]; ///< DPM state index array +} SW_STATE; + +/// DPM state +typedef struct { + BOOLEAN Valid; ///< State valid + UINT32 Sclk; ///< Sclk in kHz + UINT8 Vid; ///< VID index + UINT16 Tdp; ///< Tdp limit +} DPM_STATE; + +typedef struct { + GFX_PLATFORM_CONFIG *Gfx; + ATOM_PPLIB_POWERPLAYTABLE3 *PpTable; + PP_FUSE_ARRAY *PpFuses; + SW_STATE SwStateArray [MAX_NUM_OF_SW_STATES]; ///< SW state array + DPM_STATE DpmStateArray[MAX_NUM_OF_DPM_STATES]; ///< Sclk DPM state array + UINT8 NumOfClockVoltageLimitEnties; /// + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD VceClockVoltageLimitArray[MAX_NUM_OF_VCE_CLK_STATES]; + UINT8 NumOfVceClockEnties; + VCECLOCKINFO VceClockInfoArray[MAX_NUM_OF_VCE_CLK_STATES]; + UINT8 NumOfVceStateEntries; + ATOM_PPLIB_VCE_STATE_RECORD VceStateArray[MAX_NUM_OF_VCE_STATES]; ///< VCE state array +} PP_WORKSPACE; +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GfxIntegratedDebugDumpPpTable ( + IN ATOM_PPLIB_POWERPLAYTABLE3 *PpTable, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate existing tdp + * + * + * @param[in ] PpFuses Pointer to PP_FUSE_ARRAY + * @param[in] Sclk Sclk in 10kHz + * @param[in] StdHeader Standard configuration header + * @retval Tdp limit in DPM state array + */ + +STATIC UINT16 +GfxPowerPlayLocateTdp ( + IN PP_FUSE_ARRAY *PpFuses, + IN UINT32 Sclk, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Index; + UINT32 DpmIndex; + UINT32 DpmSclk; + UINT32 DeltaSclk; + UINT32 MinDeltaSclk; + + DpmIndex = 0; + MinDeltaSclk = 0xFFFFFFFF; + for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) { + if (PpFuses->SclkDpmDid[Index] != 0) { + DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader); + DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk); + if (DeltaSclk < MinDeltaSclk) { + MinDeltaSclk = MinDeltaSclk; + DpmIndex = Index; + } + } + } + return PpFuses->SclkDpmTdpLimit[DpmIndex]; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create new software state + * + * + * @param[in, out] PpWorkspace PP workspace + * @retval Pointer to state entry in SW state array + */ + +STATIC SW_STATE* +GfxPowerPlayCreateSwState ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + UINTN Index; + for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { + if (PpWorkspace->SwStateArray[Index].Valid == FALSE) { + PpWorkspace->SwStateArray[Index].Valid = TRUE; + return &(PpWorkspace->SwStateArray[Index]); + } + } + return NULL; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create new DPM state + * + * + * @param[in, out] PpWorkspace PP workspace + * @param[in] Sclk SCLK in kHz + * @param[in] Vid Vid index + * @param[in] Tdp Tdp limit + * @retval Index of state entry in DPM state array + */ + +STATIC UINT8 +GfxPowerPlayCreateDpmState ( + IN OUT PP_WORKSPACE *PpWorkspace, + IN UINT32 Sclk, + IN UINT8 Vid, + IN UINT16 Tdp + ) +{ + UINT8 Index; + for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { + if (PpWorkspace->DpmStateArray[Index].Valid == FALSE) { + PpWorkspace->DpmStateArray[Index].Sclk = Sclk; + PpWorkspace->DpmStateArray[Index].Vid = Vid; + PpWorkspace->DpmStateArray[Index].Valid = TRUE; + PpWorkspace->DpmStateArray[Index].Tdp = Tdp; + return Index; + } + } + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate existing or Create new DPM state + * + * + * @param[in, out] PpWorkspace PP workspace + * @param[in] Sclk SCLK in kHz + * @param[in] Vid Vid index + * @param[in] Tdp Tdp limit + * @retval Index of state entry in DPM state array + */ + +STATIC UINT8 +GfxPowerPlayAddDpmState ( + IN OUT PP_WORKSPACE *PpWorkspace, + IN UINT32 Sclk, + IN UINT8 Vid, + IN UINT16 Tdp + ) +{ + UINT8 Index; + for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { + if (PpWorkspace->DpmStateArray[Index].Valid && Sclk == PpWorkspace->DpmStateArray[Index].Sclk && Vid == PpWorkspace->DpmStateArray[Index].Vid) { + return Index; + } + } + return GfxPowerPlayCreateDpmState (PpWorkspace, Sclk, Vid, Tdp); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Add reference to DPM state for SW state + * + * + * @param[in, out] SwStateArray Pointer to SW state array + * @param[in] DpmStateIndex DPM state index + */ + +STATIC VOID +GfxPowerPlayAddDpmStateToSwState ( + IN OUT SW_STATE *SwStateArray, + IN UINT8 DpmStateIndex + ) +{ + SwStateArray->DpmSatesArray[SwStateArray->NumberOfDpmStates++] = DpmStateIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy SW state info to PPTable + * + * + * @param[in, out] PpWorkspace PP workspace + */ +STATIC VOID * +GfxPowerPlayAttachStateInfoBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + UINT8 Index; + UINT8 SwStateIndex; + STATE_ARRAY *StateArray; + ATOM_PPLIB_STATE_V2 *States; + StateArray = (STATE_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + States = &StateArray->States[0]; + SwStateIndex = 0; + for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { + if (PpWorkspace->SwStateArray[Index].Valid && PpWorkspace->SwStateArray[Index].NumberOfDpmStates != 0) { + States->nonClockInfoIndex = SwStateIndex; + States->ucNumDPMLevels = PpWorkspace->SwStateArray[Index].NumberOfDpmStates; + LibAmdMemCopy ( + &States->ClockInfoIndex[0], + PpWorkspace->SwStateArray[Index].DpmSatesArray, + PpWorkspace->SwStateArray[Index].NumberOfDpmStates, + GnbLibGetHeader (PpWorkspace->Gfx) + ); + States = (ATOM_PPLIB_STATE_V2*) ((UINT8*) States + sizeof (ATOM_PPLIB_STATE_V2) + sizeof (UINT8) * (States->ucNumDPMLevels - 1)); + SwStateIndex++; + } + } + StateArray->ucNumEntries = SwStateIndex; + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + (USHORT) ((UINT8 *) States - (UINT8 *) StateArray); + return StateArray; +} +/*----------------------------------------------------------------------------------------*/ +/** + * Copy clock info to PPTable + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachClockInfoBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + CLOCK_INFO_ARRAY *ClockInfoArray; + UINT8 Index; + UINT8 ClkStateIndex; + ClkStateIndex = 0; + ClockInfoArray = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { + if (PpWorkspace->DpmStateArray[Index].Valid == TRUE) { + ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (PpWorkspace->DpmStateArray[Index].Sclk >> 16); + ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (PpWorkspace->DpmStateArray[Index].Sclk); + ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = PpWorkspace->DpmStateArray[Index].Vid; + ClockInfoArray->ClockInfo[ClkStateIndex].tdpLimit = PpWorkspace->DpmStateArray[Index].Tdp; + ClkStateIndex++; + } + } + ClockInfoArray->ucNumEntries = ClkStateIndex; + ClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO); + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO) * ClkStateIndex - sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO); + return ClockInfoArray; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy non clock info to PPTable + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachNonClockInfoBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + NON_CLOCK_INFO_ARRAY *NonClockInfoArray; + UINT8 Index; + UINT8 NonClkStateIndex; + + NonClockInfoArray = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + NonClkStateIndex = 0; + for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { + if (PpWorkspace->SwStateArray[Index].Valid && PpWorkspace->SwStateArray[Index].NumberOfDpmStates != 0) { + NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification = PpWorkspace->SwStateArray[Index].Classification; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulCapsAndSettings = PpWorkspace->SwStateArray[Index].CapsAndSettings; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification2 = PpWorkspace->SwStateArray[Index].Classification2; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulDCLK = PpWorkspace->SwStateArray[Index].Dclk; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulVCLK = PpWorkspace->SwStateArray[Index].Vclk; + NonClkStateIndex++; + } + } + NonClockInfoArray->ucNumEntries = NonClkStateIndex; + NonClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_NONCLOCK_INFO); + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (NON_CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_NONCLOCK_INFO) * NonClkStateIndex - sizeof (ATOM_PPLIB_NONCLOCK_INFO); + return NonClockInfoArray; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if fused state valid + * + * + * @param[out] Index State index + * @param[in] PpFuses Pointer to fuse table + * @param[in] Gfx Gfx configuration info + * @retval TRUE State is valid + */ +STATIC BOOLEAN +GfxPowerPlayIsFusedStateValid ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + BOOLEAN Result; + Result = FALSE; + if (PpFuses->SclkDpmValid[Index] != 0) { + Result = TRUE; + if (PpFuses->PolicyLabel[Index] == POLICY_LABEL_BATTERY && (Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) == 0) { + Result = FALSE; + } + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get SW state calssification from fuses + * + * + * @param[out] Index State index + * @param[in] PpFuses Pointer to fuse table + * @param[in] Gfx Gfx configuration info + * @retval State classification + */ + +STATIC UINT16 +GfxPowerPlayGetClassificationFromFuses ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT16 Classification; + Classification = 0; + switch (PpFuses->PolicyFlags[Index]) { + case 0x1: + Classification |= ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE; + break; + case 0x2: + Classification |= ATOM_PPLIB_CLASSIFICATION_UVDSTATE; + break; + case 0x4: + //Possible SD + HD state + break; + case 0x8: + Classification |= ATOM_PPLIB_CLASSIFICATION_HDSTATE; + break; + case 0x10: + Classification |= ATOM_PPLIB_CLASSIFICATION_SDSTATE; + break; + default: + break; + } + switch (PpFuses->PolicyLabel[Index]) { + case POLICY_LABEL_BATTERY: + Classification |= ATOM_PPLIB_CLASSIFICATION_UI_BATTERY; + break; + case POLICY_LABEL_PERFORMANCE: + Classification |= ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE; + break; + default: + break; + } + return Classification; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get SW state calssification2 from fuses + * + * + * @param[out] Index State index + * @param[in] PpFuses Pointer to fuse table + * @param[in] Gfx Gfx configuration info + * @retval State classification2 + */ + +STATIC UINT16 +GfxPowerPlayGetClassification2FromFuses ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT16 Classification2; + Classification2 = 0; + + switch (PpFuses->PolicyFlags[Index]) { + + case 0x4: + Classification2 |= ATOM_PPLIB_CLASSIFICATION2_MVC; + break; + + default: + break; + } + + return Classification2; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build SCLK state info + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID +GfxPowerPlayBuildSclkStateTable ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + UINT8 ClkStateIndex; + UINT8 DpmFuseIndex; + UINT8 Index; + UINT32 Sclk; + SW_STATE *State; + PP_FUSE_ARRAY *PpFuses; + + PpFuses = PpWorkspace->PpFuses; + // Create States from Fuses + for (Index = 0; Index < MAX_NUM_OF_FUSED_SW_STATES; Index++) { + if (GfxPowerPlayIsFusedStateValid (Index, PpFuses, PpWorkspace->Gfx)) { + //Create new SW State; + State = GfxPowerPlayCreateSwState (PpWorkspace); + State->Classification = GfxPowerPlayGetClassificationFromFuses (Index, PpFuses, PpWorkspace->Gfx); + State->Classification2 = GfxPowerPlayGetClassification2FromFuses (Index, PpFuses, PpWorkspace->Gfx); + if ((State->Classification & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_UVDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) != 0 || + (State->Classification2 & ATOM_PPLIB_CLASSIFICATION2_MVC) != 0) { + State->Vclk = (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]], GnbLibGetHeader (PpWorkspace->Gfx)) : 0; + State->Dclk = (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]], GnbLibGetHeader (PpWorkspace->Gfx)) : 0; + } + if (((State->Classification & 0x7) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) || + ((State->Classification & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) != 0)) { + if (PpWorkspace->Gfx->AbmSupport != 0) { + State->CapsAndSettings |= ATOM_PPLIB_ENABLE_VARIBRIGHT; + } + if (PpWorkspace->Gfx->DynamicRefreshRate != 0) { + State->CapsAndSettings |= ATOM_PPLIB_ENABLE_DRR; + } + } + for (DpmFuseIndex = 0; DpmFuseIndex < MAX_NUM_OF_FUSED_DPM_STATES; DpmFuseIndex++) { + if ((PpFuses->SclkDpmValid[Index] & (1 << DpmFuseIndex)) != 0 ) { + Sclk = (PpFuses->SclkDpmDid[DpmFuseIndex] != 0) ? GfxFmCalculateClock (PpFuses->SclkDpmDid[DpmFuseIndex], GnbLibGetHeader (PpWorkspace->Gfx)) : 0; + if (Sclk != 0) { + ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex], PpFuses->SclkDpmTdpLimit[DpmFuseIndex]); + GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); + } + } + } + } + } + // Create Boot State + State = GfxPowerPlayCreateSwState (PpWorkspace); + State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT; + Sclk = 200 * 100; + ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx))); + GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); + + // Create Thermal State + State = GfxPowerPlayCreateSwState (PpWorkspace); + State->Classification = ATOM_PPLIB_CLASSIFICATION_THERMAL; + Sclk = GfxFmCalculateClock (PpFuses->SclkThermDid, GnbLibGetHeader (PpWorkspace->Gfx)); + ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx))); + GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Add ECLK state + * + * + * @param[in, out] PpWorkspace PP workspace + * @param[in] Eclk SCLK in kHz + * @retval Index of state entry in ECLK clock array + */ + +STATIC UINT8 +GfxPowerPlayAddEclkState ( + IN OUT PP_WORKSPACE *PpWorkspace, + IN UINT32 Eclk + ) +{ + UINT8 Index; + USHORT EclkLow; + UCHAR EclkHigh; + EclkLow = (USHORT) (Eclk & 0xffff); + EclkHigh = (UCHAR) (Eclk >> 16); + for (Index = 0; Index < PpWorkspace->NumOfVceClockEnties; Index++) { + if (PpWorkspace->VceClockInfoArray[Index].ucECClkHigh == EclkHigh && PpWorkspace->VceClockInfoArray[Index].usECClkLow == EclkLow) { + return Index; + } + } + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].ucECClkHigh = EclkHigh; + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].usECClkLow = EclkLow; + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].ucEVClkHigh = EclkHigh; + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].usEVClkLow = EclkLow; + return PpWorkspace->NumOfVceClockEnties++; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Add ECLK state + * + * + * @param[in, out] PpWorkspace PP workspace + * @param[in] EclkIndex ECLK index + * @param[in] Vid Vid index + * @retval Index of state entry in Eclk Voltage record array + */ + +STATIC UINT8 +GfxPowerPlayAddEclkVoltageRecord ( + IN OUT PP_WORKSPACE *PpWorkspace, + IN UINT8 EclkIndex, + IN UINT8 Vid + ) +{ + UINT8 Index; + for (Index = 0; Index < PpWorkspace->NumOfClockVoltageLimitEnties; Index++) { + if (PpWorkspace->VceClockVoltageLimitArray[Index].ucVCEClockInfoIndex == EclkIndex) { + return Index; + } + } + PpWorkspace->VceClockVoltageLimitArray[PpWorkspace->NumOfClockVoltageLimitEnties].ucVCEClockInfoIndex = EclkIndex; + PpWorkspace->VceClockVoltageLimitArray[PpWorkspace->NumOfClockVoltageLimitEnties].usVoltage = Vid; + return PpWorkspace->NumOfClockVoltageLimitEnties++; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach extended header + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachVceTableRevBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + ATOM_PPLIB_VCE_TABLE *VceTable; + VceTable = (ATOM_PPLIB_VCE_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceTable->revid = 0; + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_VCE_TABLE); + return VceTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach extended header + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachExtendedHeaderBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader; + ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + ExtendedHeader->usSize = sizeof (ATOM_PPLIB_EXTENDEDHEADER); + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_EXTENDEDHEADER); + return ExtendedHeader; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach VCE clock info block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachVceClockInfoBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + VCECLOCKINFOARRAY *VceClockInfoArray; + VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceClockInfoArray->ucNumEntries = PpWorkspace->NumOfVceClockEnties; + LibAmdMemCopy ( + &VceClockInfoArray->entries[0], + &PpWorkspace->VceClockInfoArray[0], + VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (VCECLOCKINFOARRAY) + + VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO) - + sizeof (VCECLOCKINFO); + return VceClockInfoArray; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach VCE voltage limit block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachVceVoltageLimitBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *VceClockVoltageLimitTable; + VceClockVoltageLimitTable = (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceClockVoltageLimitTable->numEntries = PpWorkspace->NumOfClockVoltageLimitEnties; + LibAmdMemCopy ( + &VceClockVoltageLimitTable->entries[0], + &PpWorkspace->VceClockVoltageLimitArray[0], + VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE) + + VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD) - + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD); + return VceClockVoltageLimitTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach VCE state block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachVceStateTaleBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + ATOM_PPLIB_VCE_STATE_TABLE *VceStateTable; + VceStateTable = (ATOM_PPLIB_VCE_STATE_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceStateTable->numEntries = PpWorkspace->NumOfVceStateEntries; + LibAmdMemCopy ( + &VceStateTable->entries[0], + &PpWorkspace->VceStateArray[0], + VceStateTable->numEntries * sizeof (ATOM_PPLIB_VCE_STATE_RECORD), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (ATOM_PPLIB_VCE_STATE_TABLE) + + VceStateTable->numEntries * sizeof (ATOM_PPLIB_VCE_STATE_RECORD) - + sizeof (ATOM_PPLIB_VCE_STATE_RECORD); + return VceStateTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build VCE state info + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID +GfxPowerPlayBuildVceStateTable ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + UINT8 Index; + UINT8 VceStateIndex; + UINT8 Vid; + UINT32 Eclk; + UINT32 Sclk; + UINT8 UsedStateBitmap; + UsedStateBitmap = 0; + // build used state + for (Index = 0; Index < (sizeof (PpWorkspace->PpFuses->VceFlags) / sizeof (PpWorkspace->PpFuses->VceFlags[0])) ; Index++) { + UsedStateBitmap |= PpWorkspace->PpFuses->VceFlags[Index]; + for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) { + if ((PpWorkspace->PpFuses->VceFlags[Index] & (1 << VceStateIndex)) != 0) { + Sclk = GfxFmCalculateClock (PpWorkspace->PpFuses->SclkDpmDid[PpWorkspace->PpFuses->VceReqSclkSel[Index]], GnbLibGetHeader (PpWorkspace->Gfx)); + Vid = PpWorkspace->PpFuses->SclkDpmVid[PpWorkspace->PpFuses->VceReqSclkSel[Index]]; + PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, Vid, GfxPowerPlayLocateTdp (PpWorkspace->PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx))); + if (PpWorkspace->PpFuses->VceMclk[Index] == 1) { + PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex |= (PpWorkspace->PpFuses->VceMclk[Index] << 6); + } + Eclk = GfxFmCalculateClock (PpWorkspace->PpFuses->EclkDid[Index], GnbLibGetHeader (PpWorkspace->Gfx)); + PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = GfxPowerPlayAddEclkState (PpWorkspace, Eclk); + GfxPowerPlayAddEclkVoltageRecord (PpWorkspace, PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex, Vid); + PpWorkspace->NumOfVceStateEntries++; + } + } + } + //build unused states + for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) { + if ((UsedStateBitmap & (1 << VceStateIndex)) == 0) { + PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = 0; + PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = GfxPowerPlayAddEclkState (PpWorkspace, 0); + PpWorkspace->NumOfVceStateEntries++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build PP table + * + * + * @param[out] Buffer Buffer to create PP table + * @param[in] Gfx Gfx configuration info + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +GfxPowerPlayBuildTable ( + OUT VOID *Buffer, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + PP_WORKSPACE PpWorkspace; + VOID *BlockPtr; + + LibAmdMemFill (&PpWorkspace, 0x00, sizeof (PP_WORKSPACE), GnbLibGetHeader (Gfx)); + PpWorkspace.PpFuses = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); + ASSERT (PpWorkspace.PpFuses != NULL); + if (PpWorkspace.PpFuses == NULL) { + return AGESA_ERROR; + } + PpWorkspace.PpTable = (ATOM_PPLIB_POWERPLAYTABLE3 *) Buffer; + PpWorkspace.Gfx = Gfx; + //Fill static info + PpWorkspace.PpTable->sHeader.ucTableFormatRevision = 6; + PpWorkspace.PpTable->sHeader.ucTableContentRevision = 1; + PpWorkspace.PpTable->ucDataRevision = PpWorkspace.PpFuses->PPlayTableRev; + PpWorkspace.PpTable->sThermalController.ucType = ATOM_PP_THERMALCONTROLLER_SUMO; + PpWorkspace.PpTable->sThermalController.ucFanParameters = ATOM_PP_FANPARAMETERS_NOFAN; + PpWorkspace.PpTable->sHeader.usStructureSize = sizeof (ATOM_PPLIB_POWERPLAYTABLE3); + PpWorkspace.PpTable->usTableSize = sizeof (ATOM_PPLIB_POWERPLAYTABLE3); + PpWorkspace.PpTable->usFormatID = 7; + if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { + PpWorkspace.PpTable->ulPlatformCaps |= ATOM_PP_PLATFORM_CAP_POWERPLAY; + } + + // Fill Slck SW/DPM state info + GfxPowerPlayBuildSclkStateTable (&PpWorkspace); + // Fill Eclk state info + if (PpWorkspace.PpFuses->VceSateTableSupport) { + GfxPowerPlayBuildVceStateTable (&PpWorkspace); + } + + //Copy state info to actual PP table + BlockPtr = GfxPowerPlayAttachStateInfoBlock (&PpWorkspace); + PpWorkspace.PpTable->usStateArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + BlockPtr = GfxPowerPlayAttachClockInfoBlock (&PpWorkspace); + PpWorkspace.PpTable->usClockInfoArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + BlockPtr = GfxPowerPlayAttachNonClockInfoBlock (&PpWorkspace); + PpWorkspace.PpTable->usNonClockInfoArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + if (PpWorkspace.PpFuses->VceSateTableSupport) { + ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader; + ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) GfxPowerPlayAttachExtendedHeaderBlock (&PpWorkspace); + PpWorkspace.PpTable->usExtendendedHeaderOffset = (USHORT) ((UINT8 *) ExtendedHeader - (UINT8 *) (PpWorkspace.PpTable)); + BlockPtr = GfxPowerPlayAttachVceTableRevBlock (&PpWorkspace); + ExtendedHeader->usVCETableOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + GfxPowerPlayAttachVceClockInfoBlock (&PpWorkspace); + GfxPowerPlayAttachVceVoltageLimitBlock (&PpWorkspace); + GfxPowerPlayAttachVceStateTaleBlock (&PpWorkspace); + + } + GNB_DEBUG_CODE ( + GfxIntegratedDebugDumpPpTable (PpWorkspace.PpTable, Gfx); + ); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump PP table + * + * + * + * @param[in] PpTable Power Play table + * @param[in] Gfx Gfx configuration info + */ + +VOID +GfxIntegratedDebugDumpPpTable ( + IN ATOM_PPLIB_POWERPLAYTABLE3 *PpTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINTN Index; + UINTN DpmIndex; + STATE_ARRAY *StateArray; + ATOM_PPLIB_STATE_V2 *StatesPtr; + NON_CLOCK_INFO_ARRAY *NonClockInfoArrayPtr; + CLOCK_INFO_ARRAY *ClockInfoArrayPtr; + ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader; + ATOM_PPLIB_VCE_STATE_TABLE *VceStateTable; + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *VceClockVoltageLimitTable; + VCECLOCKINFOARRAY *VceClockInfoArray; + UINT8 SclkIndex; + UINT8 EclkIndex; + + IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ > \n"); + IDS_HDT_CONSOLE (GFX_MISC, " Table Revision = %d\n", PpTable->ucDataRevision); + StateArray = (STATE_ARRAY *) ((UINT8 *) PpTable + PpTable->usStateArrayOffset); + StatesPtr = StateArray->States; + NonClockInfoArrayPtr = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usNonClockInfoArrayOffset); + ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset); + IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table ---------> \n"); + for (Index = 0; Index < StateArray->ucNumEntries; Index++) { + IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1 + ); + IDS_HDT_CONSOLE (GFX_MISC, " Classification 0x%x\n", + NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification + ); + IDS_HDT_CONSOLE (GFX_MISC, " Classification2 0x%x\n", + NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification2 + ); + IDS_HDT_CONSOLE (GFX_MISC, " VCLK = %dkHz\n", + NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulVCLK + ); + IDS_HDT_CONSOLE (GFX_MISC, " DCLK = %dkHz\n", + NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulDCLK + ); + IDS_HDT_CONSOLE (GFX_MISC, " DPM State Index: "); + for (DpmIndex = 0; DpmIndex < StatesPtr->ucNumDPMLevels; DpmIndex++) { + IDS_HDT_CONSOLE (GFX_MISC, "%d ", + StatesPtr->ClockInfoIndex [DpmIndex] + ); + } + IDS_HDT_CONSOLE (GFX_MISC, "\n"); + StatesPtr = (ATOM_PPLIB_STATE_V2 *) ((UINT8 *) StatesPtr + sizeof (ATOM_PPLIB_STATE_V2) + StatesPtr->ucNumDPMLevels - 1); + } + IDS_HDT_CONSOLE (GFX_MISC, " < --- SCLK DPM State Table ---> \n"); + for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) { + UINT32 Sclk; + Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16); + IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%d\n", + Index + ); + IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", + ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n", + ClockInfoArrayPtr->ClockInfo[Index].vddcIndex + ); + IDS_HDT_CONSOLE (GFX_MISC, " tdpLimit = %d\n", + ClockInfoArrayPtr->ClockInfo[Index].tdpLimit + ); + } + if (PpTable->usExtendendedHeaderOffset != 0) { + ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) PpTable + PpTable->usExtendendedHeaderOffset); + VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) ExtendedHeader + sizeof (ATOM_PPLIB_EXTENDEDHEADER) + sizeof (ATOM_PPLIB_VCE_TABLE)); + VceClockVoltageLimitTable = (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *) ((UINT8 *) VceClockInfoArray + + sizeof (VCECLOCKINFOARRAY) + + VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO) - + sizeof (VCECLOCKINFO)); + VceStateTable = (ATOM_PPLIB_VCE_STATE_TABLE *) ((UINT8 *) VceClockVoltageLimitTable + + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE) + + VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD) - + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD)); + + IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE State Table [%d]--> \n", VceStateTable->numEntries); + for (Index = 0; Index < VceStateTable->numEntries; Index++) { + SclkIndex = VceStateTable->entries[Index].ucClockInfoIndex & 0x3F; + EclkIndex = VceStateTable->entries[Index].ucVCEClockInfoIndex; + IDS_HDT_CONSOLE (GFX_MISC, " VCE State #%d\n", Index + ); + if ((VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)) == 0) { + IDS_HDT_CONSOLE (GFX_MISC, " Disable\n"); + } else { + IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", + ClockInfoArrayPtr->ClockInfo[SclkIndex].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[SclkIndex].ucEngineClockHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " ECCLK = %d\n", + VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " EVCLK = %d\n", + VceClockInfoArray->entries[EclkIndex].usEVClkLow | (VceClockInfoArray->entries[EclkIndex].ucEVClkHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " MCLK = %d\n", + (VceStateTable->entries[Index].ucClockInfoIndex >> 6 ) & 0x3 + ); + } + } + IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table ---> \n"); + for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) { + EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex; + IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%d\n", Index + ); + IDS_HDT_CONSOLE (GFX_MISC, " ECLK = %d\n", + VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n", + VceClockVoltageLimitTable->entries[Index].usVoltage + ); + } + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h new file mode 100644 index 0000000000..fd19f605d2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h @@ -0,0 +1,278 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Power Play Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GFXPOWERPLAYTABLE_H_ +#define _GFXPOWERPLAYTABLE_H_ + +#pragma pack (push, 1) + +#define POLICY_LABEL_BATTERY 0x1 +#define POLICY_LABEL_PERFORMANCE 0x2 + +#define MAX_NUM_OF_SW_STATES 10 +#define MAX_NUM_OF_DPM_STATES 10 +#define MAX_NUM_OF_VCE_CLK_STATES 5 +#define MAX_NUM_OF_VCE_STATES 6 +#define MAX_NUM_OF_FUSED_DPM_STATES 5 +#define MAX_NUM_OF_FUSED_SW_STATES 6 +/// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps +#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 +#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 +#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 +#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 +#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 +#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 +#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 +#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 +#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 +#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 +#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 +#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 +#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 +#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. +#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). +#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does +#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000ul // Enable the 'regulator hot' feature. +#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000ul // Does the driver supports BACO state. + + +#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 +#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 +#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 + +#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 +#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 +#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 +#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 +#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 +#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 +#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 +#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 +#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 +#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 +#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 +#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 +#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 +#define ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE 0x0000 + +#define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View + +#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000ul +#define ATOM_PPLIB_ENABLE_DRR 0x00080000ul + +#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 +#define ATOM_PP_THERMALCONTROLLER_SUMO 0x0E + +/// DPM state info +typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO { + USHORT usEngineClockLow; ///< Sclk [15:0] (Sclk in 10khz) + UCHAR ucEngineClockHigh; ///< Sclk [23:16](Sclk in 10khz) + UCHAR vddcIndex; ///< 2-bit VDDC index; + USHORT tdpLimit; ///< TDP Limit + USHORT rsv1; ///< Reserved + ULONG rsv2[2]; ///< Reserved +} ATOM_PPLIB_SUMO_CLOCK_INFO; + +/// Non clock info +typedef struct _ATOM_PPLIB_NONCLOCK_INFO { + USHORT usClassification; ///< State classification see ATOM_PPLIB_CLASSIFICATION_* + UCHAR ucMinTemperature; ///< Reserved + UCHAR ucMaxTemperature; ///< Reserved + ULONG ulCapsAndSettings; ///< Capability Setting (ATOM_PPLIB_ENABLE_DRR or ATOM_PPLIB_ENABLE_VARIBRIGHT or 0) + UCHAR ucRequiredPower; ///< Reserved + USHORT usClassification2; ///< Reserved + ULONG ulVCLK; ///< UVD clocks VCLK unit is in 10KHz + ULONG ulDCLK; ///< UVD clocks DCLK unit is in 10KHz + UCHAR ucUnused[5]; ///< Reserved +} ATOM_PPLIB_NONCLOCK_INFO; + +/// Thermal controller info stub +typedef struct _ATOM_PPLIB_THERMALCONTROLLER { + UCHAR ucType; ///< Reserved. Should be set 0xE + UCHAR ucI2cLine; ///< Reserved. Should be set 0 + UCHAR ucI2cAddress; ///< Reserved. Should be set 0 + UCHAR ucFanParameters; ///< Reserved. Should be set 0x80 + UCHAR ucFanMinRPM; ///< Reserved. Should be set 0 + UCHAR ucFanMaxRPM; ///< Reserved. Should be set 0 + UCHAR ucReserved; ///< Reserved. Should be set 0 + UCHAR ucFlags; ///< Reserved. Should be set 0 +} ATOM_PPLIB_THERMALCONTROLLER; + +/// SW state info +typedef struct _ATOM_PPLIB_STATE_V2 { + UCHAR ucNumDPMLevels; ///< Number of valid DPM levels in this state + UCHAR nonClockInfoIndex; ///< Index to the array of NonClockInfos + UCHAR ClockInfoIndex[1]; ///< Array of DPM states. Actual number calculated during state enumeration +} ATOM_PPLIB_STATE_V2; + +/// SW state Array +typedef struct { + UCHAR ucNumEntries; ///< Number of SW states + ATOM_PPLIB_STATE_V2 States[1]; ///< SW state info. Actual number calculated during state enumeration +} STATE_ARRAY; + +/// Clock info Array +typedef struct { + UCHAR ucNumEntries; ///< Number of ClockInfo entries + UCHAR ucEntrySize; ///< size of ATOM_PPLIB_SUMO_CLOCK_INFO + ATOM_PPLIB_SUMO_CLOCK_INFO ClockInfo[1]; ///< Clock info array. Size will be determined dynamically base on fuses +} CLOCK_INFO_ARRAY; + +/// Non clock info Array +typedef struct { + + UCHAR ucNumEntries; ///< Number of Entries; + UCHAR ucEntrySize; ///< Size of NonClockInfo + ATOM_PPLIB_NONCLOCK_INFO NonClockInfo[1]; ///< Non clock info array +} NON_CLOCK_INFO_ARRAY; + +/// VCE clock info +typedef struct { + USHORT usEVClkLow; ///< EVCLK low + UCHAR ucEVClkHigh; ///< EVCLK high + USHORT usECClkLow; ///< ECCLK low + UCHAR ucECClkHigh; ///< ECCLK high +} VCECLOCKINFO; + +/// VCE clock info array +typedef struct { + UCHAR ucNumEntries; ///< Number of entries + VCECLOCKINFO entries[1]; ///< VCE clock arrau +} VCECLOCKINFOARRAY; + +/// VCE voltage limit record +typedef struct { + USHORT usVoltage; ///< Voltage index + UCHAR ucVCEClockInfoIndex; ///< Index of VCE clock state +} ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD; + +/// VCE voltage limit table +typedef struct { + UCHAR numEntries; ///< Number of entries + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD entries[1]; ///< Coltage limit state array +} ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE; + +/// VCE state record +typedef struct { + UCHAR ucVCEClockInfoIndex; ///< Index of VCE clock state + UCHAR ucClockInfoIndex; ///< Index of SCLK clock state +} ATOM_PPLIB_VCE_STATE_RECORD; + +/// VCE state table +typedef struct { + UCHAR numEntries; ///< Number of state entries + ATOM_PPLIB_VCE_STATE_RECORD entries[1]; ///< State entries +} ATOM_PPLIB_VCE_STATE_TABLE; + +/// Extended header +typedef struct { + USHORT usSize; ///< size of header + ULONG rsv15; ///< reserved + ULONG rsv16; ///< reserved + USHORT usVCETableOffset; ///< offset of ATOM_PPLIB_VCE_TABLE +} ATOM_PPLIB_EXTENDEDHEADER; + +/// VCE table +typedef struct { + UCHAR revid; ///< revision ID +} ATOM_PPLIB_VCE_TABLE; + +/// Power Play table +typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 { + ATOM_COMMON_TABLE_HEADER sHeader; ///< Common header + UCHAR ucDataRevision; ///< Revision of PP table + UCHAR Reserved1[4]; ///< Reserved + USHORT usStateArrayOffset; ///< Offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures + USHORT usClockInfoArrayOffset; ///< Offset from start of the table to ClockInfoArray + USHORT usNonClockInfoArrayOffset; ///< Offset from Start of the table to NonClockInfoArray + USHORT Reserved2[2]; ///< Reserved + USHORT usTableSize; ///< the size of this structure, or the extended structure + ULONG ulPlatformCaps; ///< See ATOM_PPLIB_CAPS_* + ATOM_PPLIB_THERMALCONTROLLER sThermalController; ///< Thermal controller stub. + USHORT Reserved4[2]; ///< Reserved + UCHAR Reserved5; ///< Reserved + USHORT Reserved6; ///< Reserved + USHORT usFormatID; ///< Format ID + USHORT Reserved7[1]; ///< Reserved + USHORT usExtendendedHeaderOffset; ///< Extended header offset +} ATOM_PPLIB_POWERPLAYTABLE3; + +#pragma pack (pop) + + +AGESA_STATUS +GfxPowerPlayBuildTable ( + OUT VOID *Buffer, + IN GFX_PLATFORM_CONFIG *Gfx + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c new file mode 100644 index 0000000000..a01e6e7790 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c @@ -0,0 +1,225 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to collect discrete GFX card info + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbGfxInitLibV1.h" +#include "GfxCardInfo.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if GFX controller fused off + * + * + * @param[in] StdHeader Standard configuration header + * @retval TRUE Gfx controller present and available + */ +BOOLEAN +GfxLibIsControllerPresent ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 1, 0, 0), StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init Gfx SSID Registers + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxInitSsid ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + UINT32 TempData; + PCI_ADDR IgpuAddress; + PCI_ADDR HdaudioAddress; + + Status = AGESA_SUCCESS; + TempData = 0; + + IgpuAddress = Gfx->GfxPciAddress; + HdaudioAddress = Gfx->GfxPciAddress; + HdaudioAddress.Address.Function = 1; + + // Set SSID for internal GPU + if (UserOptions.CfgGnbIGPUSSID != 0) { + GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbIGPUSSID, GnbLibGetHeader (Gfx)); + } else { + GnbLibPciRead (IgpuAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); + GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); + } + + // Set SSID for internal HD Audio + if (UserOptions.CfgGnbHDAudioSSID != 0) { + GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbHDAudioSSID, GnbLibGetHeader (Gfx)); + } else { + GnbLibPciRead (HdaudioAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); + GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); + } + + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy memory content to FB + * + * + * @param[in] Source Pointer to source + * @param[in] FbOffset FB offset + * @param[in] Length The length to copy + * @param[in] Gfx Pointer to global GFX configuration + * + */ +VOID +GfxLibCopyMemToFb ( + IN VOID *Source, + IN UINT32 FbOffset, + IN UINT32 Length, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GMMx00_STRUCT GMMx00; + GMMx04_STRUCT GMMx04; + UINT32 Index; + for (Index = 0; Index < Length; Index = Index + 4 ) { + GMMx00.Value = 0x80000000 | (FbOffset + Index); + GMMx04.Value = *(UINT32*) ((UINT8*)Source + Index); + GnbLibMemWrite (Gfx->GmmBase + GMMx00_ADDRESS, AccessWidth32, &GMMx00.Value, GnbLibGetHeader (Gfx)); + GnbLibMemWrite (Gfx->GmmBase + GMMx04_ADDRESS, AccessWidth32, &GMMx04.Value, GnbLibGetHeader (Gfx)); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set iGpu VGA mode + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ +VOID +GfxLibSetiGpuVgaMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GnbLibPciIndirectRMW ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + (UINT32) ~D0F0x64_x1D_VgaEn_MASK, + ((Gfx->iGpuVgaMode == iGpuVgaAdapter) ? 1 : 0) << D0F0x64_x1D_VgaEn_OFFSET, + GnbLibGetHeader (Gfx) + ); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h new file mode 100644 index 0000000000..eb68a44d85 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Gfx Library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +#ifndef _GNBGFXINITLIBV1_H_ +#define _GNBGFXINITLIBV1_H_ + +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GfxEnumConnectors.h" +#include "GfxPowerPlayTable.h" +#include "GfxCardInfo.h" + +BOOLEAN +GfxLibIsControllerPresent ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GfxInitSsid ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + + +VOID +GfxLibCopyMemToFb ( + IN VOID *Source, + IN UINT32 FbOffset, + IN UINT32 Length, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxLibSetiGpuVgaMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c new file mode 100644 index 0000000000..037eadd02a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c @@ -0,0 +1,493 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbGfxInitLibV1.h" +#include "GnbGfxConfig.h" +#include "GnbGfxFamServices.h" +#include "GfxLibTN.h" +#include "GnbRegistersTN.h" +#include "GnbInitTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbHandleLib.h" +#include "GnbTimerLib.h" +#include "cpuFamilyTranslation.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_TABLE ROMDATA GfxEnvInitTableTN[]; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Shut Down Disabled SIMDs + * + * @param[in] Property GNB property + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxShutDownDisabledSimdsTN ( + IN UINT32 Property, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + ex1006_STRUCT ex1006 ; + ex1009_STRUCT ex1009; + D0F0xBC_xE03002F8_STRUCT D0F0xBC_xE03002F8; + D0F0xBC_xE03002FC_STRUCT D0F0xBC_xE03002FC; + D0F0xBC_xE0300054_STRUCT GfxChainPgfsmConfig; + UINT8 n; + UINT32 Mask; + CPU_LOGICAL_ID LogicalId; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledSimdsTN Enter\n"); + + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Gfx)); + + GfxChainPgfsmConfig.Value = 0; + GfxChainPgfsmConfig.Field.PowerDown = 1; + GfxChainPgfsmConfig.Field.P2Select = 1; + GfxChainPgfsmConfig.Field.FsmAddr = 0xFF; + + //Step 1: Read fuse to see which SIMD(s) have been disabled + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe000101c , &ex1006.Value, 0, GnbLibGetHeader (Gfx)); + + //Step 2: Check which SIMD has been disabled + for (n = 0; n < 6; n++) { + if (((Property & TABLE_PROPERTY_IGFX_DISABLED) != 0) || ((ex1006.Field.ex1006_0 >> n) & 0x1)) { + IDS_HDT_CONSOLE (GNB_TRACE, "Disable SIMD %d\n", n); + //Step 3: Make sure PGFSM has been programmed in GFX Power Island. + //Step 4: Make sure SCLK frequency is below 400Mhz + //Step 5: Enable PGFSM clock + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx)); + ex1009.Value |= (0x1 << (0 + n)); + GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + //Step 6 + GnbRegisterWriteTN (TYPE_D0F0xBC, (D0F0xBC_xE0300054_ADDRESS + (n * 0x1C)), &GfxChainPgfsmConfig.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + //Step 7 + Mask = (UINT32) (0x1F << (n * 5)); + do { + GnbRegisterReadTN (D0F0xBC_xE03002F8_TYPE, D0F0xBC_xE03002F8_ADDRESS, &D0F0xBC_xE03002F8.Value, 0, GnbLibGetHeader (Gfx)); + } while ((D0F0xBC_xE03002F8.Value & Mask )!= 0); + //Step 8: Restore previous SCLK divider + if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) { + do { + GnbRegisterReadTN (D0F0xBC_xE03002FC_TYPE, D0F0xBC_xE03002FC_ADDRESS, &D0F0xBC_xE03002FC.Value, 0, GnbLibGetHeader (Gfx)); + } while ((D0F0xBC_xE03002FC.Value & Mask )!= Mask); + } else { + } + //Step 10: Turn off PGFSM clock + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx)); + ex1009.Value &= (~ (UINT64) (0x1 << (0 + n))); + GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledSimdsTN Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Shut Down Disabled SIMDs + * + * + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxShutDownDisabledRbsTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + ex1006_STRUCT ex1006 ; + D0F0xBC_xE0003024_STRUCT D0F0xBC_xE0003024; + D0F0xBC_xE03000FC_STRUCT D0F0xBC_xE03000FC; + D0F0xBC_xE0300100_STRUCT D0F0xBC_xE0300100; + ex1009_STRUCT ex1009 ; + D0F0xBC_xE03002F4_STRUCT D0F0xBC_xE03002F4; + D0F0xBC_xE03002E4_STRUCT D0F0xBC_xE03002E4; + UINT8 i; + UINT8 RbNumber; + UINT32 Mask1; + UINT32 Mask2; + + D0F0xBC_xE03000FC.Value = 0; + D0F0xBC_xE03000FC.Field.WriteOp = 1; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledRbsTN Enter\n"); + + //Step 1: Read fuse to see which SIMD(s) have been disabled + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe000101c , &ex1006.Value, 0, GnbLibGetHeader (Gfx)); + + //Step 2: Power down disabled RB + if (ex1006.Field.ex1006_1 == 0x1) { + RbNumber = 0; + Mask1 = 0x3FFFA; + Mask2 = 0x5; + } else if (ex1006.Field.ex1006_1 == 0x2) { + RbNumber = 1; + Mask1 = 0x3FFF5; + Mask2 = 0xA; + } else { + return AGESA_SUCCESS; + } + //Step 3: Enable PGFSM commands during reset + GnbRegisterReadTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, 0, GnbLibGetHeader (Gfx)); + D0F0xBC_xE0003024.Value |= 0x1; + GnbRegisterWriteTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + //Step 4: Make sure PGFSM has been programmed before sending power down command. + //CB0 = 0, DB0 = 2, CB1 = 1, DB1 = 3 + for (i = RbNumber; i < 4; i += 2) { + D0F0xBC_xE0300100.Value = (5 << 16 ) | (4 << 8 ) | (10 << 0 ); //reg0 + GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + D0F0xBC_xE03000FC.Field.FsmAddr = i; + D0F0xBC_xE03000FC.Field.RegAddr = 2 ; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + + D0F0xBC_xE0300100.Value = (50 << 0 ) | (50 << 12 ); //reg1 + GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + D0F0xBC_xE03000FC.Field.RegAddr = 3 ; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + + D0F0xBC_xE0300100.Value = 0; //control + GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + D0F0xBC_xE03000FC.Field.RegAddr = 1 ; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + } + //Step 5: Make sure SCLK frequency is below 400Mhz + //Step 6: Enable PGFSM clock + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx)); + ex1009.Field.ex1009_1 = 1; + GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + //Step 7 + D0F0xBC_xE03000FC.Value = 0; + D0F0xBC_xE03000FC.Field.PowerDown = 1; + D0F0xBC_xE03000FC.Field.P1Select = 1; + D0F0xBC_xE03000FC.Field.P2Select = 1; + D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + + //Step 8 + D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber + 1; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + + //Step 9: Wait for isolation to be asserted for RB0/RB1 + do { + GnbRegisterReadTN (D0F0xBC_xE03002F4_TYPE, D0F0xBC_xE03002F4_ADDRESS, &D0F0xBC_xE03002F4.Value, 0, GnbLibGetHeader (Gfx)); + } while ((D0F0xBC_xE03002F4.Value & Mask1 )!= 0); + //Step 10: Restore previous SCLK divider + //Step 11: Wait for PSO daughter to be asserted for RB0/RB1 + do { + GnbRegisterReadTN (D0F0xBC_xE03002E4_TYPE, D0F0xBC_xE03002E4_ADDRESS, &D0F0xBC_xE03002E4.Value, 0, GnbLibGetHeader (Gfx)); + } while ((D0F0xBC_xE03002E4.Value & Mask2 )!= Mask2); + + //Step 12: Set PGFSM power up override bits so SMU will not power up disabled RB + D0F0xBC_xE0300100.Value = 0x3 << 11; + D0F0xBC_xE03000FC.Value = 0; + D0F0xBC_xE03000FC.Field.RegAddr = 1 ; + GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber + 1; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + + //Step 13: Turn off PGFSM clock + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx)); + ex1009.Field.ex1009_1 = 1; + GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + //Step 14: Disable PGFSM commands during reset + GnbRegisterReadTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, 0, GnbLibGetHeader (Gfx)); + D0F0xBC_xE0003024.Value &= 0xFFFFFFFE; + GnbRegisterWriteTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledRbsTN Exit\n"); + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GFX straps. + * + * + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxEnvInitTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D0F0x64_x1C_STRUCT D0F0x64_x1C; + D0F0x64_x1D_STRUCT D0F0x64_x1D; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInitTN Enter\n"); + + GnbLibPciIndirectRead ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, + AccessWidth32, + &D0F0x64_x1C.Value, + GnbLibGetHeader (Gfx) + ); + + GnbLibPciIndirectRead ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, + AccessWidth32, + &D0F0x64_x1D.Value, + GnbLibGetHeader (Gfx) + ); + + D0F0x64_x1C.Field.AudioNonlegacyDeviceTypeEn = 0x0; + D0F0x64_x1C.Field.F0NonlegacyDeviceTypeEn = 0x0; + + D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x1; + D0F0x64_x1C.Field.RcieEn = 0x1; + + D0F0x64_x1D.Field.VgaEn = 0x1; + + D0F0x64_x1C.Field.AudioEn = Gfx->GnbHdAudio; + D0F0x64_x1C.Field.F0En = 0x1; + D0F0x64_x1C.Field.RegApSize = 0x1; + + if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) { + D0F0x64_x1C.Field.MemApSize = 0x1; + } else if (Gfx->UmaInfo.UmaSize > 64 * 0x100000) { + D0F0x64_x1C.Field.MemApSize = 0x0; + } else if (Gfx->UmaInfo.UmaSize > 32 * 0x100000) { + D0F0x64_x1C.Field.MemApSize = 0x2; + } else { + D0F0x64_x1C.Field.MemApSize = 0x3; + } + GnbLibPciIndirectWrite ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &D0F0x64_x1D.Value, + GnbLibGetHeader (Gfx) + ); + + GnbLibPciIndirectWrite ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &D0F0x64_x1C.Value, + GnbLibGetHeader (Gfx) + ); + + D0F0x64_x1C.Field.WriteDis = 0x1; + + GnbLibPciIndirectWrite ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &D0F0x64_x1C.Value, + GnbLibGetHeader (Gfx) + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInitTN Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Env Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + + +AGESA_STATUS +GfxEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GFX_PLATFORM_CONFIG *Gfx; + GNB_HANDLE *GnbHandle; + UINT32 Property; + BOOLEAN ShutDownDisabledSimd; + BOOLEAN ShutDownDisabledRb; + UINT8 SclkDid; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Property = TABLE_PROPERTY_DEAFULT; + ShutDownDisabledSimd = GnbBuildOptions.CfgUnusedSimdPowerGatingEnable; + ShutDownDisabledRb = GnbBuildOptions.CfgUnusedRbPowerGatingEnable; + + Status = GfxLocateConfigData (StdHeader, &Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + if (Gfx->UmaInfo.UmaMode != UMA_NONE) { + Status = GfxEnvInitTN (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + } else { + GfxFmDisableController (StdHeader); + Property |= TABLE_PROPERTY_IGFX_DISABLED; + } + } else { + GfxFmDisableController (StdHeader); + Property |= TABLE_PROPERTY_IGFX_DISABLED; + } + // + // Set sclk to 100Mhz + // + SclkDid = GfxRequestSclkTNS3Save ( + GfxLibCalculateDidTN (98 * 100, StdHeader), + StdHeader + ); + + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + Status = GnbProcessTable ( + GnbHandle, + GfxEnvInitTableTN, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + if (ShutDownDisabledSimd == TRUE) { + GfxShutDownDisabledSimdsTN (Property, Gfx); + } + + if ((Property & TABLE_PROPERTY_IGFX_DISABLED) != 0) { + if (ShutDownDisabledRb == TRUE) { + GfxShutDownDisabledRbsTN (Gfx); + } + } + // + // Restore Sclk + // + GfxRequestSclkTNS3Save ( + SclkDid, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceTN Exit [0x%x]\n", AgesaStatus); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c new file mode 100644 index 0000000000..1cd96d3d83 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c @@ -0,0 +1,595 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 64152 $ @e \$Date: 2012-01-16 21:38:07 -0600 (Mon, 16 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbRegisterAccTN.h" +#include "cpuFamilyTranslation.h" +#include "GnbRegistersTN.h" +#include "GfxLibTN.h" +#include "GfxGmcInitTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN []; +extern GNB_TABLE ROMDATA GfxGmcInitTableTN []; +extern GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN []; + + +#define GNB_GFX_DRAM_CH_0_PRESENT 1 +#define GNB_GFX_DRAM_CH_1_PRESENT 2 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +DCT_REGISTER_ENTRY DctRegisterTable [] = { + { + TYPE_D18F2_dct0, + D18F2x94_dct0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct0) + }, + { + TYPE_D18F2_dct1, + D18F2x94_dct1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct1) + }, + { + TYPE_D18F2_dct0, + D18F2x2E0_dct0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct0) + }, + { + TYPE_D18F2_dct1, + D18F2x2E0_dct1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct1) + }, + { + TYPE_D18F2_dct0_mp0, + D18F2x200_dct0_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp0) + }, + { + TYPE_D18F2_dct0_mp1, + D18F2x200_dct0_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp1) + }, + { + TYPE_D18F2_dct1_mp0, + D18F2x200_dct1_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp0) + }, + { + TYPE_D18F2_dct1_mp1, + D18F2x200_dct1_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp1) + }, + { + TYPE_D18F2_dct0_mp0, + D18F2x204_dct0_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp0) + }, + { + TYPE_D18F2_dct0_mp1, + D18F2x204_dct0_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp1) + }, + { + TYPE_D18F2_dct1_mp0, + D18F2x204_dct1_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp0) + }, + { + TYPE_D18F2_dct1_mp1, + D18F2x204_dct1_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp1) + }, + { + TYPE_D18F2_dct0_mp0, + D18F2x22C_dct0_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp0) + }, + { + TYPE_D18F2_dct0_mp1, + D18F2x22C_dct0_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp1) + }, + { + TYPE_D18F2_dct1_mp0, + D18F2x22C_dct1_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp0) + }, + { + TYPE_D18F2_dct1_mp1, + D18F2x22C_dct1_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp1) + }, + { + TYPE_D18F2_dct0_mp0, + D18F2x21C_dct0_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp0) + }, + { + TYPE_D18F2_dct0_mp1, + D18F2x21C_dct0_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp1) + }, + { + TYPE_D18F2_dct1_mp0, + D18F2x21C_dct1_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp0) + }, + { + TYPE_D18F2_dct1_mp1, + D18F2x21C_dct1_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp1) + }, + { + TYPE_D18F2_dct0_mp0, + D18F2x20C_dct0_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp0) + }, + { + TYPE_D18F2_dct0_mp1, + D18F2x20C_dct0_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp1) + }, + { + TYPE_D18F2_dct1_mp0, + D18F2x20C_dct1_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp0) + }, + { + TYPE_D18F2_dct1_mp1, + D18F2x20C_dct1_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp1) + } +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize Fb location + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeFbLocationTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GMMx2024_STRUCT GMMx2024; + GMMx2068_STRUCT GMMx2068; + GMMx2C04_STRUCT GMMx2C04; + GMMx5428_STRUCT GMMx5428; + UINT64 FBBase; + UINT64 FBTop; + FBBase = 0x0F00000000; + FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1; + GMMx2024.Value = 0; + GMMx2C04.Value = 0; + GMMx2024.Field.FB_BASE = (UINT16) (FBBase >> 24); + GMMx2024.Field.FB_TOP = (UINT16) (FBTop >> 24); + GMMx2068.Field.FB_OFFSET = (UINT32) (Gfx->UmaInfo.UmaBase >> 22); + GMMx2C04.Field.NONSURF_BASE = (UINT32) (FBBase >> 8); + GMMx5428.Field.CONFIG_MEMSIZE = Gfx->UmaInfo.UmaSize >> 20; + GnbRegisterWriteTN (GMMx2024_TYPE, GMMx2024_ADDRESS, &GMMx2024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (GMMx2068_TYPE, GMMx2068_ADDRESS, &GMMx2068.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (GMMx2C04_TYPE, GMMx2C04_ADDRESS, &GMMx2C04.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (GMMx5428_TYPE, GMMx5428_ADDRESS, &GMMx5428.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Sequencer model info + * + * + * @param[out] DctChannelInfo Various DCT/GMM info + * @param[in] Gfx Pointer to global GFX configuration + */ + +STATIC VOID +GfxGmcDctMemoryChannelInfoTN ( + OUT DCT_CHANNEL_INFO *DctChannelInfo, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + + UINT32 Index; + UINT32 Value; + + for (Index = 0; Index < (sizeof (DctRegisterTable) / sizeof (DCT_REGISTER_ENTRY)); Index++) { + GnbRegisterReadTN ( + DctRegisterTable[Index].RegisterSpaceType, + DctRegisterTable[Index].Address, + &Value, + 0, + GnbLibGetHeader (Gfx) + ); + *(UINT32 *)((UINT8 *) DctChannelInfo + DctRegisterTable[Index].DctChannelInfoTableOffset) = Value; + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize sequencer model + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeSequencerTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + + UINT32 memps0_freq; + UINT32 memps1_freq; + UINT32 scale_mp0; + UINT32 scale_mp1; + UINT8 DramChannelPresent; + ex1047_STRUCT ex1047 ; + ex1048_STRUCT ex1048 ; + ex1060_STRUCT ex1060 ; + ex1061_STRUCT ex1061 ; + ex1062_STRUCT ex1062 ; + DCT_CHANNEL_INFO DctChannel; + D18F5x170_STRUCT D18F5x170; + ex1012_STRUCT ex1012 ; + ex1034_STRUCT ex1034 ; + + GfxGmcDctMemoryChannelInfoTN (&DctChannel, Gfx); + + DramChannelPresent = 0; + if (!DctChannel.D18F2x94_dct1.Field.DisDramInterface) { + DramChannelPresent |= GNB_GFX_DRAM_CH_1_PRESENT; + } + + if (!DctChannel.D18F2x94_dct0.Field.DisDramInterface) { + //if (channel 0 present) + //memps0_freq = extract frequency from DRAM Configuration High [4:0] encoding + //memps1_freq = extract frequency from Memory P-state Control Status [28:24] encoding + DramChannelPresent |= GNB_GFX_DRAM_CH_0_PRESENT; + memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct0.Field.MemClkFreq, GnbLibGetHeader (Gfx)); + memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx)); + } else { + //memps0_freq = extract frequency from DRAM Configuration High [4:0] encoding + //memps1_freq = extract frequency from Memory P-state Control Status [28:24] encoding + memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct1.Field.MemClkFreq, GnbLibGetHeader (Gfx)); + memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct1.Field.M1MemClkFreq, GnbLibGetHeader (Gfx)); + } + + GnbRegisterReadTN (D18F5x170_TYPE, D18F5x170_ADDRESS, &D18F5x170.Value, 0, GnbLibGetHeader (Gfx)); + if (D18F5x170.Field.MemPstateDis == 1) { + memps1_freq = memps0_freq; + } + + //scale_mp0 = sclk_max_freq / memps0_freq + //scale_mp1 = sclk_max_freq / memps1_freq + //Multiply it by 100 to avoid dealing with floating point values + scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq; + scale_mp1 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps1_freq; + + GnbRegisterReadTN (TYPE_GMM , 0x2774 , &ex1047.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadTN (TYPE_GMM , 0x2778 , &ex1048.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadTN (TYPE_GMM , 0x27f0 , &ex1060.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadTN (TYPE_GMM , 0x27fc , &ex1061.Value, 0, GnbLibGetHeader (Gfx)); + + if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) { + ex1047.Field.ex1047_0 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trcd, DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100; + ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0; + ex1047.Field.ex1047_2 = (MIN ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd), + (DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd)) * scale_mp0) / 100; + ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2; + + ex1048.Field.ex1048_0 = (MIN (DctChannel.D18F2x204_dct0_mp0.Field.Trc, DctChannel.D18F2x204_dct1_mp0.Field.Trc) * scale_mp0) / 100; + ex1048.Field.ex1048_1 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trp, DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100; + ex1048.Field.ex1048_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp), + (DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp)) * scale_mp0) / 100; + ex1048.Field.ex1048_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO), + (DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO)) / 2) * scale_mp0) / 100; + + ex1060.Field.ex1060_0 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trcd, DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100; + ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0; + ex1060.Field.ex1060_2 = (MIN ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd), + (DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd)) * scale_mp1) / 100; + ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2; + + ex1061.Field.ex1061_0 = (MIN (DctChannel.D18F2x204_dct0_mp1.Field.Trc, DctChannel.D18F2x204_dct1_mp1.Field.Trc) * scale_mp1) / 100; + ex1061.Field.ex1061_1 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trp, DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100; + ex1061.Field.ex1061_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp), + (DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp)) * scale_mp1) / 100; + ex1061.Field.ex1061_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO), + (DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO)) / 2) * scale_mp1) / 100; + + } else if ((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) { + ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct0_mp0.Field.Trcd * scale_mp0) / 100; + ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0; + ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd) * scale_mp0) / 100; + ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2; + + ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct0_mp0.Field.Trc * scale_mp0) / 100; + ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct0_mp0.Field.Trp * scale_mp0) / 100; + ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp) * scale_mp0) / 100; + ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100; + + ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct0_mp1.Field.Trcd * scale_mp1) / 100; + ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0; + ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd) * scale_mp1) / 100; + ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2; + + ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct0_mp1.Field.Trc * scale_mp1) / 100; + ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct0_mp1.Field.Trp * scale_mp1) / 100; + ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp) * scale_mp1) / 100; + ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100; + + } else { + ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct1_mp0.Field.Trcd * scale_mp0) / 100; + ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0; + ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100; + ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2; + + ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct1_mp0.Field.Trc * scale_mp0) / 100; + ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct1_mp0.Field.Trp * scale_mp0) / 100; + ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100; + ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100; + + ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct1_mp1.Field.Trcd * scale_mp1) / 100; + ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0; + ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100; + ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2; + + ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct1_mp1.Field.Trc * scale_mp1) / 100; + ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct1_mp1.Field.Trp * scale_mp1) / 100; + ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100; + ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100; + } + + GnbRegisterWriteTN (TYPE_GMM , 0x2774 , &ex1047.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (TYPE_GMM , 0x2778 , &ex1048.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (TYPE_GMM , 0x27f0 , &ex1060.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (TYPE_GMM , 0x27fc , &ex1061.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + ex1062.Field.ex1062_0 = GfxLibGetNumberOfSclkPerDramBurst (scale_mp0, GnbLibGetHeader (Gfx)); + ex1062.Field.ex1062_1 = GfxLibGetNumberOfSclkPerDramBurst (scale_mp1, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (TYPE_GMM , 0x2808 , &ex1062.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + + //MC Performance settings base on memory channel configuration + //If 1 channel + ex1012.Value = 0x210; + ex1034.Value = 0x3; + if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) { + //If 2 channels + ex1012.Value = 0x1210; + ex1034.Value = 0xC3; + } + GnbRegisterWriteTN (TYPE_GMM , 0x2004 , &ex1012.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (TYPE_GMM , 0x2214 , &ex1034.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +STATIC VOID +GfxGmcSecureGarlicAccessTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + ex1064_STRUCT ex1064 ; + ex1065_STRUCT ex1065 ; + GMMx287C_STRUCT GMMx287C; + + ex1064.Value = (UINT32) (Gfx->UmaInfo.UmaBase >> 20); + GnbRegisterWriteTN (TYPE_GMM , 0x2868 , &ex1064.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + ex1065.Value = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1); + GnbRegisterWriteTN (TYPE_GMM , 0x286c , &ex1065.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + // Areag FB - 32K reserved by VBIOS for SBIOS to use + GMMx287C.Value = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 32 * 1024) >> 12); + GnbRegisterWriteTN (GMMx287C_TYPE, GMMx287C_ADDRESS, &GMMx287C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize C6 aperture location + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeC6LocationTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F2x118_STRUCT D18F2x118; + D18F1x44_STRUCT D18F1x44; + GMMx2870_STRUCT GMMx2870; + GMMx2874_STRUCT GMMx2874; + + // From D18F1x[144:140,44:40] DRAM Base/Limit, + // {DramBase[47:24], 00_0000h} <= address[47:0] <= {DramLimit[47:24], FF_FFFFh}. + GnbRegisterReadTN (D18F1x44_TYPE, D18F1x44_ADDRESS, &D18F1x44.Value, 0, GnbLibGetHeader (Gfx)); + // + // base 39:20, base = Dram Limit + 1 + // ex: system 256 MB on Node 0, D18F1x44.Field.DramLimit_39_24_ = 0xE (240MB -1) + // Node DRAM D18F1x[144:140,44:40] CC6DRAMRange D18F4x128 D18F1x120 D18F1x124 + // 0 256MB 0MB ~ 240 MB - 1 240 MB ~ 256 MB - 1 0 0 MB, 256 MB - 1 + // + + // base 39:20 + GMMx2870.Value = ((D18F1x44.Field.DramLimit_39_24_ + 1) << 4); + // top 39:20 + GMMx2874.Value = (((D18F1x44.Field.DramLimit_39_24_ + 1) << 24) + (16 * 0x100000) - 1) >> 20; + + // Check C6 enable, D18F2x118[CC6SaveEn] + GnbRegisterReadTN (TYPE_D18F2 , 0x118 , &D18F2x118.Value, 0, GnbLibGetHeader (Gfx)); + + if (D18F2x118.Field.CC6SaveEn) { + + GnbRegisterWriteTN (GMMx2874_TYPE, GMMx2874_ADDRESS, &GMMx2874.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (GMMx2870_TYPE, GMMx2870_ADDRESS, &GMMx2870.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GMC + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ + +AGESA_STATUS +GfxGmcInitTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GMMx28D8_STRUCT GMMx28D8; + ex1017_STRUCT ex1017 ; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Enter\n"); + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + GnbProcessTable ( + GnbHandle, + GfxGmcColockGatingDisableTN, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); + GfxGmcInitializeSequencerTN (Gfx); + GfxGmcInitializeFbLocationTN (Gfx); + GfxGmcSecureGarlicAccessTN (Gfx); + GfxGmcInitializeC6LocationTN (Gfx); + GnbProcessTable ( + GnbHandle, + GfxGmcInitTableTN, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); + if (Gfx->GmcClockGating) { + GnbProcessTable ( + GnbHandle, + GfxGmcColockGatingEnableTN, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); + } + if (Gfx->UmaSteering == excel993 ) { + ex1017.Value = 0x2; + GnbRegisterWriteTN (TYPE_GMM , 0x206c , &ex1017.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx)); + if (Gfx->GmcLockRegisters) { + GnbRegisterReadTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, 0, GnbLibGetHeader (Gfx)); + GMMx28D8.Field.CRITICAL_REGS_LOCK = 1; + GnbRegisterWriteTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } + if (Gfx->GmcPowerGating != GmcPowerGatingDisabled) { + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Exit\n"); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h new file mode 100644 index 0000000000..91de2f7475 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h @@ -0,0 +1,121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * various service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GFXGMCINITTN_H_ +#define _GFXGMCINITTN_H_ + +#include "GnbRegistersTN.h" + +AGESA_STATUS +GfxGmcInitTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#pragma pack (push, 1) + +/// DCT channel information +typedef struct { + D18F2x94_dct0_STRUCT D18F2x94_dct0; ///< Register 0x94 + D18F2x94_dct1_STRUCT D18F2x94_dct1; ///< Register 0x94 + D18F2x2E0_dct0_STRUCT D18F2x2E0_dct0; ///< Register 0x2E0 + D18F2x2E0_dct1_STRUCT D18F2x2E0_dct1; ///< Register 0x2E0 + D18F2x200_dct0_mp0_STRUCT D18F2x200_dct0_mp0; ///< Register 0x200 + D18F2x200_dct0_mp1_STRUCT D18F2x200_dct0_mp1; ///< Register 0x200 + D18F2x200_dct1_mp0_STRUCT D18F2x200_dct1_mp0; ///< Register 0x200 + D18F2x200_dct1_mp1_STRUCT D18F2x200_dct1_mp1; ///< Register 0x200 + D18F2x204_dct0_mp0_STRUCT D18F2x204_dct0_mp0; ///< Register 0x204 + D18F2x204_dct0_mp1_STRUCT D18F2x204_dct0_mp1; ///< Register 0x204 + D18F2x204_dct1_mp0_STRUCT D18F2x204_dct1_mp0; ///< Register 0x204 + D18F2x204_dct1_mp1_STRUCT D18F2x204_dct1_mp1; ///< Register 0x204 + D18F2x22C_dct0_mp0_STRUCT D18F2x22C_dct0_mp0; ///< Register 0x22C + D18F2x22C_dct0_mp1_STRUCT D18F2x22C_dct0_mp1; ///< Register 0x22C + D18F2x22C_dct1_mp0_STRUCT D18F2x22C_dct1_mp0; ///< Register 0x22C + D18F2x22C_dct1_mp1_STRUCT D18F2x22C_dct1_mp1; ///< Register 0x22C + D18F2x21C_dct0_mp0_STRUCT D18F2x21C_dct0_mp0; ///< Register 0x21C + D18F2x21C_dct0_mp1_STRUCT D18F2x21C_dct0_mp1; ///< Register 0x21C + D18F2x21C_dct1_mp0_STRUCT D18F2x21C_dct1_mp0; ///< Register 0x21C + D18F2x21C_dct1_mp1_STRUCT D18F2x21C_dct1_mp1; ///< Register 0x21C + D18F2x20C_dct0_mp0_STRUCT D18F2x20C_dct0_mp0; ///< Register 0x20C + D18F2x20C_dct0_mp1_STRUCT D18F2x20C_dct0_mp1; ///< Register 0x20C + D18F2x20C_dct1_mp0_STRUCT D18F2x20C_dct1_mp0; ///< Register 0x20C + D18F2x20C_dct1_mp1_STRUCT D18F2x20C_dct1_mp1; ///< Register 0x20C +} DCT_CHANNEL_INFO; + +/// DCT_CHANNEL_INFO field entry +typedef struct { + UINT8 RegisterSpaceType; ///< Register type + UINT32 Address; ///< Register address + UINT16 DctChannelInfoTableOffset; ///< destination offset in DCT_CHANNEL_INFO table +} DCT_REGISTER_ENTRY; + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c new file mode 100644 index 0000000000..15c0109566 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c @@ -0,0 +1,922 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 64730 $ @e \$Date: 2012-01-30 02:05:39 -0600 (Mon, 30 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbSbLib.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbGfxFamServices.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbNbInitLibV1.h" +#include "GfxConfigLib.h" +#include "GfxLibTN.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +#define GFX_REFCLK 100 // (in MHz) Reference clock is 100 MHz +#define GFX_NCLK_MIN 700 // (in MHz) Minimum value for NCLK is 700 MHz +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxIntInfoTableInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +CONST UINT8 DdiLaneConfigArrayTN [][4] = { + {31, 24, 1, 0}, + {24, 31, 0, 1}, + {24, 27, 0, 0}, + {27, 24, 0, 0}, + {28, 31, 1, 1}, + {31, 28, 1, 1}, + {32, 38, 2, 2}, + {32, 35, 2, 2}, + {35, 32, 2, 2}, + {8 , 15, 3, 3}, + {15, 8 , 3, 3}, + {12, 15, 3, 3}, + {15, 12, 3, 3}, + {16, 19, 4, 4}, + {19, 16, 4, 4}, + {16, 23, 4, 5}, + {23, 16, 5, 4}, + {20, 23, 5, 5}, + {23, 20, 5, 5}, +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init TN Support for eDP to Lvds translators + * + * + * @param[in] Engine Engine configuration info + * @param[in,out] Buffer Buffer pointer + * @param[in] Pcie PCIe configuration info + */ +VOID +STATIC +GfxIntegrateducEDPToLVDSRxIdCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *uceDPToLVDSRxId; + uceDPToLVDSRxId = (UINT8*) Buffer; + // APU output DP signal to a 3rd party DP translator chip (Analogix, Parade etc), + // the chip is handled by the 3rd party DP Rx firmware and it does not require the AMD SW to have a special + // initialize/enable/disable sequence to control this chip, the AMD SW just follows the eDP spec + // to enable the LVDS panel through this chip. + + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) { + *uceDPToLVDSRxId = eDP_TO_LVDS_COMMON_ID; + IDS_HDT_CONSOLE (GNB_TRACE, "Found 3rd party common EDPToLvds Connector\n"); + } + // APU output DP signal to a 3rd party DP translator chip which requires a AMD SW one time initialization + // to the chip based on the LVDS panel parameters ( such as power sequence time and panel SS parameter etc ). + // After that, the AMD SW does not need any specific enable/disable sequences to control this chip and just + // follows the eDP spec. to control the panel. + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToRealtecLvds) { + *uceDPToLVDSRxId = eDP_TO_LVDS_REALTEK_ID; + IDS_HDT_CONSOLE (GNB_TRACE, "Found Realtec EDPToLvds Connector\n"); + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init TN Nb p-State MemclkFreq + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillNbPstateMemclkFreqTN ( + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F2x94_dct0_STRUCT D18F2x94; + D18F2x2E0_dct0_STRUCT D18F2x2E0; + D18F5x160_STRUCT NbPstate; + UINT8 i; + UINT8 Channel; + ULONG memps0_freq; + ULONG memps1_freq; + + if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) { + Channel = 0; + } else { + Channel = 1; + } + + GnbRegisterReadTN ( + ((Channel == 0) ? D18F2x94_dct0_TYPE : D18F2x94_dct1_TYPE), + ((Channel == 0) ? D18F2x94_dct0_ADDRESS : D18F2x94_dct1_ADDRESS), + &D18F2x94.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + GnbRegisterReadTN ( + ((Channel == 0) ? D18F2x2E0_dct0_TYPE : D18F2x2E0_dct1_TYPE), + ((Channel == 0) ? D18F2x2E0_dct0_ADDRESS : D18F2x2E0_dct1_ADDRESS), + &D18F2x2E0.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + memps0_freq = 100 * GfxLibExtractDramFrequency ((UINT8) D18F2x94.Field.MemClkFreq, GnbLibGetHeader (Gfx)); + memps1_freq = 100 * GfxLibExtractDramFrequency ((UINT8) D18F2x2E0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx)); + + for (i = 0; i < 4; i++) { + NbPstate.Value = 0; + GnbRegisterReadTN ( + TYPE_D18F5, + (D18F5x160_ADDRESS + (i * 4)), + &NbPstate.Value, + 0, + GnbLibGetHeader (Gfx) + ); + if (NbPstate.Field.NbPstateEn == 1) { + IntegratedInfoTable->ulNbpStateMemclkFreq[i] = (NbPstate.Field.MemPstate == 0) ? memps0_freq : memps1_freq; + } + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init TN HTC Data + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillHtcDataTN ( + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F3x64_STRUCT D18F3x64; + + GnbRegisterReadTN ( + D18F3x64_TYPE, + D18F3x64_ADDRESS, + &D18F3x64.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + if (D18F3x64.Field.HtcEn == 1) { + IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52); + IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2); + } else { + IntegratedInfoTable->ucHtcTmpLmt = 0; + IntegratedInfoTable->ucHtcHystLmt = 0; + } +} +/*----------------------------------------------------------------------------------------*/ +/** + * Get TN CSR phy self refresh power down mode. + * + * + * @param[in] Channel DCT controller index + * @param[in] StdHeader Standard configuration header + * @retval CsrPhySrPllPdMode + */ +STATIC UINT32 +GfxLibGetMemPhyPllPdModeTN ( + IN UINT8 Channel, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F2xA8_dct0_STRUCT D18F2xA8; + + GnbRegisterReadTN ( + ((Channel == 0) ? D18F2xA8_dct0_TYPE : D18F2xA8_dct1_TYPE), + ((Channel == 0) ? D18F2xA8_dct0_ADDRESS : D18F2xA8_dct1_ADDRESS), + &D18F2xA8.Value, + 0, + StdHeader + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "MemPhyPllPdMode : %x\n", D18F2xA8.Field.MemPhyPllPdMode); + return D18F2xA8.Field.MemPhyPllPdMode; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get TN disable DLL shutdown in self-refresh mode. + * + * + * @param[in] Channel DCT controller index + * @param[in] StdHeader Standard configuration header + * @retval DisDllShutdownSR + */ +STATIC UINT32 +GfxLibGetDisDllShutdownSRTN ( + IN UINT8 Channel, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F2x90_dct0_STRUCT D18F2x90; + + GnbRegisterReadTN ( + ((Channel == 0) ? D18F2x90_dct0_TYPE : D18F2x90_dct1_TYPE), + ((Channel == 0) ? D18F2x90_dct0_ADDRESS : D18F2x90_dct1_ADDRESS), + &D18F2x90.Value, + 0, + StdHeader + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "DisDllShutdownSR : %x\n", D18F2x90.Field.DisDllShutdownSR); + return D18F2x90.Field.DisDllShutdownSR; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init TN NbPstateVid + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillNbPStateVidTN ( + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + //TN Register Mapping for D18F5x1[6C:60] + D18F5x160_STRUCT NbPstate[4]; + D0F0xBC_x1F428_STRUCT D0F0xBC_x1F428; + UINT8 MinNclkIndex; + UINT8 i; + + MinNclkIndex = 0; + IntegratedInfoTable->ucNBDPMEnable = 0; + + + GnbRegisterReadTN ( + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + &D0F0xBC_x1F428.Value, + 0, + GnbLibGetHeader (Gfx) + ); + // Check if NbPstate enbale + if (D0F0xBC_x1F428.Field.EnableNbDpm == 1) { + //1: enable 0: not enable + IntegratedInfoTable->ucNBDPMEnable = 1; + } + + for (i = 0; i < 4; i++) { + GnbRegisterReadTN ( + TYPE_D18F5, + (D18F5x160_ADDRESS + (i * 4)), + &NbPstate[i].Value, + 0, + GnbLibGetHeader (Gfx) + ); + if (NbPstate[i].Field.NbPstateEn == 1) { + MinNclkIndex = i; + } + IntegratedInfoTable->ulNbpStateNClkFreq[i] = GfxLibGetNclkTN ((UINT8) NbPstate[i].Field.NbFid, (UINT8) NbPstate[i].Field.NbDid); + } + IntegratedInfoTable->usNBP0Voltage = (USHORT) ((NbPstate[0].Field.NbVid_7_ << 7) | NbPstate[0].Field.NbVid_6_0_); + IntegratedInfoTable->usNBP1Voltage = (USHORT) ((NbPstate[1].Field.NbVid_7_ << 7) | NbPstate[1].Field.NbVid_6_0_); + IntegratedInfoTable->usNBP2Voltage = (USHORT) ((NbPstate[2].Field.NbVid_7_ << 7) | NbPstate[2].Field.NbVid_6_0_); + IntegratedInfoTable->usNBP3Voltage = (USHORT) ((NbPstate[3].Field.NbVid_7_ << 7) | NbPstate[3].Field.NbVid_6_0_); + + IntegratedInfoTable->ulMinimumNClk = GfxLibGetNclkTN ((UINT8) NbPstate[MinNclkIndex].Field.NbFid, (UINT8) NbPstate[MinNclkIndex].Field.NbDid); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize display path for given engine + * + * + * + * @param[in] Engine Engine configuration info + * @param[out] DisplayPathList Display path list + * @param[in] Gfx Pointer to global GFX configuration + */ + +AGESA_STATUS +GfxFmMapEngineToDisplayPath ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + UINT8 PrimaryDisplayPathId; + UINT8 SecondaryDisplayPathId; + UINTN DisplayPathIndex; + PrimaryDisplayPathId = 0xff; + SecondaryDisplayPathId = 0xff; + for (DisplayPathIndex = 0; DisplayPathIndex < (sizeof (DdiLaneConfigArrayTN) / 4); DisplayPathIndex++) { + if (DdiLaneConfigArrayTN[DisplayPathIndex][0] == Engine->EngineData.StartLane && + DdiLaneConfigArrayTN[DisplayPathIndex][1] == Engine->EngineData.EndLane) { + PrimaryDisplayPathId = DdiLaneConfigArrayTN[DisplayPathIndex][2]; + SecondaryDisplayPathId = DdiLaneConfigArrayTN[DisplayPathIndex][3]; + break; + } + } + if (PrimaryDisplayPathId != 0xff) { + IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId); + Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE; + GfxIntegratedCopyDisplayInfo ( + Engine, + &DisplayPathList[PrimaryDisplayPathId], + (PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL, + Gfx + ); + Status = AGESA_SUCCESS; + } else { + IDS_HDT_CONSOLE (GFX_MISC, " Error!!! Map DDI lanes %d - %d to display path failed\n", + Engine->EngineData.StartLane, + Engine->EngineData.EndLane + ); + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION, + Engine->EngineData.StartLane, + Engine->EngineData.EndLane, + 0, + 0, + GnbLibGetHeader (Gfx) + ); + Status = AGESA_ERROR; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy memory content to FB + * + * + * @param[in] SystemInfoTableV2Ptr Pointer to integrated info table + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxIntInfoTabablePostToFb ( + IN ATOM_FUSION_SYSTEM_INFO_V2 *SystemInfoTableV2Ptr, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 Index; + UINT32 TableOffset; + UINT32 FbAddress; + + TableOffset = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V2)) | 0x80000000; + for (Index = 0; Index < sizeof (ATOM_FUSION_SYSTEM_INFO_V2); Index = Index + 4 ) { + FbAddress = TableOffset + Index; + GnbLibMemWrite (Gfx->GmmBase + GMMx00_ADDRESS, AccessWidth32, &FbAddress, GnbLibGetHeader (Gfx)); + GnbLibMemWrite (Gfx->GmmBase + GMMx04_ADDRESS, AccessWidth32, (UINT8*) SystemInfoTableV2Ptr + Index, GnbLibGetHeader (Gfx)); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + *Init Dispclk <-> VID table + * + * + * @param[in] PpFuseArray Fuse array pointer + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxIntInfoTableInitDispclkTable ( + IN PP_FUSE_ARRAY *PpFuseArray, + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINTN Index; + for (Index = 0; Index < 4; Index++) { + if (PpFuseArray->DisplclkDid[Index] != 0) { + IntegratedInfoTable->sDISPCLK_Voltage[Index].ulMaximumSupportedCLK = GfxFmCalculateClock ( + PpFuseArray->DisplclkDid[Index], + GnbLibGetHeader (Gfx) + ); + IntegratedInfoTable->sDISPCLK_Voltage[Index].ulVoltageIndex = (ULONG) Index; + } + } + IntegratedInfoTable->ucDPMState0VclkFid = PpFuseArray->VclkDid[0]; + IntegratedInfoTable->ucDPMState1VclkFid = PpFuseArray->VclkDid[1]; + IntegratedInfoTable->ucDPMState2VclkFid = PpFuseArray->VclkDid[2]; + IntegratedInfoTable->ucDPMState3VclkFid = PpFuseArray->VclkDid[3]; + IntegratedInfoTable->ucDPMState0DclkFid = PpFuseArray->DclkDid[0]; + IntegratedInfoTable->ucDPMState1DclkFid = PpFuseArray->DclkDid[1]; + IntegratedInfoTable->ucDPMState2DclkFid = PpFuseArray->DclkDid[2]; + IntegratedInfoTable->ucDPMState3DclkFid = PpFuseArray->DclkDid[3]; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init Sclk <-> VID table + * + * + * @param[in] PpFuseArray Fuse array pointer + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxIntInfoTableInitSclkTable ( + IN PP_FUSE_ARRAY *PpFuseArray, + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINTN Index; + UINTN AvailSclkIndex; + ATOM_AVAILABLE_SCLK_LIST *AvailSclkList; + BOOLEAN Sorting; + AvailSclkList = &IntegratedInfoTable->sAvail_SCLK[0]; + + AvailSclkIndex = 0; + for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) { + if (PpFuseArray->SclkDpmDid[Index] != 0) { + AvailSclkList[AvailSclkIndex].ulSupportedSCLK = GfxFmCalculateClock (PpFuseArray->SclkDpmDid[Index], GnbLibGetHeader (Gfx)); + AvailSclkList[AvailSclkIndex].usVoltageIndex = PpFuseArray->SclkDpmVid[Index]; + AvailSclkList[AvailSclkIndex].usVoltageID = PpFuseArray->SclkVid[PpFuseArray->SclkDpmVid[Index]]; + AvailSclkIndex++; + } + } + //Sort by VoltageIndex & ulSupportedSCLK + if (AvailSclkIndex > 1) { + do { + Sorting = FALSE; + for (Index = 0; Index < (AvailSclkIndex - 1); Index++) { + ATOM_AVAILABLE_SCLK_LIST Temp; + BOOLEAN Exchange; + Exchange = FALSE; + if (AvailSclkList[Index].usVoltageIndex > AvailSclkList[Index + 1].usVoltageIndex) { + Exchange = TRUE; + } + if ((AvailSclkList[Index].usVoltageIndex == AvailSclkList[Index + 1].usVoltageIndex) && + (AvailSclkList[Index].ulSupportedSCLK > AvailSclkList[Index + 1].ulSupportedSCLK)) { + Exchange = TRUE; + } + if (Exchange) { + Sorting = TRUE; + LibAmdMemCopy (&Temp, &AvailSclkList[Index], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); + LibAmdMemCopy (&AvailSclkList[Index], &AvailSclkList[Index + 1], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); + LibAmdMemCopy (&AvailSclkList[Index + 1], &Temp, sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); + } + } + } while (Sorting); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Read GFX PGFSM register + * + * + * @param[in] RegisterAddress Index of PGFSM register + * @param[out] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +STATIC VOID +GfxPgfsmRegisterReadTN ( + IN UINT32 RegisterAddress, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RegisterWriteValue; + UINT32 RegisterReadValue; + RegisterWriteValue = (RegisterAddress << D0F0xBC_xE0300000_RegAddr_OFFSET) + + (1 << D0F0xBC_xE0300000_ReadOp_OFFSET) + + (0 << D0F0xBC_xE0300000_FsmAddr_OFFSET); + IDS_HDT_CONSOLE (GNB_TRACE, "Read PGFSM Register %d\n", RegisterAddress); + GnbRegisterWriteTN ( + D0F0xBC_xE0300000_TYPE, + D0F0xBC_xE0300000_ADDRESS, + &RegisterWriteValue, + 0, + StdHeader); + do { + GnbRegisterReadTN ( + D0F0xBC_xE0300008_TYPE, + D0F0xBC_xE0300008_ADDRESS, + &RegisterReadValue, + 0, + StdHeader); + } while ((RegisterReadValue & D0F0xBC_xE0300008_ReadValid_MASK) == 0); + *Value = RegisterReadValue & D0F0xBC_xE0300008_ReadValue_MASK; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Calculate ulGMCRestoreResetTime + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + * @param[in] PpFuseArray Fuse array pointer + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxCalculateRestoreResetTimeTN ( + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx, + IN PP_FUSE_ARRAY *PpFuseArray + ) +{ + UINT8 MaxDid; + ULONG FreqSclk; + UINTN Index; + UINT32 TSclk; + UINT32 TRefClk; + UINT32 TNclkHalf; + UINT32 PgfsmDelayReg0; + UINT32 PgfsmDelayReg1; + UINT32 ResetTime; + UINT32 IsoTime; + UINT32 MemSd; + UINT32 MotherPso; + UINT32 DaughterPso; + UINT32 THandshake; + UINT32 TGmcSync; + UINT32 TPuCmd; + UINT32 TPgfsmCmdSerialization; + UINT32 TReset; + UINT32 TMoPso; + UINT32 TDaPso; + UINT32 TMemSd; + UINT32 TIso; + UINT32 TRegRestore; + UINT32 TPgfsmCleanUp; + UINT32 TGmcPu; + UINT32 TGmcPd; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeTN Enter\n"); + // Find FreqSclk = MIN of frequencies SclkDpmDid (0 to 4) and SclkThermDid + // First find the highest Did + MaxDid = PpFuseArray->SclkThermDid; + for (Index = 0; Index < 4; Index++) { + // Compare with SclkDpmDid[x] - These are stored in: + // IntegratedInfoTable-> sDISPCLK_Voltage[Index].ulMaximumSupportedCLK + MaxDid = MAX (MaxDid, PpFuseArray->SclkDpmDid[Index]); + } + IDS_HDT_CONSOLE (GNB_TRACE, "MaxDid = %d\n", MaxDid); + FreqSclk = GfxFmCalculateClock (MaxDid, GnbLibGetHeader (Gfx)); + // FreqSclk is in 10KHz units - need calculations in nS + // For accuracy, do calculations in .01nS, then convert at the end + TSclk = (100 * (1000000000 / 10000)) / FreqSclk; + // FreqRefClk frequency of reference clock + // Caclculate period in .01 nS + TRefClk = (100 * 1000) / GFX_REFCLK; + // FreqNclkHalf = half of Minimum NCLK value + // Calculate period in .01 nS + TNclkHalf = (100 * 1000) / (GFX_NCLK_MIN / 2); + + // Read delay time values from PGFSM registers + GfxPgfsmRegisterReadTN (2 , &PgfsmDelayReg0, GnbLibGetHeader (Gfx)); + GfxPgfsmRegisterReadTN (3 , &PgfsmDelayReg1, GnbLibGetHeader (Gfx)); + ResetTime = (PgfsmDelayReg0 & 0x000000FF ) >> 0 ; + IsoTime = (PgfsmDelayReg0 & 0x0000FF00 ) >> 8 ; + MemSd = (PgfsmDelayReg0 & 0x00FF0000 ) >> 16 ; + MotherPso = (PgfsmDelayReg1 & 0x00000FFF ) >> 0 ; + DaughterPso = (PgfsmDelayReg1 & 0x00FFF000 ) >> 12 ; + IDS_HDT_CONSOLE (GNB_TRACE, "ResetTime = %d\n", ResetTime); + IDS_HDT_CONSOLE (GNB_TRACE, "IsoTime = %d\n", IsoTime); + IDS_HDT_CONSOLE (GNB_TRACE, "MemSd = %d\n", MemSd); + IDS_HDT_CONSOLE (GNB_TRACE, "MotherPso = %d\n", MotherPso); + IDS_HDT_CONSOLE (GNB_TRACE, "DaughterPso = %d\n", DaughterPso); + + // Calculate various timing values required for the final calculation + // THandshake = 10*1/FreqNclkHalf + THandshake = 10 * TNclkHalf; + // TGmcSync = 2.5*(1/FreqRefclk+1/FreqSclk) + TGmcSync = (25 * (TRefClk + TSclk)) / 10; + // TPuCmd =9*1/FreqSclk + TPuCmd = 9 * TSclk; + // TPgfsmCmdSerialization = 82*1/FreqSclk + TPgfsmCmdSerialization = 82 * TSclk; + // TReset = (RESET_TIME+3)*1/FreqRefclk+3*1/FreqSclk+TGmcSync + TReset = ((ResetTime + 3) * TRefClk) + (3 * TSclk) + TGmcSync; + // TMoPso = (MOTHER_PSO+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync + TMoPso = ((MotherPso + 3) * TRefClk) + (3 * TSclk) + TGmcSync; + // TDaPso = (DAUGHTER_PSO+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync + TDaPso = ((DaughterPso + 3) * TRefClk) + (3 * TSclk) + TGmcSync; + // TMemSD = (MEM_SD+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync + TMemSd = ((MemSd + 3) * TRefClk) + (3 * TSclk) + TGmcSync; + // TIso = (ISO_TIME+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync + TIso = ((IsoTime + 3) * TRefClk) + (3 * TSclk) + TGmcSync; + // TRegRestore = 508*1/FreqSclk + TRegRestore = 508 * TSclk; + // TPgfsmCleanUp = 3*1/FreqSclk + TPgfsmCleanUp = 3 * TSclk; + // TGmcPu = TPUCmd + TPgfsmCmdSerialization + TReset + TMoPso + TDaPso + TMemSD + TIso + TRegRestore + TGmcPu = TPuCmd + TPgfsmCmdSerialization + TReset + TMoPso + TDaPso + TMemSd + TIso + TRegRestore; + // TGmcPd = THandshake + TPgfsmCmdSerialization + Tiso + TmemSD + TMoPso + TDaPso + TpgfsmCleanUp + 3*TReset + TGmcPd = THandshake + TPgfsmCmdSerialization + TIso + TMemSd + TMoPso + TDaPso + TPgfsmCleanUp + (3 * TReset); + // ulGMCRestoreResetTime = TGmcPu + TGmcPd + // All calculated times are in .01nS for accuracy. We can now correct that. + // By adding 99 and dividing by 100, value is rounded up to next 1 nS + IntegratedInfoTable->ulGMCRestoreResetTime = (TGmcPd + TGmcPu + 99) / 100; + IDS_HDT_CONSOLE (GNB_TRACE, "ulGMCRestoreResetTime = %d\n", IntegratedInfoTable->ulGMCRestoreResetTime); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeTN Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build integrated info table + * + * + * + * @param[in] Gfx Gfx configuration info + * @retval AGESA_STATUS + */ +AGESA_STATUS +STATIC +GfxIntInfoTableInitTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + ATOM_FUSION_SYSTEM_INFO_V2 SystemInfoTableV2; + PP_FUSE_ARRAY *PpFuseArray; + PCIe_PLATFORM_CONFIG *Pcie; + ATOM_PPLIB_POWERPLAYTABLE3 *PpTable; + UINT8 Channel; + + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitTN Enter\n"); + LibAmdMemFill (&SystemInfoTableV2, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V2), GnbLibGetHeader (Gfx)); + SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7); + ASSERT (SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize == 512); + SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1; + SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableContentRevision = 7; + SystemInfoTableV2.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetSytemPllCofTN (GnbLibGetHeader (Gfx)) * 100; + SystemInfoTableV2.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100; + SystemInfoTableV2.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl; + SystemInfoTableV2.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2; + SystemInfoTableV2.sIntegratedSysInfo.ucMemoryType = 3; //DDR3 + SystemInfoTableV2.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ + SystemInfoTableV2.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx)); + SystemInfoTableV2.sIntegratedSysInfo.ulMinEngineClock = 200 * 100; + SystemInfoTableV2.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate; + SystemInfoTableV2.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum; + //Locate PCIe configuration data to get definitions of display connectors + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1; + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1; + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex; + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport; + SystemInfoTableV2.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7, sExtDispConnInfo); + SystemInfoTableV2.sIntegratedSysInfo.ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx)); + + SystemInfoTableV2.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum; + + SystemInfoTableV2.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value; + IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value); + if (Gfx->LvdsMiscControl.Field.TravisLvdsVoltOverwriteEn) { + SystemInfoTableV2.sIntegratedSysInfo.gnbgfxline429 = Gfx->gfxplmcfg0 ; + IDS_HDT_CONSOLE (GNB_TRACE, "TravisLVDSVoltAdjust : %x\n", Gfx->gfxplmcfg0 ); + } + + SystemInfoTableV2.sIntegratedSysInfo.ulOtherDisplayMisc = Gfx->DisplayMiscControl.Value; + IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value); + + // LVDS + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl; + SystemInfoTableV2.sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue; + SystemInfoTableV2.sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq; + Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + Status = GfxIntegratedEnumerateAllConnectors ( + &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sPath[0], + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, + GfxIntegrateducEDPToLVDSRxIdCallback, + &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId, + Pcie + ); + + // Build PP table + PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoTableV2.ulPowerplayTable; + // Build PP table + Status = GfxPowerPlayBuildTable (PpTable, Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + // Assign usFormatID to 0x000B to represent Trinity + PpTable->usFormatID = 0xB; + // Build info from fuses + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray != NULL) { + // Build Display clock info + GfxIntInfoTableInitDispclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx); + // Build Sclk info table + GfxIntInfoTableInitSclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx); + } else { + Status = AGESA_ERROR; + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + //@todo review if thouse parameters needed + // Fill in Nb P-state MemclkFreq Data + GfxFillNbPstateMemclkFreqTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); + // Fill in HTC Data + GfxFillHtcDataTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); + // Fill in NB P states VID + GfxFillNbPStateVidTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); + // Fill in NCLK info + //GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); + // Fill in the M3 arbitration control tables + //GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); + // Family specific data update + + // Determine ulGMCRestoreResetTime + Status = GfxCalculateRestoreResetTimeTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx, PpFuseArray); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + //GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); + SystemInfoTableV2.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940; + SystemInfoTableV2.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000; + + if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) { + Channel = 0; + } else { + Channel = 1; + } + if (GfxLibGetMemPhyPllPdModeTN (Channel, GnbLibGetHeader (Gfx)) != 0) { + SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT2; + } + if (GfxLibGetDisDllShutdownSRTN (Channel, GnbLibGetHeader (Gfx)) == 0) { + SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT1; + } + if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) { + SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT0; + } + SystemInfoTableV2.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE; + + IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig); + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV2.sIntegratedSysInfo, GnbLibGetHeader (Gfx)); + //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.) + GfxIntInfoTabablePostToFb (&SystemInfoTableV2, Gfx); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build integrated info table + * GMC FB access requred + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +GfxIntInfoTableInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + GFX_PLATFORM_CONFIG *Gfx; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + if (GfxLibIsControllerPresent (StdHeader)) { + Status = GfxLocateConfigData (StdHeader, &Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status != AGESA_FATAL) { + Status = GfxIntInfoTableInitTN (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Exit[0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c new file mode 100644 index 0000000000..8aace220c3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c @@ -0,0 +1,478 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize PP/DPM fuse table. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GfxLibTN.h" +#include "GnbCommonLib.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +CONST UINT16 GfxMemClockFrequencyDefinitionTable [][8] = { +{0 , 0 , 0 , 0 , 333, 0, 400, 0 }, +{0 , 0 , 533, 0 , 0 , 0 , 667, 0 }, +{0 , 0 , 800, 0 , 0 , 0 , 0 , 0 }, +{0 , 1050, 1066, 0 , 0, 0 , 0, 1200} +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GfxFmDisableController ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxFmCalculateClock ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GfxFmIsVbiosPosted ( + IN GFX_PLATFORM_CONFIG *Gfx + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Disable GFX controller + * + * + * + * @param[in] StdHeader Standard configuration header + */ + +VOID +GfxFmDisableController ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbLibPciRMW ( + MAKE_SBDFO (0, 0, 0, 0,D0F0x7C_ADDRESS), + AccessS3SaveWidth32, + 0xffffffff, + 1 << D0F0x7C_ForceIntGFXDisable_OFFSET, + StdHeader + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get system PLL COF + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval System PLL COF + */ +UINT32 +GfxLibGetSytemPllCofTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_xFF000000_STRUCT D0F0xBC_xFF000000; + GnbRegisterReadTN (D0F0xBC_xFF000000_TYPE, D0F0xBC_xFF000000_ADDRESS, &D0F0xBC_xFF000000.Value, 0, StdHeader); + return 100 * (D0F0xBC_xFF000000.Field.MainPllOpFreqIdStartup + 0x10); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate COF for DFS out of Main PLL + * + * + * + * @param[in] Did Did + * @param[in] StdHeader Standard Configuration Header + * @retval COF in 10khz + */ + +UINT32 +GfxFmCalculateClock ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Divider; + UINT32 SystemPllCof; + SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100; + if (Did >= 8 && Did <= 0x3F) { + Divider = Did * 25; + } else if (Did > 0x3F && Did <= 0x5F) { + Divider = (Did - 64) * 50 + 1600; + } else if (Did > 0x5F && Did <= 0x7E) { + Divider = (Did - 96) * 100 + 3200; + } else if (Did == 0x7f) { + Divider = 128 * 100; + } else { + ASSERT (FALSE); + return 200 * 100; + } + ASSERT (Divider != 0); + return (((SystemPllCof * 100) + (Divider - 1)) / Divider); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set idle voltage mode for GFX + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +BOOLEAN +GfxFmIsVbiosPosted ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 Value; + + GnbRegisterReadTN (GMMx670_TYPE, GMMx670_ADDRESS, &Value, 0, GnbLibGetHeader (Gfx)); + return ((Value & BIT16) == 0) ? TRUE : FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Extract DRAM frequency + * + * + * + * @param[in] Encoding Memory Clock Frequency Value Definition + * @param[in] StdHeader Standard configuration header + * @retval Dram fraquency Mhz + */ +UINT32 +GfxLibExtractDramFrequency ( + IN UINT8 Encoding, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (Encoding >= (sizeof (GfxMemClockFrequencyDefinitionTable) / sizeof (UINT16))) { + ASSERT (FALSE); + return 0; + } + return GfxMemClockFrequencyDefinitionTable[Encoding / 8][Encoding % 8]; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get max SCLK + * + * + * @param[in] StdHeader Standard configuration header + * @retval Max SCLK in Mhz + */ +UINT32 +GfxLibGetMaxSclk ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 MaxSclkClk; + D0F0xBC_xFF000000_STRUCT D0F0xBC_xFF000000; + D0F0xBC_xE0003048_STRUCT D0F0xBC_xE0003048; + + GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xFF000000_ADDRESS, &D0F0xBC_xFF000000.Value, 0, StdHeader); + GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE0003048_ADDRESS, &D0F0xBC_xE0003048.Value, 0, StdHeader); + //sclk_max_freq = 100 * (GCLK_PLL_FUSES.MainPllOptFreqIdStartup + 16) / + // (((SCLK_MIN_DIV.INT<<12 + SCLK_MIN_DIV.FRAC)>>12) + MaxSclkClk = 100 * (D0F0xBC_xFF000000.Field.MainPllOpFreqIdStartup + 16); + MaxSclkClk /= ((D0F0xBC_xE0003048.Field.Intv << 12) + D0F0xBC_xE0003048.Field.Fracv) >> 12; + return MaxSclkClk; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of SCLK Dram burst + * + * + * @param[in] ScaleMp Scaled number of sclk_max_freq / memps_freq + * @param[in] StdHeader Standard configuration header + * @retval number of sclks (*2) per dram burst, except (0,1,2,3)=(1,1.25,1.5,1.75) + */ +UINT32 +GfxLibGetNumberOfSclkPerDramBurst ( + IN UINT32 ScaleMp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + if ((2 * ScaleMp) < 125) { + return 0; //STATE0 = 0 + } else if ((2 * ScaleMp) < 150) { + return 1; //STATE0 = 1 + } else if ((2 * ScaleMp) < 175) { + return 2; //STATE0 = 2 + } else if ((2 * ScaleMp) < 200) { + return 3; //STATE0 = 3 + } else { + //STATE0 = floor(4*scale_mp[0] ) + return ((4 * ScaleMp) / 100); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate TN NCLK clock + * + * + * + * @param[in] NbFid NbFid + * @param[in] NbDid NbDid + * @retval Clock in 10KHz + */ + +UINT32 +GfxLibGetNclkTN ( + IN UINT8 NbFid, + IN UINT8 NbDid + ) +{ + UINT32 Divider; + //i.e. NBCOF[0] = (100 * (D18F5x160[NbFid] + 4h) / (2^D18F5x160[NbDid])) Mhz + if (NbDid == 1) { + Divider = 2; + } else if (NbDid == 0) { + Divider = 1; + } else { + Divider = 1; + } + ASSERT (NbDid == 0 || NbDid == 1); + return ((10000 * (NbFid + 4)) / Divider); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set VID through CG client + * + * + * @param[in] Vid VID code + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxRequestVoltageTN ( + IN UINT8 Vid, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GMMx770_STRUCT GMMx770; + GMMx774_STRUCT GMMx774; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxRequestVoltageTN Enter\n"); + + GnbRegisterReadTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, 0, StdHeader); + GMMx770.Field.VoltageChangeEn = 1; + GnbRegisterWriteTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GMMx770.Field.VoltageLevel = Vid; + GMMx770.Field.VoltageChangeReq = ~GMMx770.Field.VoltageChangeReq; + GnbRegisterWriteTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + do { + GnbRegisterReadTN (GMMx774_TYPE, GMMx774_ADDRESS, &GMMx774, 0, StdHeader); + } while (GMMx774.Field.VoltageChangeAck != GMMx770.Field.VoltageChangeReq); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxRequestVoltageTN Exit\n"); + return AGESA_SUCCESS; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set SCLK + * + * + * @param[in] Did Devider + * @param[in] StdHeader Standard configuration header + * @retval previous DID + */ + +UINT8 +GfxRequestSclkTNS3Save ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + S3_SAVE_DISPATCH (StdHeader, GfxRequestSclkTNS3Script_ID, sizeof (Did), &Did); + return GfxRequestSclkTN (Did, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set SCLK + * + * + * @param[in] Did Devider + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +UINT8 +GfxRequestSclkTN ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GMMx600_STRUCT GMMx600; + GMMx604_STRUCT GMMx604; + UINT8 OriginalDid; + do { + GnbRegisterReadTN (GMMx604_TYPE, GMMx604_ADDRESS, &GMMx604, 0, StdHeader); + } while (GMMx604.Field.SclkStatus == 0); + GnbRegisterReadTN (GMMx600_TYPE, GMMx600_ADDRESS, &GMMx600, 0, StdHeader); + OriginalDid = (UINT8) GMMx600.Field.IndClkDiv; + GMMx600.Field.IndClkDiv = Did; + GnbRegisterWriteTN (GMMx600_TYPE, GMMx600_ADDRESS, &GMMx600, 0, StdHeader); + do { + GnbRegisterReadTN (GMMx604_TYPE, GMMx604_ADDRESS, &GMMx604, 0, StdHeader); + } while (GMMx604.Field.SclkStatus == 0); + return OriginalDid; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Sclk in S3 script + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context Length (not used) + * @param[in] Context pointer to UINT32 number of us + */ +VOID +GfxRequestSclkTNS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ) +{ + GfxRequestSclkTN (* ((UINT8*) Context), StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate did from main VCO + * + * + * + * @param[in] Vco Vco in 10Khz + * @param[in] StdHeader Standard configuration header + * @retval DID + */ + +UINT8 +GfxLibCalculateDidTN ( + IN UINT32 Vco, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Divider; + UINT32 SystemPllCof; + UINT8 Did; + ASSERT (Vco != 0); + SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100; + Divider = ((SystemPllCof * 100) + (Vco - 1)) / Vco; + Did = 0; + if (Divider < 200) { + } else if (Divider <= 1575) { + Did = (UINT8) (Divider / 25); + } else if (Divider <= 3150) { + Did = (UINT8) ((Divider - 1600) / 50) + 64; + } else if (Divider <= 6200) { + Did = (UINT8) ((Divider - 3200) / 100) + 96; + } else { + Did = 0x7f; + } + return Did; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h new file mode 100644 index 0000000000..69dd6477eb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h @@ -0,0 +1,134 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * various service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GFXLIBTN_H_ +#define _GFXLIBTN_H_ + +UINT32 +GfxLibGetSytemPllCofTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxLibExtractDramFrequency ( + IN UINT8 Encoding, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxLibGetMaxSclk ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxLibGetNumberOfSclkPerDramBurst ( + IN UINT32 ScaleMp, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxLibGetNclkTN ( + IN UINT8 NbFid, + IN UINT8 NbDid + ); + +AGESA_STATUS +GfxRequestVoltageTN ( + IN UINT8 Vid, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GfxRequestSclkTN ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GfxRequestSclkTNS3Save ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GfxRequestSclkTNS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +UINT8 +GfxLibCalculateDidTN ( + IN UINT32 Vco, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c new file mode 100644 index 0000000000..4e3efa5466 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c @@ -0,0 +1,304 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 65199 $ @e \$Date: 2012-02-09 21:36:06 -0600 (Thu, 09 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbNbInitLibV1.h" +#include "GnbGfxFamServices.h" +#include "GfxLibTN.h" +#include "GfxGmcInitTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "PcieConfigData.h" +#include "PcieConfigLib.h" +#include "cpuFamilyTranslation.h" +#include "GnbHandleLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxIntegratedEnumerateAudioConnectors ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +exec803 /* GfxAzWorkaroundTN */ ( + IN GFX_PLATFORM_CONFIG *Gfx + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Set boot up voltage + * + * + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxSetBootUpVoltageTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltageTN Enter\n"); + GfxRequestVoltageTN (GnbLocateHighestVidCode (GnbLibGetHeader (Gfx)), GnbLibGetHeader (Gfx)); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set boot up voltage + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +VOID +exec803 /* GfxAzWorkaroundTN */ ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 i; + UINT32 Address; + UINT32 Data; + + + Data = 0x156; + for (i = 0; i < 6; i++) { + Address = 0x5E00 + (i * 0x18); + GnbLibMemWrite (Gfx->GmmBase + Address, AccessS3SaveWidth32, &Data, GnbLibGetHeader (Gfx)); + GnbLibMemRMW (Gfx->GmmBase + Address + 4, AccessS3SaveWidth32, 0xFFFFFF00, 0xF0, GnbLibGetHeader (Gfx)); + } + + return; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Mid Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GFX_PLATFORM_CONFIG *Gfx; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_FATAL) { + GfxFmDisableController (StdHeader); + } else { + if (Gfx->UmaInfo.UmaMode != UMA_NONE) { + Status = GfxEnableGmmAccess (Gfx); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status != AGESA_SUCCESS) { + // Can not initialize GMM registers going to disable GFX controller + IDS_HDT_CONSOLE (GNB_TRACE, " Fail to establish GMM access\n"); + Gfx->UmaInfo.UmaMode = UMA_NONE; + GfxFmDisableController (StdHeader); + } else { + Status = GfxGmcInitTN (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxSetBootUpVoltageTN (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxInitSsid (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxIntegratedEnumerateAudioConnectors (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + exec803 /* GfxAzWorkaroundTN */ (Gfx); + } + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Determine number of audio ports for each connector + * + * + * + * @param[in] Engine Engine configuration info + * @param[in,out] Buffer Buffer pointer + * @param[in] Pcie PCIe configuration info + */ +VOID +STATIC +GfxIntegratedAudioEnumCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *AudioCount; + AudioCount = (UINT8*) Buffer; + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) { + IDS_HDT_CONSOLE (GNB_TRACE, "Found HDMI Connector\n"); + (*AudioCount)++; + } else if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) { + if ((Engine->Type.Ddi.DdiData.Flags & DDI_DATA_FLAGS_DP1_1_ONLY) == 0) { + IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.2 Connector\n"); + *AudioCount += 4; + } else { + IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.1 Connector\n"); + (*AudioCount)++; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "New AudioCount = %d\n", *AudioCount); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors with audio capability and configure number of ports + * + * + * + * @param[in] Gfx Gfx configuration info + */ +AGESA_STATUS +GfxIntegratedEnumerateAudioConnectors ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT8 AudioCount; + AGESA_STATUS Status; + GMMx5F50_STRUCT GMMx5F50; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Enter\n"); + + Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie); + if ((Status == AGESA_SUCCESS) && (Gfx->GnbHdAudio != 0)) { + AudioCount = 0; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, + GfxIntegratedAudioEnumCallback, + &AudioCount, + Pcie + ); + if (AudioCount > 4) { + AudioCount = 4; + } + GMMx5F50.Value = 0x00; + GMMx5F50.Field.PortConnectivity = (7 - AudioCount); + GMMx5F50.Field.PortConnectivityOverrideEnable = 1; + GnbRegisterWriteTN (GMMx5F50_TYPE, GMMx5F50_ADDRESS, &GMMx5F50.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Exit\n"); + return Status; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c new file mode 100644 index 0000000000..36e013ef3c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c @@ -0,0 +1,155 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbGfxConfig.h" +#include "GnbFuseTable.h" +#include "GnbGfxInitLibV1.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxPostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + + +AGESA_STATUS +GfxPostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_POST_PARAMS *PostParamsPtr; + GFX_CARD_CARD_INFO GfxDiscreteCardInfo; + AGESA_STATUS Status; + GFX_PLATFORM_CONFIG *Gfx; + PostParamsPtr = (AMD_POST_PARAMS *)StdHeader; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceTN Enter\n"); + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + if (GfxLibIsControllerPresent (StdHeader)) { + if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) { + LibAmdMemFill (&GfxDiscreteCardInfo, 0x0, sizeof (GfxDiscreteCardInfo), StdHeader); + GfxGetDiscreteCardInfo (&GfxDiscreteCardInfo, StdHeader); + if (((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) || + (GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != GfxDiscreteCardInfo.PcieGfxCardBitmap)) || + ((PostParamsPtr->GnbPostConfig.IgpuEnableDisablePolicy == IGPU_DISABLE_ANY_PCIE) && + ((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) || (GfxDiscreteCardInfo.PcieGfxCardBitmap != 0)))) { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + IDS_HDT_CONSOLE (GFX_MISC, " GfxDisabled due dGPU policy\n"); + } + } + } else { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + Gfx->GfxFusedOff = TRUE; + } + } else { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceTN Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c new file mode 100644 index 0000000000..876614e510 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c @@ -0,0 +1,1096 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GFx tables + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 64726 $ @e \$Date: 2012-01-30 01:00:01 -0600 (Mon, 30 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbRegistersTN.h" +#include "cpuFamilyTranslation.h" +#include "GnbInitTN.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + +GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN [] = { + //2.1 Disable clock-gating + GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00000C80), + GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00001401), + GNB_ENTRY_TERMINATE +}; + + +GNB_TABLE ROMDATA GfxGmcInitTableTN [] = { + GNB_ENTRY_RMW (D18F5x178_TYPE, D18F5x178_ADDRESS, D18F5x178_SwGfxDis_MASK, 0 << D18F5x178_SwGfxDis_OFFSET), + //2.2 System memory address translation + GNB_ENTRY_COPY (GMMx2814_TYPE, GMMx2814_ADDRESS, 0, 32, D18F2x40_dct0_TYPE, D18F2x40_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2818_TYPE, GMMx2818_ADDRESS, 0, 32, D18F2x40_dct1_TYPE, D18F2x40_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx281C_TYPE, GMMx281C_ADDRESS, 0, 32, D18F2x44_dct0_TYPE, D18F2x44_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2820_TYPE, GMMx2820_ADDRESS, 0, 32, D18F2x44_dct1_TYPE, D18F2x44_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2824_TYPE, GMMx2824_ADDRESS, 0, 32, D18F2x48_dct0_TYPE, D18F2x48_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2828_TYPE, GMMx2828_ADDRESS, 0, 32, D18F2x48_dct1_TYPE, D18F2x48_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx282C_TYPE, GMMx282C_ADDRESS, 0, 32, D18F2x4C_dct0_TYPE, D18F2x4C_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2830_TYPE, GMMx2830_ADDRESS, 0, 32, D18F2x4C_dct1_TYPE, D18F2x4C_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2834_TYPE, GMMx2834_ADDRESS, 0, 32, D18F2x60_dct0_TYPE, D18F2x60_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2838_TYPE, GMMx2838_ADDRESS, 0, 32, D18F2x64_dct0_TYPE, D18F2x64_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx283C_TYPE, GMMx283C_ADDRESS, 0, 32, D18F2x60_dct1_TYPE, D18F2x60_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2840_TYPE, GMMx2840_ADDRESS, 0, 32, D18F2x64_dct1_TYPE, D18F2x64_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 0, 8, D18F2x80_dct0_TYPE, D18F2x80_dct0_ADDRESS, 0, 8), + GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 16, 1, D18F2x94_dct0_TYPE, D18F2x94_dct0_ADDRESS, 22, 1), + GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 19, 1, D18F2xA8_dct0_TYPE, D18F2xA8_dct0_ADDRESS, 20, 1), + GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 0, 8, D18F2x80_dct1_TYPE, D18F2x80_dct1_ADDRESS, 0, 8), + GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 16, 1, D18F2x94_dct1_TYPE, D18F2x94_dct1_ADDRESS, 22, 1), + GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 19, 1, D18F2xA8_dct1_TYPE, D18F2xA8_dct1_ADDRESS, 20, 1), + GNB_ENTRY_COPY (GMMx284C_TYPE, GMMx284C_ADDRESS, 0, 32, TYPE_D18F2 , 0x110 , 0, 32), + GNB_ENTRY_COPY (GMMx2850_TYPE, GMMx2850_ADDRESS, 0, 32, D18F2x114_TYPE, D18F2x114_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2854_TYPE, GMMx2854_ADDRESS, 0, 32, D18F1xF0_TYPE, D18F1xF0_ADDRESS, 0, 32), + //GNB_ENTRY_COPY (GMMx2858_TYPE, GMMx2858_ADDRESS, 0, 32, ????, ????, 0, 32), + GNB_ENTRY_COPY (GMMx285C_TYPE, GMMx285C_ADDRESS, 0, 32, TYPE_D18F2 , 0x10c , 0, 32), + // 2.4 RENG init + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000000), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001b0a05), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000001D), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00080500), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000027), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001050c), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002a), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x1000051e), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002e), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010536), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000031), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001053e), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000034), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010546), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000037), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a054e), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000053), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001056f), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000056), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010572), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000059), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020575), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005d), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000800), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005f), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a0801), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007b), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001082a), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007e), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0014082d), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000094), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00040843), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000009a), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00170851), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000b3), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001d086a), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d2), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000891), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d4), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000893), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d6), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020895), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000da), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020899), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000de), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0002089d), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e2), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000208a1), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e6), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x006808cd), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000150), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0016094d), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000168), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d096d), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000177), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0009097f), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000182), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000a098a), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000018e), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d0998), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000019d), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000409a7), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001a3), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x003709cd), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001dc), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000f0a21), + GNB_ENTRY_WR (GMMx28D4_TYPE, GMMx28D4_ADDRESS, 0x7b1ec000), + GNB_ENTRY_WR (GMMx28D8_TYPE, GMMx28D8_ADDRESS, 0x200cf01d), + // 2.5 + GNB_ENTRY_RMW (GMMx5490_TYPE, GMMx5490_ADDRESS, GMMx5490_FB_WRITE_EN_MASK | GMMx5490_FB_READ_EN_MASK, (1 << GMMx5490_FB_READ_EN_OFFSET) | (1 << GMMx5490_FB_WRITE_EN_OFFSET)), + // 2.6 Perfromance tuning + GNB_ENTRY_WR (TYPE_GMM , 0x27d0 , 0x10734847), + GNB_ENTRY_WR (TYPE_GMM , 0x27c0 , 0x00032005), + GNB_ENTRY_WR (TYPE_GMM , 0x27c4 , 0x00C12008), + GNB_ENTRY_WR (TYPE_GMM , 0x27d4 , 0x00003d3c), + GNB_ENTRY_WR (TYPE_GMM , 0x277c , 0x00000007), + GNB_ENTRY_WR (TYPE_GMM , 0x2198 , 0x000221b1), + GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080A20), + GNB_ENTRY_WR (TYPE_GMM , 0x201c , 0x66660006), + GNB_ENTRY_WR (TYPE_GMM , 0x2020 , 0x70770007), + GNB_ENTRY_WR (TYPE_GMM , 0x2018 , 0x66070050), + GNB_ENTRY_WR (TYPE_GMM , 0x2014 , 0x77550000), + GNB_ENTRY_WR (TYPE_GMM , 0x2794 , 0xfcfcfdfc), + GNB_ENTRY_WR (TYPE_GMM , 0x2798 , 0xfcfcfdfc), + GNB_ENTRY_WR (TYPE_GMM , 0x27a4 , 0x00ffffff), + GNB_ENTRY_WR (TYPE_GMM , 0x27a8 , 0x00ffffff), + GNB_ENTRY_WR (TYPE_GMM , 0x278c , 0x00000004), + GNB_ENTRY_WR (TYPE_GMM , 0x2790 , 0x00000004), + GNB_ENTRY_WR (TYPE_GMM , 0x2628 , 0x44111222), + GNB_ENTRY_WR (TYPE_GMM , 0x25e0 , 0x00000004), + GNB_ENTRY_WR (TYPE_GMM , 0x262c , 0x11222111), + GNB_ENTRY_WR (TYPE_GMM , 0x25e4 , 0x00000002), + //2.7 Miscellaneous programming + GNB_ENTRY_WR (TYPE_GMM , 0x20b4 , 0x00000000), + //2.8 Enabling garlic interface + GNB_ENTRY_RMW (TYPE_GMM , 0x2878 , 0x1 , 1 << 0 ), + // Limit number of garlic credits to 12 + GNB_ENTRY_WR (TYPE_GMM , 0x276c , 0x000000ff), + GNB_ENTRY_WR (TYPE_GMM , 0x2898 , 0x01800360), + GNB_ENTRY_RMW (TYPE_GMM , 0x289c , 0x8000 , 1 << 15 ), + GNB_ENTRY_REV_RMW (0x0000000000000100ull , TYPE_GMM , 0x289c , 0x8000 , 0 << 15 ), + GNB_ENTRY_RMW (GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 0 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET), + GNB_ENTRY_REV_RMW (0x0000000000000100ull , GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 1 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET), + //2.10 UVD and VCE latency + //These settings are to improve UVD and VCE latency. + //They need these settings to get good memory performance. + GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080200), + GNB_ENTRY_WR (TYPE_GMM , 0x2190 , 0x001EA1A1), + GNB_ENTRY_WR (TYPE_GMM , 0x2180 , 0x0000A1E1), + GNB_ENTRY_WR (TYPE_GMM , 0x218c , 0x000FA1E1), + GNB_ENTRY_WR (GMMx2188_TYPE, GMMx2188_ADDRESS, 0x0000A1E1), + GNB_ENTRY_WR (TYPE_GMM , 0x21f0 , 0x0000A1F1), + GNB_ENTRY_WR (TYPE_GMM , 0x21ec , 0x0000A1F1), + GNB_ENTRY_WR (TYPE_GMM , 0x21f8 , 0x0000A1E1), + GNB_ENTRY_WR (TYPE_GMM , 0x21f4 , 0x0000A1E1), + GNB_ENTRY_RMW (TYPE_GMM , 0x690 , 0x20000000 , 1 << 29 ), + GNB_ENTRY_RMW (TYPE_GMM , 0x21a8 , 0x4 , 0), +//MC Performance settings base on memory channel configuration, so, move settings to GfxGmcInitializeSequencerTN() +// GNB_ENTRY_WR (TYPE_GMM , 0x2214 , 0x00000003), + GNB_ENTRY_WR (TYPE_GMM , 0x2218 , 0x0000000C), + GNB_ENTRY_WR (GMMx2888_TYPE, GMMx2888_ADDRESS, 0x000007DE), + GNB_ENTRY_WR (GMMx25C8_TYPE, GMMx25C8_ADDRESS, 0x00403932), + GNB_ENTRY_WR (GMMx2114_TYPE, GMMx2114_ADDRESS, 0x00000015), + //2.11 Remove blackout + GNB_ENTRY_WR (GMMx25C0_TYPE, GMMx25C0_ADDRESS, 0x00000000), + GNB_ENTRY_WR (TYPE_GMM , 0x20ec , 0x000001DC), + GNB_ENTRY_WR (TYPE_GMM , 0x20d4 , 0x00000016), + GNB_ENTRY_WR (TYPE_GMM , 0x20ac , 0x00000000), + GNB_ENTRY_RMW (TYPE_GMM , 0x2760 , 0x3 , 1 << 0 ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN [] = { + GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00040c80), + GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00041401), + //In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks + //Implement in GnbCgttOverrideTN + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GfxEnvInitTableTN [] = { + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + TYPE_GMM , + 0xe60 , + 0x0, + (0x1 << 1 ) | (0x1 << 0 ) | + (0x1 << 5 ) | (0x1 << 2 ) | + (0x1 << 7 ) | (0x1 << 6 ) | + (0x1 << 9 ) | (0x1 << 8 ) | + (0x1 << 11 ) | (0x1 << 10 ) | + (0x1 << 14 ) | (0x1 << 13 ) | + (0x1 << 17 ) | (0x1 << 15 ) | + (0x1 << 19 ) | (0x1 << 18 ) | + (0x1 << 24 ) | (0x1 << 20 ) + ), +//--------------------------------------------------------------------------- +// Configure GMC Power Island + GNB_ENTRY_WR ( + D0F0xBC_xE0300004_TYPE, + D0F0xBC_xE0300004_ADDRESS, + (10 << 0 ) | (4 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300000_TYPE, + D0F0xBC_xE0300000_ADDRESS, + (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300000_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300004_TYPE, + D0F0xBC_xE0300004_ADDRESS, + (90 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300000_TYPE, + D0F0xBC_xE0300000_ADDRESS, + (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300000_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300004_TYPE, + D0F0xBC_xE0300004_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300000_TYPE, + D0F0xBC_xE0300000_ADDRESS, + (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300000_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), +// Shutdown GMC if integrated GFX disabled + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x1 + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300000_TYPE, + D0F0xBC_xE0300000_ADDRESS, + (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300000_P1Select_OFFSET) | (1 << D0F0xBC_xE0300000_P2Select_OFFSET) + ), + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300200_TYPE, + D0F0xBC_xE0300200_ADDRESS, + D0F0xBC_xE0300200_P1IsoN_MASK, + 0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), +//--------------------------------------------------------------------------- +// Configure UVD Power Island + GNB_ENTRY_WR ( + D0F0xBC_xE0300040_TYPE, + D0F0xBC_xE0300040_ADDRESS, + (10 << 0 ) | (50 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030003C_TYPE, + D0F0xBC_xE030003C_ADDRESS, + (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | + (2 << D0F0xBC_xE030003C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300040_TYPE, + D0F0xBC_xE0300040_ADDRESS, + (50 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030003C_TYPE, + D0F0xBC_xE030003C_ADDRESS, + (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | + (3 << D0F0xBC_xE030003C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300040_TYPE, + D0F0xBC_xE0300040_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030003C_TYPE, + D0F0xBC_xE030003C_ADDRESS, + (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | (1 << D0F0xBC_xE030003C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), +// Shutdown UVD if integrated GFX disabled + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x1 + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE030003C_TYPE, + D0F0xBC_xE030003C_ADDRESS, + (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_PowerDown_OFFSET) | + (1 << D0F0xBC_xE030003C_P1Select_OFFSET) | (1 << D0F0xBC_xE030003C_P2Select_OFFSET) + ), + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300218_TYPE, + D0F0xBC_xE0300218_ADDRESS, + D0F0xBC_xE0300218_P1IsoN_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300324_TYPE, + D0F0xBC_xE0300324_ADDRESS, + D0F0xBC_xE0300324_UvdPgfsmClockEn_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), +//--------------------------------------------------------------------------- +// Configure VCE Power Island + GNB_ENTRY_WR ( + D0F0xBC_xE0300028_TYPE, + D0F0xBC_xE0300028_ADDRESS, + (10 << 0 ) | (50 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300024_TYPE, + D0F0xBC_xE0300024_ADDRESS, + (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300024_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300028_TYPE, + D0F0xBC_xE0300028_ADDRESS, + (50 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300024_TYPE, + D0F0xBC_xE0300024_ADDRESS, + (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300024_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300028_TYPE, + D0F0xBC_xE0300028_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300024_TYPE, + D0F0xBC_xE0300024_ADDRESS, + (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300024_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), +// Shutdown VCE if integrated GFX disabled + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x1 + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300024_TYPE, + D0F0xBC_xE0300024_ADDRESS, + (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300024_P1Select_OFFSET) | (1 << D0F0xBC_xE0300024_P2Select_OFFSET) + ), + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE030020C_TYPE, + D0F0xBC_xE030020C_ADDRESS, + D0F0xBC_xE030020C_P1IsoN_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300324_TYPE, + D0F0xBC_xE0300324_ADDRESS, + D0F0xBC_xE0300324_VcePgfsmClockEn_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), + +//--------------------------------------------------------------------------- +// Configure DCE Power Island + // Step 1: Take control over DC2 PGFSM. By default display sends power up/down commands. + GNB_ENTRY_WR ( + D0F0xBC_xE03002DC_TYPE, + D0F0xBC_xE03002DC_ADDRESS, + (1 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET) + ), + //Step 2: Read CC_RCU_FUSES register + //If Internal GPU is fused off go to Step 3, ELSE Go to Step 4. + + //Step 3: Enable PGFSM commands during reset + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x1 + ), + //Step 4: + GNB_ENTRY_WR ( + D0F0xBC_xE0300034_TYPE, + D0F0xBC_xE0300034_ADDRESS, + (10 << 0 ) | (50 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300030_TYPE, + D0F0xBC_xE0300030_ADDRESS, + (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300030_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300034_TYPE, + D0F0xBC_xE0300034_ADDRESS, + (50 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300030_TYPE, + D0F0xBC_xE0300030_ADDRESS, + (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300030_WriteOp_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300034_TYPE, + D0F0xBC_xE0300034_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300030_TYPE, + D0F0xBC_xE0300030_ADDRESS, + (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) + ), + GNB_ENTRY_STALL (1), + //Step 5: IF (cc_rcu_fuses.f.gpu_dis == 0x1) Skip Step6 ELSE Go to Step 6 + //Step 6: Disable PGFSM commands during reset. Move to after shutdown DCE. + //Step 7: Release control over DC2 PGFSM. Move to after shutdown DCE. + +// Shutdown DCE if integrated GFX disabled + //Step 1: Take control over DC2 PGFSM. By default display sends power up down commands. + //Step 2: Read CC_RCU_FUSES register + //Step 3: Enable PGFSM commands during reset + //Step 4: Make sure SCLK frequency is below 400Mhz + //Step 5: Enable PGFSM clock + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300324_TYPE, + D0F0xBC_xE0300324_ADDRESS, + D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK, + (1 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET) + ), + //Step 6 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300030_TYPE, + D0F0xBC_xE0300030_ADDRESS, + (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300030_P1Select_OFFSET) | (1 << D0F0xBC_xE0300030_P2Select_OFFSET) + ), + //Step 7 + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300210_TYPE, + D0F0xBC_xE0300210_ADDRESS, + D0F0xBC_xE0300210_P1IsoN_MASK, + (0 << D0F0xBC_xE0300210_P1IsoN_OFFSET) + ), + //Step 8: Restore previous SCLK divider + //Step 9: Wait PSO daughter to be asserted + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + TYPE_D0F0xBC , + 0xe0300210 , + 0x2000 , + (1 << 13 ) + ), + //Step 10: Turn off PGFSM clock + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300324_TYPE, + D0F0xBC_xE0300324_ADDRESS, + D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK, + (0 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET) + ), + //Step 11: Disable PGFSM commands during reset. Same final 2 step as DCE power island + GNB_ENTRY_RMW ( + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03002DC_TYPE, + D0F0xBC_xE03002DC_ADDRESS, + (0 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET) + ), + +//--------------------------------------------------------------------------- +// Configure GFX Power Island + + //Step 3 + GNB_ENTRY_WR ( + D0F0xBC_xE0300058_TYPE, + D0F0xBC_xE0300058_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300054_TYPE, + D0F0xBC_xE0300054_ADDRESS, + (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300054_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300058_TYPE, + D0F0xBC_xE0300058_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300054_TYPE, + D0F0xBC_xE0300054_ADDRESS, + (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300054_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300058_TYPE, + D0F0xBC_xE0300058_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300054_TYPE, + D0F0xBC_xE0300054_ADDRESS, + (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) | + (1 << D0F0xBC_xE0300054_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 4 + GNB_ENTRY_WR ( + D0F0xBC_xE0300074_TYPE, + D0F0xBC_xE0300074_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300070_TYPE, + D0F0xBC_xE0300070_ADDRESS, + (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300070_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300074_TYPE, + D0F0xBC_xE0300074_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300070_TYPE, + D0F0xBC_xE0300070_ADDRESS, + (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300070_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300074_TYPE, + D0F0xBC_xE0300074_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300070_TYPE, + D0F0xBC_xE0300070_ADDRESS, + (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) | + (1 << D0F0xBC_xE0300070_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 5 + GNB_ENTRY_WR ( + D0F0xBC_xE0300090_TYPE, + D0F0xBC_xE0300090_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030008C_TYPE, + D0F0xBC_xE030008C_ADDRESS, + (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) | + (2 << D0F0xBC_xE030008C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300090_TYPE, + D0F0xBC_xE0300090_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030008C_TYPE, + D0F0xBC_xE030008C_ADDRESS, + (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) | + (3 << D0F0xBC_xE030008C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300090_TYPE, + D0F0xBC_xE0300090_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030008C_TYPE, + D0F0xBC_xE030008C_ADDRESS, + (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) | + (1 << D0F0xBC_xE030008C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 6 + GNB_ENTRY_WR ( + D0F0xBC_xE03000AC_TYPE, + D0F0xBC_xE03000AC_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000A8_TYPE, + D0F0xBC_xE03000A8_ADDRESS, + (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) | + (2 << D0F0xBC_xE03000A8_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000AC_TYPE, + D0F0xBC_xE03000AC_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000A8_TYPE, + D0F0xBC_xE03000A8_ADDRESS, + (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) | + (3 << D0F0xBC_xE03000A8_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000AC_TYPE, + D0F0xBC_xE03000AC_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000A8_TYPE, + D0F0xBC_xE03000A8_ADDRESS, + (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) | + (1 << D0F0xBC_xE03000A8_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 7 + GNB_ENTRY_WR ( + D0F0xBC_xE03000C8_TYPE, + D0F0xBC_xE03000C8_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000C4_TYPE, + D0F0xBC_xE03000C4_ADDRESS, + (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) | + (2 << D0F0xBC_xE03000C4_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000C8_TYPE, + D0F0xBC_xE03000C8_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000C4_TYPE, + D0F0xBC_xE03000C4_ADDRESS, + (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) | + (3 << D0F0xBC_xE03000C4_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000C8_TYPE, + D0F0xBC_xE03000C8_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000C4_TYPE, + D0F0xBC_xE03000C4_ADDRESS, + (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) | + (1 << D0F0xBC_xE03000C4_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 8 + GNB_ENTRY_WR ( + D0F0xBC_xE03000E4_TYPE, + D0F0xBC_xE03000E4_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000E0_TYPE, + D0F0xBC_xE03000E0_ADDRESS, + (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) | + (2 << D0F0xBC_xE03000E0_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000E4_TYPE, + D0F0xBC_xE03000E4_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000E0_TYPE, + D0F0xBC_xE03000E0_ADDRESS, + (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) | + (3 << D0F0xBC_xE03000E0_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000E4_TYPE, + D0F0xBC_xE03000E4_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000E0_TYPE, + D0F0xBC_xE03000E0_ADDRESS, + (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) | + (1 << D0F0xBC_xE03000E0_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 9 + GNB_ENTRY_WR ( + D0F0xBC_xE0300100_TYPE, + D0F0xBC_xE0300100_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000FC_TYPE, + D0F0xBC_xE03000FC_ADDRESS, + (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) | + (2 << D0F0xBC_xE03000FC_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300100_TYPE, + D0F0xBC_xE0300100_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000FC_TYPE, + D0F0xBC_xE03000FC_ADDRESS, + (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) | + (3 << D0F0xBC_xE03000FC_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300100_TYPE, + D0F0xBC_xE0300100_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000FC_TYPE, + D0F0xBC_xE03000FC_ADDRESS, + (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) | + (1 << D0F0xBC_xE03000FC_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 10 + GNB_ENTRY_RMW ( + TYPE_D0F0xBC , + 0xe0300328 , + 0x1 | 0x2 | + 0x4 | 0x8 | + 0x10 | 0x20 | + 0x40 , + 0x0 + ), + // Step 12 + GNB_ENTRY_RMW ( + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), +// Shutdown Gfx if integrated GFX disabled + // Step 2 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x1 + ), + // Step 3: Save current SCLK. Make sure SCLK frequency is below 400Mhz + // Step 5 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + TYPE_D0F0xBC , + 0xe0300328 , + 0x1 | 0x2 | + 0x4 | 0x8 | + 0x10 | 0x20 | + 0x40 , + (1 << 0 ) | (1 << 1 ) | + (1 << 2 ) | (1 << 3 ) | + (1 << 4 ) | (1 << 5 ) | + (1 << 6 ) + ), + // Step 6 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300054_TYPE, + D0F0xBC_xE0300054_ADDRESS, + (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300054_P1Select_OFFSET) | (1 << D0F0xBC_xE0300054_P2Select_OFFSET) + ), + // Step 7 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300070_TYPE, + D0F0xBC_xE0300070_ADDRESS, + (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300070_P1Select_OFFSET) | (1 << D0F0xBC_xE0300070_P2Select_OFFSET) + ), + // Step 8 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE030008C_TYPE, + D0F0xBC_xE030008C_ADDRESS, + (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_PowerDown_OFFSET) | + (1 << D0F0xBC_xE030008C_P1Select_OFFSET) | (1 << D0F0xBC_xE030008C_P2Select_OFFSET) + ), + // Step 9 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03000A8_TYPE, + D0F0xBC_xE03000A8_ADDRESS, + (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_PowerDown_OFFSET) | + (1 << D0F0xBC_xE03000A8_P1Select_OFFSET) | (1 << D0F0xBC_xE03000A8_P2Select_OFFSET) + ), + // Step 10 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03000C4_TYPE, + D0F0xBC_xE03000C4_ADDRESS, + (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_PowerDown_OFFSET) | + (1 << D0F0xBC_xE03000C4_P1Select_OFFSET) | (1 << D0F0xBC_xE03000C4_P2Select_OFFSET) + ), + // Step 11 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03000E0_TYPE, + D0F0xBC_xE03000E0_ADDRESS, + (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_PowerDown_OFFSET) | + (1 << D0F0xBC_xE03000E0_P1Select_OFFSET) | (1 << D0F0xBC_xE03000E0_P2Select_OFFSET) + ), + // Step 12 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03000FC_TYPE, + D0F0xBC_xE03000FC_ADDRESS, + (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_PowerDown_OFFSET) | + (1 << D0F0xBC_xE03000FC_P1Select_OFFSET) | (1 << D0F0xBC_xE03000FC_P2Select_OFFSET) + ), + // Step 13 + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03002F4_TYPE, + D0F0xBC_xE03002F4_ADDRESS, + 0xFFFFFFFF, + 0 + ), + // Step 14 + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03002F0_TYPE, + D0F0xBC_xE03002F0_ADDRESS, + 0xFFFFFFFF, + 0 + ), + // Step 15: Restore SCLK that is saved in step 4 + // Step 16 + GNB_ENTRY_FULL_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */, + D0F0xBC_xE03002FC_TYPE, + D0F0xBC_xE03002FC_ADDRESS, + 0xFFFFFFFF, + 0x3FFFFFFF + ), + // Step 17 + GNB_ENTRY_FULL_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */, + D0F0xBC_xE03002E4_TYPE, + D0F0xBC_xE03002E4_ADDRESS, + 0xFFFFFFFF, + 0x3FFFF + ), + // Step 18 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + TYPE_D0F0xBC , + 0xe0300328 , + 0x1 | 0x2 | + 0x4 | 0x8 | + 0x10 | 0x20 | + 0x40 , + 0 + ), + // Step 19 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), +//--------------------------------------------------------------------------- +// Isolate DC, SYS and CP tile when Internal Graphics is disabled + // Step 2: Reduce SCLK frequency to 100Mhz. Save current SCLK divider. + // Step 3 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003034_TYPE, + D0F0xBC_xE0003034_ADDRESS, + D0F0xBC_xE0003034_SysIso_MASK | D0F0xBC_xE0003034_CpIso_MASK | + D0F0xBC_xE0003034_Dc0Iso_MASK | D0F0xBC_xE0003034_Dc1Iso_MASK | + D0F0xBC_xE0003034_DciIso_MASK | D0F0xBC_xE0003034_DcipgIso_MASK, + (1 << D0F0xBC_xE0003034_SysIso_OFFSET) | (1 << D0F0xBC_xE0003034_CpIso_OFFSET) | + (1 << D0F0xBC_xE0003034_Dc0Iso_OFFSET) | (1 << D0F0xBC_xE0003034_Dc1Iso_OFFSET) | + (1 << D0F0xBC_xE0003034_DciIso_OFFSET) | (1 << D0F0xBC_xE0003034_DcipgIso_OFFSET) + ), + //Step 4: Restore pervious SCLK frequency + +//--------------------------------------------------------------------------- +// For IOMMU add logic of GfxDis + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F2xF4_x57_TYPE, + D0F2xF4_x57_ADDRESS, + D0F2xF4_x57_L1ImuIntGfxDis_MASK, + (0x1 << D0F2xF4_x57_L1ImuIntGfxDis_OFFSET) + ), + + GNB_ENTRY_TERMINATE +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c new file mode 100644 index 0000000000..b8dc935f43 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c @@ -0,0 +1,353 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe early post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbBapmCoeffCalcTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "GnbInitTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBBAPMCOEFFCALC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +#define GnbFpLibGetExp(V) ((INT32) ((*((UINT64*) &Value) >> 52) & 0x7FF) - (1023 + 52)) +#define GnbFpLibGetMnts(V) (INT64) ((*((UINT64*) &Value) & ((1ull << 52) - 1)) | (1ull << 52)) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +INT32 _fltused = 0; + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate power of + * + * + * @param[in] Value value + * @param[in] Pow power + * @retval Value^Pow + */ + +STATIC DOUBLE +GnbBapmPowerOf ( + IN DOUBLE Value, + IN UINTN Pow + ) +{ + DOUBLE Result; + Result = Value; + while ( --Pow > 0) { + Result *= Value; + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Decode R from fuse + * + * + * @param[in] FuseR R fused value + * @retval R + */ +STATIC DOUBLE +GnbBapmDecodeR ( + IN UINT32 FuseR + ) +{ + DOUBLE Value; + Value = ((DOUBLE) (FuseR & 0x1ff)) / (2 << (8 - 1)); + Value = GnbBapmPowerOf (Value, 4); + return ((FuseR & 0x200) != 0) ? (-1) * Value : Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Decode Tau from fuse + * + * + * @param[in] FuseTau Tau fused value + * @retval Tau + */ +STATIC DOUBLE +GnbBapmDecodeTau ( + IN UINT32 FuseTau + ) +{ + DOUBLE Value; + Value = FuseTau; + Value = GnbBapmPowerOf (Value / (2 << (9 - 1)), 16); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Calaculate X + * + * + * @param[in] Ts Samplig rate + * @param[in] Tau Tau value + * @param[in] R R value + * @retval X + */ +STATIC DOUBLE +GnbBapmCalculateX ( + IN DOUBLE Ts, + IN DOUBLE Tau, + IN DOUBLE R + ) +{ + //X=(R*Ts)/(2*Tau+Ts); + DOUBLE Result; + Result = (R * Ts) / (2 * Tau + Ts); + return (Result * GnbBapmPowerOf (2, 36)) + 0.5; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Calaculate Y + * + * + * @param[in] Ts Samplig rate + * @param[in] Tau Tau value + * @retval Y + */ +STATIC DOUBLE +GnbBapmCalculateY ( + IN DOUBLE Ts, + IN DOUBLE Tau + ) +{ + //Y=(2*Tau-Ts)/(2*Tau+Ts); + DOUBLE Result; + Result = (2 * Tau - Ts) / (2 * Tau + Ts); + return (Result * GnbBapmPowerOf (2, 32)) + 0.5; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set X & Y value + * + * + * @param[in] X X value + * @param[in] Y Y value + * @param[in] AddrOffset Offset of address + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbBapmSetYAndX ( + IN INT32 X, + IN INT32 Y, + IN UINT32 AddrOffset, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbRegisterWriteTN ( + D0F0xBC_x1F480_TYPE, + D0F0xBC_x1F480_ADDRESS + AddrOffset, + &X, + 0, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "X: 0x%08x\n", X); + GnbRegisterWriteTN ( + D0F0xBC_x1F480_TYPE, + D0F0xBC_x1F480_ADDRESS + AddrOffset + 4, + &Y, + 0, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "Y: 0x%08x\n", Y); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Extract INt32 from DOUBLE + * + * + * + * @param[in] Value Double value + * @retval int32 + */ +INT32 +GnbFpLibDoubleToInt32 ( + IN DOUBLE Value + ) +{ + INT64 Mantissa; + INT32 Exponent; + Mantissa = GnbFpLibGetMnts (Value); + Exponent = GnbFpLibGetExp (Value); + if (Exponent < -64) { + Mantissa = 0; + } else if (Exponent < 0) { + Mantissa >>= - Exponent; + } else { + Mantissa <<= Exponent; + } + return (INT32) ((Value < 0) ? - Mantissa : Mantissa); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Calcuate BAPM coefficient + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +VOID +GnbBapmCalculateCoeffsTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RFuse1; + UINT32 TauFuse1; + UINT32 Index; + DOUBLE R; + DOUBLE Tau; + DOUBLE Ts; + INT32 X; + INT32 Y; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmCalculateCoeffsTN Enter\n"); + + LibAmdFinit (); + + Ts = ((DOUBLE) (D0F0xBC_x1F468_TimerPeriod_Value * D0F0xBC_x1F46C_BapmPeriod_Value) / 100) / 1000000; + + for (Index = 0; Index < 15; Index++) { + GnbRegisterReadTN ( + TYPE_D0F0xBC , + 0xe01040c4 + Index * 4, + &RFuse1, + 0, + StdHeader + ); + GnbRegisterReadTN ( + TYPE_D0F0xBC , + 0xe01040c4 + (Index + 15) * 4, + &TauFuse1, + 0, + StdHeader + ); + + R = GnbBapmDecodeR (RFuse1 & 0x3FF); + Tau = GnbBapmDecodeTau (TauFuse1 & 0x3FF); + + X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R)); + Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau)); + GnbBapmSetYAndX (X, Y, Index * 2 * 4, StdHeader); + + R = GnbBapmDecodeR ((RFuse1 >> 10) & 0x3FF); + Tau = GnbBapmDecodeTau ((TauFuse1 >> 10) & 0x3FF); + + X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R)); + Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau)); + + GnbBapmSetYAndX (X, Y, (Index * 2 + 30) * 4 , StdHeader); + + R = GnbBapmDecodeR ((RFuse1 >> 20) & 0x3FF); + Tau = GnbBapmDecodeTau ((TauFuse1 >> 20) & 0x3FF); + + X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R)); + Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau)); + + GnbBapmSetYAndX (X, Y, (Index * 2 + 60) * 4 , StdHeader); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmCalculateCoeffsTN Exit\n"); +} + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h new file mode 100644 index 0000000000..3ed7b4807f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB CAC weights table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBBAPMCOEFFCALCTN_H_ +#define _GNBBAPMCOEFFCALCTN_H_ + +typedef double DOUBLE; + +VOID +GnbBapmCalculateCoeffsTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +INT32 +GnbFpLibDoubleToInt32 ( + IN DOUBLE Value + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h new file mode 100644 index 0000000000..bf17ad1601 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h @@ -0,0 +1,175 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB CAC weights table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBCACWEIGHTSTABLETN_H_ +#define _GNBCACWEIGHTSTABLETN_H_ + +UINT32 CacWeightsTN[] = { + 0xD65, + 0x289A, + 0x289A, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x16F, + 0x0, + 0x0, + 0x0, + 0x0, + 0x16A5, + 0x592, + 0x0, + 0x0, + 0xE60, + 0x0, + 0xE60, + 0x0, + 0xE60, + 0x0, + 0xE60, + 0x0, + 0xE60, + 0x0, + 0xE60, + 0xEC9, + 0xEC9, + 0x41A, + 0x41A, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0xF15, + 0xF15, + 0xF15, + 0xF15, + 0xF15, + 0xF15, + 0x79, + 0x79, + 0x79, + 0x0, + 0x0, + 0x0, + 0x0, + 0x3F2, + 0x3F2, + 0x0, + 0x0, + 0x123, + 0x0, + 0x0, + 0x0, + 0x123, + 0x0, + 0x0, + 0x0, + 0x0, + 0x195B, + 0x629, + 0x0, + 0x0, + 0x195B, + 0x629, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x755, + 0x0, + 0x755, + 0x0, + 0x755, + 0x0, + 0x755, + 0x0, + 0x755, + 0x0, + 0x755, + 0x0, + 0x88B, + 0x1206, + 0x0, + 0x88B, + 0x1206, + 0x0, + 0x0 +}; + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c new file mode 100644 index 0000000000..b3b3101072 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c @@ -0,0 +1,888 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe early post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 64732 $ @e \$Date: 2012-01-30 02:16:26 -0600 (Mon, 30 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbTable.h" +#include "GnbNbInitLibV4.h" +#include "GnbSmuFirmwareTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "GfxLibTN.h" +#include "GnbCacWeightsTN.h" +#include "cpuFamilyTranslation.h" +#include "GnbHandleLib.h" +#include "GnbBapmCoeffCalcTN.h" +#include "GnbInitTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_TABLE ROMDATA GnbEarlyInitTableTN []; +extern GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN []; +extern GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN []; +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbEarlierInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader +); +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb TN Decrease all of the SMU VIDs by 4 (+25mV) + + * + * + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbAdjustSmuVidBeforeSmuTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_xE0001008_STRUCT D0F0xBC_xE0001008; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidBeforeSmuTN Enter\n"); + + GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader); + D0F0xBC_xE0001008.Field.SClkVid3 -= 4; + D0F0xBC_xE0001008.Field.SClkVid2 -= 4; + D0F0xBC_xE0001008.Field.SClkVid1 -= 4; + D0F0xBC_xE0001008.Field.SClkVid0 -= 4; + GnbRegisterWriteTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidBeforeSmuTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb TN Decrease all of the SMU VIDs by 4 (+25mV) + + * + * + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbAdjustSmuVidAfterSmuTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F88C_STRUCT D0F0xBC_x1F88C; + D0F0xBC_x1F8DC_STRUCT D0F0xBC_x1F8DC; + D0F0xBC_x1F8E0_STRUCT D0F0xBC_x1F8E0; + D0F0xBC_x1F8E4_STRUCT D0F0xBC_x1F8E4; + D0F0xBC_x1F8E8_STRUCT D0F0xBC_x1F8E8; + D0F0xBC_x1F400_STRUCT D0F0xBC_x1F400; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidAfterSmuTN Enter\n"); + + //Adjust SMU VIDs + GnbRegisterReadTN (D0F0xBC_x1F88C_TYPE, D0F0xBC_x1F88C_ADDRESS, &D0F0xBC_x1F88C, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F8E0_TYPE, D0F0xBC_x1F8E0_ADDRESS, &D0F0xBC_x1F8E0, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F8E4_TYPE, D0F0xBC_x1F8E4_ADDRESS, &D0F0xBC_x1F8E4, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F8E8_TYPE, D0F0xBC_x1F8E8_ADDRESS, &D0F0xBC_x1F8E8, 0, StdHeader); + + D0F0xBC_x1F88C.Field.NbVid_3 -= 4; + D0F0xBC_x1F88C.Field.NbVid_2 -= 4; + D0F0xBC_x1F88C.Field.NbVid_1 -= 4; + D0F0xBC_x1F88C.Field.NbVid_0 -= 4; + + D0F0xBC_x1F8DC.Field.SClkVid3 -= 4; + D0F0xBC_x1F8DC.Field.SClkVid2 -= 4; + D0F0xBC_x1F8DC.Field.SClkVid1 -= 4; + D0F0xBC_x1F8DC.Field.SClkVid0 -= 4; + D0F0xBC_x1F8E0.Field.BapmSclkVid_2 -= 4; + D0F0xBC_x1F8E0.Field.BapmSclkVid_1 -= 4; + D0F0xBC_x1F8E0.Field.BapmSclkVid_0 -= 4; + D0F0xBC_x1F8E4.Field.BapmNbVid_1 -= 4; + D0F0xBC_x1F8E4.Field.BapmNbVid_0 -= 4; + D0F0xBC_x1F8E4.Field.BapmSclkVid_3 -= 4; + D0F0xBC_x1F8E8.Field.BapmNbVid_3 -= 4; + D0F0xBC_x1F8E8.Field.BapmNbVid_2 -= 4; + + GnbRegisterWriteTN (D0F0xBC_x1F88C_TYPE, D0F0xBC_x1F88C_ADDRESS, &D0F0xBC_x1F88C, 0, StdHeader); + GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC, 0, StdHeader); + GnbRegisterWriteTN (D0F0xBC_x1F8E0_TYPE, D0F0xBC_x1F8E0_ADDRESS, &D0F0xBC_x1F8E0, 0, StdHeader); + GnbRegisterWriteTN (D0F0xBC_x1F8E4_TYPE, D0F0xBC_x1F8E4_ADDRESS, &D0F0xBC_x1F8E4, 0, StdHeader); + GnbRegisterWriteTN (D0F0xBC_x1F8E8_TYPE, D0F0xBC_x1F8E8_ADDRESS, &D0F0xBC_x1F8E8, 0, StdHeader); + + //D0F0xBC_x1F400[SviLoadLineOffsetVddNB]=01b (-25mV) + GnbRegisterReadTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader); + D0F0xBC_x1F400.Field.SviLoadLineOffsetVddNB = 1; + GnbRegisterWriteTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader); + + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidAfterSmuTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb SMU LHTC support + * + * Part of BAPM enablement. + * When BAPM is disabled in battery mode firmware will enable LHTC. + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbBapmLhtcInitTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F638_STRUCT D0F0xBC_x1F638; + D0F0xBC_x1F428_STRUCT D0F0xBC_x1F428; + D0F0xBC_x1F86C_STRUCT D0F0xBC_x1F86C; + D0F0xBC_x1F628_STRUCT D0F0xBC_x1F628; + D0F0xBC_xE0104188_STRUCT D0F0xBC_xE0104188; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmLhtcInitTN Enter\n"); + + GnbRegisterReadTN (D0F0xBC_x1F638_TYPE, D0F0xBC_x1F638_ADDRESS, &D0F0xBC_x1F638, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader); + + //1. Set HTC period to 10 in PM_TIMERS_2 register + //Still need to keep PM_CONFIG.Enable_HTC_Limit to 0 + D0F0xBC_x1F428.Field.field_4 = 0; + GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + D0F0xBC_x1F638.Field.HtcPeriod = 10; + GnbRegisterWriteTN (D0F0xBC_x1F638_TYPE, D0F0xBC_x1F638_ADDRESS, &D0F0xBC_x1F638, 0, StdHeader); + + //2. Read BapmLhtcCap fuse + GnbRegisterReadTN (D0F0xBC_x1F86C_TYPE, D0F0xBC_x1F86C_ADDRESS, &D0F0xBC_x1F86C, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F628_TYPE, D0F0xBC_x1F628_ADDRESS, &D0F0xBC_x1F628, 0, StdHeader); + if (D0F0xBC_x1F86C.Field.BapmLhtcCap == 0) { + D0F0xBC_x1F628.Field.HtcActivePstateLimit = 0; + } else { + D0F0xBC_x1F628.Field.HtcActivePstateLimit = D0F0xBC_xE0104188.Field.LhtcPstateLimit; + } + GnbRegisterWriteTN (D0F0xBC_x1F628_TYPE, D0F0xBC_x1F628_ADDRESS, &D0F0xBC_x1F628, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmLhtcInitTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Measured temperature with BAPM + * + * + * + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbBapmMeasuredTempTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F428_STRUCT D0F0xBC_x1F428; + D0F0xBC_xE0104188_STRUCT D0F0xBC_xE0104188; + D0F0xBC_x1F844_STRUCT D0F0xBC_x1F844; + D0F0xBC_x1F848_STRUCT D0F0xBC_x1F848; + D0F0xBC_x1F84C_STRUCT D0F0xBC_x1F84C; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmMeasuredTempTN Enter\n"); + + GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader); + + //Measured temperature with BAPM + GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + D0F0xBC_x1F428.Field.line180 = 0; + if (D0F0xBC_xE0104188.Field.BapmMeasuredTemp == 1) { + D0F0xBC_x1F844.Value = 0x38B; + GnbRegisterWriteTN (D0F0xBC_x1F844_TYPE, D0F0xBC_x1F844_ADDRESS, &D0F0xBC_x1F844, 0, StdHeader); + D0F0xBC_x1F848.Value = 0x38D; + GnbRegisterWriteTN (D0F0xBC_x1F848_TYPE, D0F0xBC_x1F848_ADDRESS, &D0F0xBC_x1F848, 0, StdHeader); + D0F0xBC_x1F84C.Value = 0x389; + GnbRegisterWriteTN (D0F0xBC_x1F84C_TYPE, D0F0xBC_x1F84C_ADDRESS, &D0F0xBC_x1F84C, 0, StdHeader); + + D0F0xBC_x1F428.Field.line180 = 1; + } + GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmMeasuredTempTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb SMU LHTC Enable + * + * Part of BAPM enablement. + * When BAPM is disabled in battery mode firmware will enable LHTC. + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbLhtcEnableTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F428_STRUCT D0F0xBC_x1F428; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLhtcEnableTN Enter\n"); + + GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + D0F0xBC_x1F428.Field.field_4 = 1; + GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLhtcEnableTN Exit\n"); +} +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb TN Update BAPMTI_TjOffset + * + * + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbTjOffsetUpdateTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F870_STRUCT D0F0xBC_x1F870; + + CPU_LOGICAL_ID LogicalId; + GNB_HANDLE *GnbHandle; + D0F0xBC_xE0104040_STRUCT D0F0xBC_xE0104040; + D0F0xBC_x1F85C_STRUCT D0F0xBC_x1F85C; + ex1075_STRUCT ex1075 ; + UINT32 TimerPeriod; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Enter\n"); + + + TimerPeriod = D0F0xBC_x1F468_TimerPeriod_Value; + GnbRegisterReadTN (D0F0xBC_x1F85C_TYPE, D0F0xBC_x1F85C_ADDRESS, &D0F0xBC_x1F85C, 0, StdHeader); + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe010413c , &ex1075, 0, StdHeader); + // Determine desired AgingRate: + // PM_FUSES4.TdpAgeRate * Fuse[BAPMTI_Ts] (encoded in us) + // Re-encode TdpAgeRate with 1ms BAPM interval + D0F0xBC_x1F85C.Field.TdpAgeRate = (D0F0xBC_x1F85C.Field.TdpAgeRate * ex1075.Field.ex1075_0 ) / (TimerPeriod / 100); + GnbRegisterWriteTN (D0F0xBC_x1F85C_TYPE, D0F0xBC_x1F85C_ADDRESS, &D0F0xBC_x1F85C, 0, StdHeader); + + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader); + if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) { + IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %x, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision); + return; + } + GnbRegisterReadTN (D0F0xBC_xE0104040_TYPE, D0F0xBC_xE0104040_ADDRESS, &D0F0xBC_xE0104040, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader); + //9900h=FS1r2/FP2 Devastator + //9903h=FS1r2/FP2 Devastator Lite + //9990h=FS1r2/FP2 Scrapper + //9901h=FM2 Devastator + //9904h=FM2 Devastator Lite + //9991h=FM2 Scrapper + if ((D0F0xBC_xE0104040.Field.DeviceID == 0x9900) || (D0F0xBC_xE0104040.Field.DeviceID == 0x9903)) { + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0 = 0x26; + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1 = 0x26; + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2 = 0x26; + } else if (D0F0xBC_xE0104040.Field.DeviceID == 0x9990) { + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0 = 0x2E; + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1 = 0x2E; + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2 = 0x2E; + } else { + IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Skip DID- %x\n", D0F0xBC_xE0104040.Field.DeviceID); + } + GnbRegisterWriteTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * GPU CAC enablement and weights programming + * + * + * + * @param[in] StdHeader Standard configuration header + */ + +STATIC VOID +GnbCacEnablement ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F464_STRUCT D0F0xBC_x1F464; + ex1071_STRUCT ex1071 ; + ex1072_STRUCT ex1072 ; + PCI_ADDR PciAddress; + UINT8 Index; + ex1073_STRUCT ex1073 ; + D18F5x160_STRUCT D18F5x160; + DOUBLE UnbCac; + GMMx898_STRUCT GMMx898; + + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072, 0, StdHeader); + ex1072.Field.ex1072_2 = 0x29; + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f920 , &ex1072, 0, StdHeader); + + //UNB_CAC_VALUE.UNB_CAC = 2.3734E-04 * FNBPS0 (in MHz) * 2^GPU_CAC_AVRG_CNTL.WEIGHT_PREC + GnbRegisterReadTN (D18F5x160_TYPE, D18F5x160_ADDRESS, &D18F5x160.Value, 0, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "NBP0 10khz %x (%d)\n", GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid), GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid)); + UnbCac = 0.00000204831536 * (1 << ex1072.Field.ex1072_0 ) * GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid); + ex1073.Field.ex1073_0 = (UINT32) GnbFpLibDoubleToInt32 (UnbCac); + IDS_HDT_CONSOLE (GNB_TRACE, "UnbCac %x (%d)\n", ex1073.Field.ex1073_0 , ex1073.Field.ex1073_0 ); + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f91c , &ex1073.Value, 0, StdHeader); + + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f160 , &ex1071, 0, StdHeader); + ex1071.Field.ex1071_0 = 0x1; + ex1071.Field.ex1071_3 = 0x4; + ex1071.Field.ex1071_4 = 0x25; + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f160 , &ex1071, 0, StdHeader); + + GnbRegisterReadTN (GMMx898_TYPE, GMMx898_ADDRESS, &GMMx898, 0, StdHeader); + GMMx898.Field.Threshold = 0x31; + GnbRegisterWriteTN (GMMx898_TYPE, GMMx898_ADDRESS, &GMMx898, 0, StdHeader); + + // Set CAC/TDP interval + GnbRegisterReadTN (D0F0xBC_x1F464_TYPE, D0F0xBC_x1F464_ADDRESS, &D0F0xBC_x1F464, 0, StdHeader); + D0F0xBC_x1F464.Field.TdpCntl = 1; + GnbRegisterWriteTN (D0F0xBC_x1F464_TYPE, D0F0xBC_x1F464_ADDRESS, &D0F0xBC_x1F464, 0, StdHeader); + + // Program GPU CAC weights + + for (Index = 0; Index < (sizeof (CacWeightsTN) / sizeof (CacWeightsTN[0])); Index++) { + GnbRegisterWriteTN (TYPE_D0F0xBC , (0x1f9a0 + (Index * 4)), &CacWeightsTN[Index], 0, StdHeader); + } + + // Call BIOS service SMC_MSG_CONFIG_TDP_CNTL + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + GnbSmuServiceRequestV4 ( + PciAddress, + SMC_MSG_CONFIG_TDP_CNTL, + 0, + StdHeader + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Decode power of CPU out of Watt + * + * + * + * @param[in] Encode PwrCpu encode + * @param[in] StdHeader Standard Configuration Header + * @retval mWatt + */ +STATIC INT32 +CpuPowerDecode ( + IN UINT8 Encode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + INT32 Power; + ex1002_STRUCT ex1002 ; + + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f850 , &ex1002, 0, StdHeader); + + //TdpWatt = TdpWattEncode / 1024 + //PwrCpu / TdpWatt = Encode + //PwrCpu = Encode * TdpWattEncode / 1024 + + Power = (INT32) ((Encode * ex1002.Field.ex1002_0 *1000) / 1024); + + return Power; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Encode the offset of power of CPU + * + * + * + * @param[in] NewPower New power of mWatt + * @param[in] OrgPower Original power of mWatt + * @param[in] StdHeader Standard Configuration Header + * @retval Encode + */ +STATIC UINT8 +CpuPowerOffsetEncode ( + IN INT32 NewPower, + IN INT32 OrgPower, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + INT8 PowerOffsetEncode; + INT32 PowerOffset; + ex1002_STRUCT ex1002 ; + BOOLEAN Postive; + + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f850 , &ex1002, 0, StdHeader); + if (NewPower > OrgPower) { + PowerOffset = NewPower - OrgPower; + Postive = TRUE; + } else { + PowerOffset = OrgPower - NewPower; + Postive = FALSE; + } + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu New Pwr %x (%d)\n", NewPower, NewPower); + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu org Pwr %x (%d)\n", OrgPower, OrgPower); + IDS_HDT_CONSOLE (GNB_TRACE, "Tdp2Watt %x, (%d)\n", ex1002.Field.ex1002_0 , ex1002.Field.ex1002_0 ); + //Ceil of (mWatt *1024 / TdpWattEncode) / 1000 = Encode in watt + PowerOffset = (((PowerOffset * 1024) / ex1002.Field.ex1002_0 ) + 500) / 1000; + + if (Postive) { + PowerOffsetEncode = (INT8) PowerOffset; + } else { + PowerOffsetEncode = 0 - (INT8) PowerOffset; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PowerOffsetEncode %x\n", PowerOffsetEncode); + return (UINT8) PowerOffsetEncode; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Decode power of GPU out of Watt + * + * + * + * @param[in] Encode PwrGpu encode + * @param[in] StdHeader Standard Configuration Header + * @retval mWatt + */ +STATIC INT16 +GpuPowerDecode ( + IN UINT16 Encode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + INT16 Power; + + Power = (INT16) Encode; + + + return Power; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Decode Max Tj + * + * + * + * @param[in] Encode Tj encode + * @retval 100 x Tj + */ +STATIC INT16 +TjMaxDecode ( + IN UINT8 Encode + ) +{ + INT16 TjMax; + + TjMax = (INT16) Encode; + + return (TjMax * 100); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * for BAPMTI_TjOffset decoding + * + * + * + * @param[in] Encode Tj encode + * @retval 100 x Tjoffset + */ +STATIC INT16 +TjOffsetDecode ( + IN UINT8 Encode + ) +{ + UINT16 Number; + UINT8 Floating; + BOOLEAN Postive; + UINT8 TjOffsetEncode; + + TjOffsetEncode = Encode; + Postive = TRUE; + + if (Encode == 0) { + return 0; + } + + if ((TjOffsetEncode & 0x80) != 0) { + Postive = FALSE; + TjOffsetEncode = (UINT8) (~(Encode - 1)); + } + + Number = ((TjOffsetEncode >> 2) & 0x1F) * 100; + + Floating = (TjOffsetEncode & 0x3); + if (Floating == 1) { + Number += 25; + } else if (Floating == 2) { + Number += 50; + } else if (Floating == 3) { + Number += 75; + } else { + } + + if (Postive) { + return (INT16) Number; + } else { + return (INT16) (0 - Number); + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Trinity SMU supports a software-writeable TjOffset (called swTjOffset) that can be programmed to + * account for underspec thermal solutions. + * There is a mechanism for customers to adjust TjOffset (via BAPM_PARAMETERS3.TjOffset) + * for under-performing thermal solutions. + * BIOS will adjust NomPow/MidPow/MaxPow based on this software-programmable TjOffset (called swTjOffset). + * SMU firmware will add this value to Fuse[TjOffset] for all TE's during BAPM calculations. + * + * Tj stands for junction temperature of the processor. However, here is a general description of + * our software-programmable TjOffset for BAPM (Birdirectional Application Power Management): + * "swTjOffset is an adjustable offset for BAPM thermal calculations to account for changes in + * junction temperature, TjOffset. For further details, see Thermal Guide." + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbSoftwareTjOffsetTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F860_STRUCT D0F0xBC_x1F860; + D0F0xBC_x1F864_STRUCT D0F0xBC_x1F864; + ex999_STRUCT ex999 ; + D0F0xBC_x1F870_STRUCT D0F0xBC_x1F870; + ex1000_STRUCT ex1000 ; + ex1001_STRUCT ex1001 ; + + ex996_STRUCT ex996; + ex997_STRUCT ex997 ; + D0F0xBC_x1F6B4_STRUCT D0F0xBC_x1F6B4; + ex998_STRUCT ex998 ; + INT8 SwTjOffset; + INT16 Delta_T_org; + INT16 Delta_T_new; + INT32 Cpu_New_Pwr; + INT32 Gpu_New_Pwr; + + SwTjOffset = (INT8) UserOptions.CfgGnbSwTjOffset; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSoftwareTjOffsetTN Enter\n"); + + IDS_OPTION_HOOK (IDS_GNB_PMM_SWTJOFFSET, &SwTjOffset, StdHeader); + if (SwTjOffset == 0) { + return; + } + + IDS_HDT_CONSOLE (GNB_TRACE, "User Input Tj Offset %x\n", SwTjOffset); + GnbRegisterReadTN (D0F0xBC_x1F860_TYPE, D0F0xBC_x1F860_ADDRESS, &D0F0xBC_x1F860, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F864_TYPE, D0F0xBC_x1F864_ADDRESS, &D0F0xBC_x1F864, 0, StdHeader); + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f868 , &ex999, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader); + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f898 , &ex1000, 0, StdHeader); + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f8c0 , &ex1001, 0, StdHeader); + + //Tjoffset_new = Tjoffset_org + SwTjOffset + //Delta_T_org = T_die - Tjoffset_org - 45 + + //Delta_T_new = T_die - Tjoffset_new - 45 + // = T_die - (Tjoffset_org + SwTjOffset) - 45 + // = T_die - Tjoffset_org - SwTjOffset - 45 + + //Pwr_new = Pwr_org * (Delta_T_new/Delta_T_org) + // = Pwr_org * (T_org - TjOffset) / T_org + + //Cpu0 + Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_0) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0) - 4500; + Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_0) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0) - (SwTjOffset * 100) - 4500; + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu0 Delta T org %x (%d)\n", Delta_T_org, Delta_T_org); + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu0 Delta T New %x (%d)\n", Delta_T_new, Delta_T_new); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_3 , StdHeader) * Delta_T_new) / Delta_T_org; + ex996.Field.ex996_2 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_3 , StdHeader), StdHeader); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_2 , StdHeader) * Delta_T_new) / Delta_T_org; + ex996.Field.ex996_3 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_2 , StdHeader), StdHeader); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex1001.Field.ex1001_2 , StdHeader) * Delta_T_new) / Delta_T_org; + ex998.Field.ex998_2 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex1001.Field.ex1001_2 , StdHeader), StdHeader); + + //Cpu1 + Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_1) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1) - 4500; + Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_1) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1) - (SwTjOffset * 100) - 4500; + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu1 Delta T org %x (%d)\n", Delta_T_org, Delta_T_org); + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu1 Delta T New %x (%d)\n", Delta_T_new, Delta_T_new); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_1 , StdHeader) * Delta_T_new) / Delta_T_org; + ex996.Field.ex996_0 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_1, StdHeader), StdHeader); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_0 , StdHeader) * Delta_T_new) / Delta_T_org; + ex996.Field.ex996_1 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_0 , StdHeader), StdHeader); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex1001.Field.ex1001_1 , StdHeader) * Delta_T_new) / Delta_T_org; + ex998.Field.ex998_1 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex1001.Field.ex1001_1 , StdHeader), StdHeader); + + //GPU + Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F864.Field.BAPMTI_GpuTjMax) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2) - 4500; + Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F864.Field.BAPMTI_GpuTjMax) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2) - (SwTjOffset * 100) - 4500; + IDS_HDT_CONSOLE (GNB_TRACE, "Gpu Delta T org %x (%d)\n", Delta_T_org, Delta_T_org); + IDS_HDT_CONSOLE (GNB_TRACE, "Gpu Delta T New %x (%d)\n", Delta_T_new, Delta_T_new); + Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1000.Field.ex1000_1 , StdHeader) * Delta_T_new) / Delta_T_org; + ex997.Field.ex997_0 = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1000.Field.ex1000_1 , StdHeader)); + Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1000.Field.ex1000_0 , StdHeader) * Delta_T_new) / Delta_T_org; + ex997.Field.ex997_1 = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1000.Field.ex1000_0 , StdHeader)); + Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1001.Field.ex1001_0 , StdHeader) * Delta_T_new) / Delta_T_org; + ex998.Field.ex998_0 = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1001.Field.ex1001_0 , StdHeader)); + + //SwTjOffset + D0F0xBC_x1F6B4.Field.TjOffset = SwTjOffset; + + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f6ac , &ex996, 0, StdHeader); + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f6b0 , &ex997, 0, StdHeader); + GnbRegisterWriteTN (D0F0xBC_x1F6B4_TYPE, D0F0xBC_x1F6B4_ADDRESS, &D0F0xBC_x1F6B4, 0, StdHeader); + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1F6B8 , &ex998, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSoftwareTjOffsetTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init TDC + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +STATIC VOID +GnbInitTdc ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_EARLY_PARAMS *EarlyParams; + D0F0xBC_x1F62C_STRUCT D0F0xBC_x1F62C; + D0F0xBC_x1F840_STRUCT D0F0xBC_x1F840; + + EarlyParams = (AMD_EARLY_PARAMS *) StdHeader; + D0F0xBC_x1F62C.Field.Idd = EarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit / 10; + D0F0xBC_x1F62C.Field.Iddnb = EarlyParams->PlatformConfig.VrmProperties[NbVrm].CurrentLimit / 10; + GnbRegisterWriteTN (D0F0xBC_x1F62C_TYPE, D0F0xBC_x1F62C_ADDRESS, &D0F0xBC_x1F62C, 0, StdHeader); + + D0F0xBC_x1F840.Field.IddspikeOCP = EarlyParams->PlatformConfig.VrmProperties[CoreVrm].SviOcpLevel / 10; + D0F0xBC_x1F840.Field.IddNbspikeOCP = EarlyParams->PlatformConfig.VrmProperties[NbVrm].SviOcpLevel / 10; + GnbRegisterWriteTN (D0F0xBC_x1F840_TYPE, D0F0xBC_x1F840_ADDRESS, &D0F0xBC_x1F840, 0, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GNB_HANDLE *GnbHandle; + UINT32 Property; + D0F0xBC_xE0104188_STRUCT D0F0xBC_xE0104188; + + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceTN Enter\n"); + Property = TABLE_PROPERTY_DEAFULT; + + //Check fuse to support BAPM disabled. + GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader); + if (D0F0xBC_xE0104188.Field.BapmDisable == 0) { + Property |= GnbBuildOptions.CfgBapmSupport ? TABLE_PROPERTY_BAPM : 0; + } + + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + + // SMU LHTC support init + GnbBapmLhtcInitTN (StdHeader); + + if ((Property & TABLE_PROPERTY_BAPM) == TABLE_PROPERTY_BAPM) { + GnbTjOffsetUpdateTN (StdHeader); + GnbSoftwareTjOffsetTN (StdHeader); + GnbBapmCalculateCoeffsTN (StdHeader); + GnbCacEnablement (StdHeader); + GnbBapmMeasuredTempTN (StdHeader); + } else { + // If BAPM is disabled (either through fusing or CBS option), AGESA should enable LHTC algorithm. + // Right now, LHTC is only enabled in the "DisableBAPM()" firmware routine, so unless Driver specifically calls this message, + // LHTC will never be enabled if BAPM is disabled from the start. + GnbLhtcEnableTN (StdHeader); + } + + GnbInitTdc (StdHeader); + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + Status = GnbProcessTable ( + GnbHandle, + GnbEarlyInitTableTN, + Property, + 0, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceTN Exit [0x%x]\n", Status); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEarlierInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GNB_HANDLE *GnbHandle; + D0F0xBC_xE0107060_STRUCT D0F0xBC_xE0107060; + D0F0xBC_xE0001008_STRUCT D0F0xBC_xE0001008; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceTN Enter\n"); + + GnbAdjustSmuVidBeforeSmuTN (StdHeader); + + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + GnbRegisterReadTN (D0F0xBC_xE0107060_TYPE, D0F0xBC_xE0107060_ADDRESS, &D0F0xBC_xE0107060, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader); + GfxRequestVoltageTN ((UINT8) D0F0xBC_xE0001008.Field.SClkVid1, StdHeader); + GfxRequestSclkTN ((UINT8) D0F0xBC_xE0107060.Field.SClkDpmDid1, StdHeader); + Status = GnbProcessTable ( + GnbHandle, + GnbEarlierInitTableBeforeSmuTN, + 0, + 0, + StdHeader + ); + GnbSmuFirmwareLoadV4 (GnbHandle->Address, (FIRMWARE_HEADER_V4*) &FirmwareTN[0], StdHeader); + Status = GnbProcessTable ( + GnbHandle, + GnbEarlierInitTableAfterSmuTN, + 0, + 0, + StdHeader + ); + + GnbAdjustSmuVidAfterSmuTN (StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceTN Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c new file mode 100644 index 0000000000..f98884dcf9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c @@ -0,0 +1,197 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbFuseTableTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "heapManager.h" +#include "GnbFuseTable.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern GNB_TABLE ROMDATA GnbEnvInitTableTN []; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AMD_ENV_PARAMS *EnvParamsPtr; + UINT32 Property; + GNB_HANDLE *GnbHandle; + D18F5x170_STRUCT D18F5x170; + D0F0xBC_x1F8DC_STRUCT D0F0xBC_x1F8DC; + PP_FUSE_ARRAY *PpFuseArray; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Enter\n"); + Property = TABLE_PROPERTY_DEAFULT; + EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader; + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + GnbLoadFuseTableTN (StdHeader); + Status = GnbSetTom (GnbGetHostPciAddress (GnbHandle), StdHeader); + GnbOrbDynamicWake (GnbGetHostPciAddress (GnbHandle), StdHeader); + GnbClumpUnitIdV4 (GnbHandle, StdHeader); + GnbLpcDmaDeadlockPreventionV4 (GnbHandle, StdHeader); + Property |= GnbBuildOptions.CfgLoadlineEnable ? TABLE_PROPERTY_LOADLINE_ENABLE : 0; + Property |= GnbBuildOptions.CfgIommuL1ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING : 0; + Property |= GnbBuildOptions.CfgIommuL2ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING : 0; + if (!EnvParamsPtr->GnbEnvConfiguration.IommuSupport) { + Property |= TABLE_PROPERTY_IOMMU_DISABLED; + } + + if (GnbBuildOptions.CfgNbdpmEnable) { + GnbRegisterReadTN ( + TYPE_D18F5, + D18F5x170_ADDRESS, + &D18F5x170.Value, + 0, + StdHeader + ); + // Check if NbPstate enbale + if ((D18F5x170.Field.SwNbPstateLoDis != 1) && (D18F5x170.Field.NbPstateMaxVal != 0)) { + Property |= TABLE_PROPERTY_NBDPM; + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + if (PpFuseArray != NULL) { + // NBDPM is requesting SclkVid0 from the register. + // Write them back if SclkVid has been changed in PpFuseArray. + GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, 0, StdHeader); + if ((D0F0xBC_x1F8DC.Field.SClkVid0 != PpFuseArray->SclkVid[0]) || + (D0F0xBC_x1F8DC.Field.SClkVid1 != PpFuseArray->SclkVid[1]) || + (D0F0xBC_x1F8DC.Field.SClkVid2 != PpFuseArray->SclkVid[2]) || + (D0F0xBC_x1F8DC.Field.SClkVid3 != PpFuseArray->SclkVid[3])) { + D0F0xBC_x1F8DC.Field.SClkVid0 = PpFuseArray->SclkVid[0]; + D0F0xBC_x1F8DC.Field.SClkVid1 = PpFuseArray->SclkVid[1]; + D0F0xBC_x1F8DC.Field.SClkVid2 = PpFuseArray->SclkVid[2]; + D0F0xBC_x1F8DC.Field.SClkVid3 = PpFuseArray->SclkVid[3]; + GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + } + } + } + } + + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + + Status = GnbProcessTable ( + GnbHandle, + GnbEnvInitTableTN, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c new file mode 100644 index 0000000000..c2bb8823ff --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c @@ -0,0 +1,1000 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Gnb fuse table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfxFamServices.h" +#include "GnbCommonLib.h" +#include "GnbFuseTable.h" +#include "GnbFuseTableTN.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbFuseTableDebugDumpTN ( + IN PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + + +PP_FUSE_ARRAY ex907 = { + 0, // PP table revision + {1, 0, 0, 0, 0, 0}, // Valid DPM states + {0x40, 0, 0, 0, 0, 0}, // Sclk DPM DID + {0, 0, 0, 0, 0, 0}, // Sclk DPM VID + {0, 0, 0, 0, 0}, // Sclk DPM Cac + {1, 0, 0, 0, 0, 0}, // State policy flags + {2, 0, 0, 0, 0, 0}, // State policy label + {0x40, 0, 0, 0}, // VCLK DID + {0x40, 0, 0, 0}, // DCLK DID + 8, // Thermal SCLK + {0, 0, 0, 0, 0, 0}, // Vclk/Dclk selector + {0, 0, 0, 0}, // Valid Lclk DPM states + {0x40, 0x40, 0x40, 0}, // Lclk DPM DID + {0x40, 0x40, 0x40, 0}, // Lclk DPM VID + {0, 0, 0, 0}, // Displclk DID + 3, // Pcie Gen 2 VID + 0x10, // Main PLL id for 3200 VCO + 0, // WRCK SMU clock Divisor + {0x24, 0x24, 0x24, 0x24}, // SCLK VID + 0, // GPU boost cap + {0, 0, 0, 0, 0, 0}, // Sclk DPM TDP limit + 0, // TDP limit PG + 0, // Boost margin + 0, // Throttle margin + TRUE, // Support VCE in PP table + {0x3, 0xC, 0x30, 0xC0}, // VCE Flags + {0, 1, 0, 1}, // MCLK for VCE + {0, 0, 0, 0}, // SCLK selector for VCE + {0x40, 0x40, 0x40, 0x40} // Eclk DID +}; + + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104158_TABLE [] = { + { + D0F0xBC_xE0104158_EClkDid0_OFFSET, + D0F0xBC_xE0104158_EClkDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[0]) + }, + { + D0F0xBC_xE0104158_EClkDid1_OFFSET, + D0F0xBC_xE0104158_EClkDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[1]) + }, + { + D0F0xBC_xE0104158_EClkDid2_OFFSET, + D0F0xBC_xE0104158_EClkDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[2]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010415B_TABLE [] = { + { + D0F0xBC_xE010415B_EClkDid3_OFFSET, + D0F0xBC_xE010415B_EClkDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[3]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104184_TABLE [] = { + { + D0F0xBC_xE0104184_VCEFlag0_OFFSET, + D0F0xBC_xE0104184_VCEFlag0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[0]) + }, + { + D0F0xBC_xE0104184_VCEFlag1_OFFSET, + D0F0xBC_xE0104184_VCEFlag1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[1]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104187_TABLE [] = { + { + D0F0xBC_xE0104187_VCEFlag2_OFFSET, + D0F0xBC_xE0104187_VCEFlag2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[2]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104188_TABLE [] = { + { + D0F0xBC_xE0104188_VCEFlag3_OFFSET, + D0F0xBC_xE0104188_VCEFlag3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[3]) + }, + { + D0F0xBC_xE0104188_ReqSclkSel0_OFFSET, + D0F0xBC_xE0104188_ReqSclkSel0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[0]) + }, + { + D0F0xBC_xE0104188_ReqSclkSel1_OFFSET, + D0F0xBC_xE0104188_ReqSclkSel1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[1]) + }, + { + D0F0xBC_xE0104188_ReqSclkSel2_OFFSET, + D0F0xBC_xE0104188_ReqSclkSel2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[2]) + }, + { + D0F0xBC_xE0104188_ReqSclkSel3_OFFSET, + D0F0xBC_xE0104188_ReqSclkSel3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[3]) + }, + { + D0F0xBC_xE0104188_VCEMclk_OFFSET + 0, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[0]) + }, + { + D0F0xBC_xE0104188_VCEMclk_OFFSET + 1, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[1]) + }, + { + D0F0xBC_xE0104188_VCEMclk_OFFSET + 2, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[2]) + }, + { + D0F0xBC_xE0104188_VCEMclk_OFFSET + 3, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[3]) + }, +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106020_TABLE [] = { + { + D0F0xBC_xE0106020_PowerplayDClkVClkSel0_OFFSET, + D0F0xBC_xE0106020_PowerplayDClkVClkSel0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0]) + }, + { + D0F0xBC_xE0106020_PowerplayDClkVClkSel1_OFFSET, + D0F0xBC_xE0106020_PowerplayDClkVClkSel1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1]) + }, + { + D0F0xBC_xE0106020_PowerplayDClkVClkSel2_OFFSET, + D0F0xBC_xE0106020_PowerplayDClkVClkSel2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106023_TABLE [] = { + { + D0F0xBC_xE0106023_PowerplayDClkVClkSel3_OFFSET, + D0F0xBC_xE0106023_PowerplayDClkVClkSel3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106024_TABLE [] = { + { + D0F0xBC_xE0106024_PowerplayDClkVClkSel4_OFFSET, + D0F0xBC_xE0106024_PowerplayDClkVClkSel4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4]) + }, + { + D0F0xBC_xE0106024_PowerplayDClkVClkSel5_OFFSET, + D0F0xBC_xE0106024_PowerplayDClkVClkSel5_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705C_TABLE [] = { + { + D0F0xBC_xE010705C_PowerplayTableRev_OFFSET, + D0F0xBC_xE010705C_PowerplayTableRev_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PPlayTableRev) + }, + { + D0F0xBC_xE010705C_SClkThermDid_OFFSET, + D0F0xBC_xE010705C_SClkThermDid_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkThermDid) + }, + { + D0F0xBC_xE010705C_PcieGen2Vid_OFFSET, + D0F0xBC_xE010705C_PcieGen2Vid_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PcieGen2Vid) + } +}; +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705F_TABLE [] = { + { + D0F0xBC_xE010705F_SClkDpmVid0_OFFSET, + D0F0xBC_xE010705F_SClkDpmVid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0]) + }, + { + D0F0xBC_xE010705F_SClkDpmVid0_OFFSET, + D0F0xBC_xE010705F_SClkDpmVid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107060_TABLE [] = { + { + D0F0xBC_xE0107060_SClkDpmVid1_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1]) + }, + { + D0F0xBC_xE0107060_SClkDpmVid1_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[1]) + }, + { + D0F0xBC_xE0107060_SClkDpmVid2_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2]) + }, + { + D0F0xBC_xE0107060_SClkDpmVid2_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[2]) + }, + { + D0F0xBC_xE0107060_SClkDpmVid3_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3]) + }, + { + D0F0xBC_xE0107060_SClkDpmVid4_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4]) + }, + { + D0F0xBC_xE0107060_SClkDpmDid0_OFFSET, + D0F0xBC_xE0107060_SClkDpmDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0]) + }, + { + D0F0xBC_xE0107060_SClkDpmDid1_OFFSET, + D0F0xBC_xE0107060_SClkDpmDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1]) + }, + { + D0F0xBC_xE0107060_SClkDpmDid2_OFFSET, + D0F0xBC_xE0107060_SClkDpmDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107063_TABLE [] = { + { + D0F0xBC_xE0107063_SClkDpmDid3_OFFSET, + D0F0xBC_xE0107063_SClkDpmDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107064_TABLE [] = { + { + D0F0xBC_xE0107064_SClkDpmDid4_OFFSET, + D0F0xBC_xE0107064_SClkDpmDid4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107067_TABLE [] = { + { + D0F0xBC_xE0107067_DispClkDid0_OFFSET, + D0F0xBC_xE0107067_DispClkDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107068_TABLE [] = { + { + D0F0xBC_xE0107068_DispClkDid1_OFFSET, + D0F0xBC_xE0107068_DispClkDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[1]) + }, + { + D0F0xBC_xE0107068_DispClkDid2_OFFSET, + D0F0xBC_xE0107068_DispClkDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[2]) + }, + { + D0F0xBC_xE0107068_DispClkDid3_OFFSET, + D0F0xBC_xE0107068_DispClkDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[3]) + }, + { + D0F0xBC_xE0107068_LClkDpmDid0_OFFSET, + D0F0xBC_xE0107068_LClkDpmDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706B_TABLE [] = { + { + D0F0xBC_xE010706B_LClkDpmDid1_OFFSET, + D0F0xBC_xE010706B_LClkDpmDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706C_TABLE [] = { + { + D0F0xBC_xE010706C_LClkDpmDid2_OFFSET, + D0F0xBC_xE010706C_LClkDpmDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2]) + }, + { + D0F0xBC_xE010706C_LClkDpmDid3_OFFSET, + D0F0xBC_xE010706C_LClkDpmDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3]) + }, + { + D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 0, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0]) + }, + { + D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 1, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1]) + }, + { + D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 2, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2]) + }, + { + D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 3, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3]) + }, + { + D0F0xBC_xE010706C_DClkDid0_OFFSET, + D0F0xBC_xE010706C_DClkDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706F_TABLE [] = { + { + D0F0xBC_xE010706F_DClkDid1_OFFSET, + D0F0xBC_xE010706F_DClkDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[1]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107070_TABLE [] = { + { + D0F0xBC_xE0107070_DClkDid2_OFFSET, + D0F0xBC_xE0107070_DClkDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[2]) + }, + { + D0F0xBC_xE0107070_DClkDid3_OFFSET, + D0F0xBC_xE0107070_DClkDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[3]) + }, + { + D0F0xBC_xE0107070_VClkDid0_OFFSET, + D0F0xBC_xE0107070_VClkDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107073_TABLE [] = { + { + D0F0xBC_xE0107073_VClkDid1_OFFSET, + D0F0xBC_xE0107073_VClkDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[1]) + }, +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107074_TABLE [] = { + { + D0F0xBC_xE0107074_VClkDid2_OFFSET, + D0F0xBC_xE0107074_VClkDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[2]) + }, + { + D0F0xBC_xE0107074_VClkDid3_OFFSET, + D0F0xBC_xE0107074_VClkDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[3]) + }, + { + D0F0xBC_xE0107074_PowerplaySclkDpmValid0_OFFSET, + D0F0xBC_xE0107074_PowerplaySclkDpmValid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0]) + }, + { + D0F0xBC_xE0107074_PowerplaySclkDpmValid1_OFFSET, + D0F0xBC_xE0107074_PowerplaySclkDpmValid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1]) + }, + { + D0F0xBC_xE0107074_PowerplaySclkDpmValid2_OFFSET, + D0F0xBC_xE0107074_PowerplaySclkDpmValid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107077_TABLE [] = { + { + D0F0xBC_xE0107077_PowerplaySclkDpmValid3_OFFSET, + D0F0xBC_xE0107077_PowerplaySclkDpmValid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107078_TABLE [] = { + { + D0F0xBC_xE0107078_PowerplaySclkDpmValid4_OFFSET, + D0F0xBC_xE0107078_PowerplaySclkDpmValid4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4]) + }, + { + D0F0xBC_xE0107078_PowerplaySclkDpmValid5_OFFSET, + D0F0xBC_xE0107078_PowerplaySclkDpmValid5_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel0_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[0]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel1_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[1]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel2_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[2]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel3_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[3]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel4_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[4]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel5_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel5_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[5]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707B_TABLE [] = { + { + D0F0xBC_xE010707B_PowerplayStateFlag0_OFFSET, + D0F0xBC_xE010707B_PowerplayStateFlag0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707C_TABLE [] = { + { + D0F0xBC_xE010707C_PowerplayStateFlag1_OFFSET, + D0F0xBC_xE010707C_PowerplayStateFlag1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[1]) + }, + { + D0F0xBC_xE010707C_PowerplayStateFlag2_OFFSET, + D0F0xBC_xE010707C_PowerplayStateFlag2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[2]) + }, + { + D0F0xBC_xE010707C_PowerplayStateFlag3_OFFSET, + D0F0xBC_xE010707C_PowerplayStateFlag3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[3]) + }, + { + D0F0xBC_xE010707C_PowerplayStateFlag4_OFFSET, + D0F0xBC_xE010707C_PowerplayStateFlag4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[4]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707F_TABLE [] = { + { + D0F0xBC_xE010707F_PowerplayStateFlag5_OFFSET, + D0F0xBC_xE010707F_PowerplayStateFlag5_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[5]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xFF000000_TABLE [] = { + { + D0F0xBC_xFF000000_MainPllOpFreqIdStartup_OFFSET, + D0F0xBC_xFF000000_MainPllOpFreqIdStartup_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, MainPllId) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0001008_TABLE [] = { + { + D0F0xBC_xE0001008_SClkVid0_OFFSET, + D0F0xBC_xE0001008_SClkVid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[0]) + }, + { + D0F0xBC_xE0001008_SClkVid1_OFFSET, + D0F0xBC_xE0001008_SClkVid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[1]) + }, + { + D0F0xBC_xE0001008_SClkVid2_OFFSET, + D0F0xBC_xE0001008_SClkVid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[2]) + }, + { + D0F0xBC_xE0001008_SClkVid3_OFFSET, + D0F0xBC_xE0001008_SClkVid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[3]) + } +}; + + +FUSE_TABLE_ENTRY_TN FuseRegisterTableTN [] = { + { + D0F0xBC_xE0104158_TYPE, + D0F0xBC_xE0104158_ADDRESS, + sizeof (D0F0xBC_xE0104158_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0104158_TABLE + }, + { + D0F0xBC_xE010415B_TYPE, + D0F0xBC_xE010415B_ADDRESS, + sizeof (D0F0xBC_xE010415B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010415B_TABLE + }, + { + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + sizeof (D0F0xBC_xE0104184_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0104184_TABLE + }, + { + D0F0xBC_xE0104187_TYPE, + D0F0xBC_xE0104187_ADDRESS, + sizeof (D0F0xBC_xE0104187_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0104187_TABLE + }, + { + D0F0xBC_xE0104188_TYPE, + D0F0xBC_xE0104188_ADDRESS, + sizeof (D0F0xBC_xE0104188_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0104188_TABLE + }, + { + D0F0xBC_xE0106020_TYPE, + D0F0xBC_xE0106020_ADDRESS, + sizeof (D0F0xBC_xE0106020_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0106020_TABLE + }, + { + D0F0xBC_xE0106023_TYPE, + D0F0xBC_xE0106023_ADDRESS, + sizeof (D0F0xBC_xE0106023_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0106023_TABLE + }, + { + D0F0xBC_xE0106024_TYPE, + D0F0xBC_xE0106024_ADDRESS, + sizeof (D0F0xBC_xE0106024_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0106024_TABLE + }, + { + D0F0xBC_xE010705C_TYPE, + D0F0xBC_xE010705C_ADDRESS, + sizeof (D0F0xBC_xE010705C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010705C_TABLE + }, + { + D0F0xBC_xE010705F_TYPE, + D0F0xBC_xE010705F_ADDRESS, + sizeof (D0F0xBC_xE010705F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010705F_TABLE + }, + { + D0F0xBC_xE0107060_TYPE, + D0F0xBC_xE0107060_ADDRESS, + sizeof (D0F0xBC_xE0107060_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107060_TABLE + }, + { + D0F0xBC_xE0107063_TYPE, + D0F0xBC_xE0107063_ADDRESS, + sizeof (D0F0xBC_xE0107063_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107063_TABLE + }, + { + D0F0xBC_xE0107064_TYPE, + D0F0xBC_xE0107064_ADDRESS, + sizeof (D0F0xBC_xE0107064_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107064_TABLE + }, + { + D0F0xBC_xE0107067_TYPE, + D0F0xBC_xE0107067_ADDRESS, + sizeof (D0F0xBC_xE0107067_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107067_TABLE + }, + { + D0F0xBC_xE0107068_TYPE, + D0F0xBC_xE0107068_ADDRESS, + sizeof (D0F0xBC_xE0107068_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107068_TABLE + }, + { + D0F0xBC_xE010706B_TYPE, + D0F0xBC_xE010706B_ADDRESS, + sizeof (D0F0xBC_xE010706B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010706B_TABLE + }, + { + D0F0xBC_xE010706C_TYPE, + D0F0xBC_xE010706C_ADDRESS, + sizeof (D0F0xBC_xE010706C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010706C_TABLE + }, + { + D0F0xBC_xE010706F_TYPE, + D0F0xBC_xE010706F_ADDRESS, + sizeof (D0F0xBC_xE010706F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010706F_TABLE + }, + { + D0F0xBC_xE0107070_TYPE, + D0F0xBC_xE0107070_ADDRESS, + sizeof (D0F0xBC_xE0107070_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107070_TABLE + }, + { + D0F0xBC_xE0107073_TYPE, + D0F0xBC_xE0107073_ADDRESS, + sizeof (D0F0xBC_xE0107073_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107073_TABLE + }, + { + D0F0xBC_xE0107074_TYPE, + D0F0xBC_xE0107074_ADDRESS, + sizeof (D0F0xBC_xE0107074_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107074_TABLE + }, + { + D0F0xBC_xE0107077_TYPE, + D0F0xBC_xE0107077_ADDRESS, + sizeof (D0F0xBC_xE0107077_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107077_TABLE + }, + { + D0F0xBC_xE0107078_TYPE, + D0F0xBC_xE0107078_ADDRESS, + sizeof (D0F0xBC_xE0107078_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107078_TABLE + }, + { + D0F0xBC_xE010707B_TYPE, + D0F0xBC_xE010707B_ADDRESS, + sizeof (D0F0xBC_xE010707B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010707B_TABLE + }, + { + D0F0xBC_xE010707C_TYPE, + D0F0xBC_xE010707C_ADDRESS, + sizeof (D0F0xBC_xE010707C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010707C_TABLE + }, + { + D0F0xBC_xE010707F_TYPE, + D0F0xBC_xE010707F_ADDRESS, + sizeof (D0F0xBC_xE010707F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010707F_TABLE + }, + { + D0F0xBC_xFF000000_TYPE, + D0F0xBC_xFF000000_ADDRESS, + sizeof (D0F0xBC_xFF000000_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xFF000000_TABLE + }, + { + D0F0xBC_xE0001008_TYPE, + D0F0xBC_xE0001008_ADDRESS, + sizeof (D0F0xBC_xE0001008_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0001008_TABLE + } +}; + +FUSE_TABLE_TN FuseTableTN = { + sizeof (FuseRegisterTableTN) / sizeof (FUSE_TABLE_ENTRY_TN), + FuseRegisterTableTN +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Load Fuse Table TN + * + * + * @param[out] PpFuseArray Pointer to save fuse table + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +STATIC VOID +NbFuseLoadFuseTableTN ( + OUT PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + FUSE_TABLE_TN *FuseTable; + UINTN RegisterIndex; + FuseTable = &FuseTableTN; + for (RegisterIndex = 0; RegisterIndex < FuseTable->FuseTableLength; RegisterIndex++ ) { + UINTN FieldIndex; + UINTN FuseRegisterTableLength; + UINT32 FuseValue; + FuseRegisterTableLength = FuseTable->FuseTable[RegisterIndex].FuseRegisterTableLength; + + GnbRegisterReadTN ( + FuseTable->FuseTable[RegisterIndex].RegisterSpaceType, + FuseTable->FuseTable[RegisterIndex].Register, + &FuseValue, + 0, + StdHeader + ); + for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength; FieldIndex++) { + FUSE_REGISTER_ENTRY_TN RegisterEntry; + RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex]; + *((UINT8 *) PpFuseArray + RegisterEntry.FuseOffset) = (UINT8) ((FuseValue >> RegisterEntry.FieldOffset) & + ((1 << RegisterEntry.FieldWidth) - 1)); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb load fuse table + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbLoadFuseTableTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PP_FUSE_ARRAY *PpFuseArray; + AGESA_STATUS Status; + D18F3xA0_STRUCT D18F3xA0; + + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Enter\n"); + + PpFuseArray = (PP_FUSE_ARRAY *) GnbAllocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, sizeof (PP_FUSE_ARRAY), StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray != NULL) { + //Support for real fuste table + GnbRegisterReadTN (D18F3xA0_TYPE, D18F3xA0_ADDRESS, &D18F3xA0.Value, 0, StdHeader); + if ((D18F3xA0.Field.CofVidProg) && (GnbBuildOptions.GnbLoadRealFuseTable)) { + NbFuseLoadFuseTableTN (PpFuseArray, StdHeader); + PpFuseArray->VceSateTableSupport = TRUE; + IDS_HDT_CONSOLE (NB_MISC, " Processor Fused\n"); + } else { + LibAmdMemCopy (PpFuseArray, &ex907 , sizeof (PP_FUSE_ARRAY), StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Processor Unfuse\n"); + } + } else { + Status = AGESA_ERROR; + } + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPFUSE_OVERRIDE, PpFuseArray, StdHeader); + GnbFuseTableDebugDumpTN (PpFuseArray, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Exit [0x%x]\n", Status); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Debug dump fuse table + * + * + * @param[out] PpFuseArray Pointer to save fuse table + * @param[in] StdHeader Pointer to Standard configuration + */ + +VOID +GnbFuseTableDebugDumpTN ( + IN PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Index; + + IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n"); + for (Index = 0; Index < 4; Index++) { + if (PpFuseArray->LclkDpmValid[Index] != 0) { + IDS_HDT_CONSOLE ( + NB_MISC, + " LCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->LclkDpmDid[Index], + (PpFuseArray->LclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->LclkDpmDid[Index], StdHeader) / 100) : 0 + ); + IDS_HDT_CONSOLE (NB_MISC, " LCLK VID[%d] - 0x02%x\n", Index, PpFuseArray->LclkDpmVid[Index]); + } + } + for (Index = 0; Index < 4; Index++) { + IDS_HDT_CONSOLE ( + NB_MISC, + " VCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->VclkDid[Index], + (PpFuseArray->VclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->VclkDid[Index], StdHeader) / 100) : 0 + ); + IDS_HDT_CONSOLE ( + NB_MISC, + " DCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->DclkDid[Index], + (PpFuseArray->DclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DclkDid[Index], StdHeader) / 100) : 0 + ); + } + for (Index = 0; Index < 4; Index++) { + IDS_HDT_CONSOLE ( + NB_MISC, + " DISPCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->DisplclkDid[Index], + (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DisplclkDid[Index], StdHeader) / 100) : 0 + ); + } + for (Index = 0; Index < 4; Index++) { + IDS_HDT_CONSOLE ( + NB_MISC, + " ECLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->EclkDid[Index], + (PpFuseArray->EclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->EclkDid[Index], StdHeader) / 100) : 0 + ); + IDS_HDT_CONSOLE ( + NB_MISC, + " VCE SCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]], + (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]], StdHeader) / 100) : 0 + ); + IDS_HDT_CONSOLE ( + NB_MISC, + " VCE Flags[ % d] - 0x % 02x\n", + Index, + PpFuseArray->VceFlags[Index] + ); + } + for (Index = 0; Index < 6; Index++) { + IDS_HDT_CONSOLE ( + NB_MISC, + " SCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->SclkDpmDid[Index], + (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[Index], StdHeader) / 100) : 0 + ); + IDS_HDT_CONSOLE ( + NB_MISC, + " SCLK TDP[%d] - 0x%x \n", + Index, + PpFuseArray->SclkDpmTdpLimit[Index] + ); + IDS_HDT_CONSOLE (NB_MISC, " SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]); + } + for (Index = 0; Index < 6; Index++) { + IDS_HDT_CONSOLE (NB_MISC, " State #%d\n", Index); + } + IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n"); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h new file mode 100644 index 0000000000..5d6177f1e0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h @@ -0,0 +1,105 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fuse table initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBFUSETABLETN_H_ +#define _GNBFUSETABLETN_H_ + +#pragma pack (push, 1) + +/// Fuse field entry +typedef struct { + UINT8 FieldOffset; ///< Field offset in fuse register + UINT8 FieldWidth; ///< Width of field + UINT16 FuseOffset; ///< destination offset in translation table +} FUSE_REGISTER_ENTRY_TN; + +/// Fuse register entry +typedef struct { + UINT8 RegisterSpaceType; ///< Register type + UINT32 Register; ///< FCR register address + UINT8 FuseRegisterTableLength; ///< Length of field table for this register + FUSE_REGISTER_ENTRY_TN *FuseRegisterTable; ///< Pointer to field table +} FUSE_TABLE_ENTRY_TN; + +/// Fuse translation table +typedef struct { + UINT8 FuseTableLength; ///< Length of translation table + FUSE_TABLE_ENTRY_TN *FuseTable; ///< Pointer to register table +} FUSE_TABLE_TN; + +#pragma pack (pop) + +AGESA_STATUS +GnbLoadFuseTableTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h new file mode 100644 index 0000000000..76196f1c08 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h @@ -0,0 +1,78 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various TN definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBINITTN_H_ +#define _GNBINITTN_H_ + +#define D0F0xBC_x1F468_TimerPeriod_Value 100000 +#define D0F0xBC_x1F46C_BapmPeriod_Value 1 + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h new file mode 100644 index 0000000000..e6ac431378 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h @@ -0,0 +1,200 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Tn service installation file + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNB_INIT_TN_INSTALL_H_ +#define _GNB_INIT_TN_INSTALL_H_ + +//----------------------------------------------------------------------- +// Specify definition used by module services +//----------------------------------------------------------------------- + +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbFamServices.h" + +//----------------------------------------------------------------------- +// Export services +//----------------------------------------------------------------------- + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) + extern F_PCIEFMGETCOMPLEXDATALENGTH PcieGetComplexDataLengthTN; + extern F_PCIEFMBUILDCOMPLEXCONFIGURATION PcieBuildComplexConfigurationTN; + extern F_PCIEFMCONFIGUREENGINESLANEALLOCATION PcieConfigureEnginesLaneAllocationTN; + extern F_PCIEFMCHECKPORTPCIDEVICEMAPPING PcieCheckPortPciDeviceMappingTN; + extern F_PCIEFMMAPPORTPCIADDRESS PcieMapPortPciAddressTN; + extern F_PCIEFMCHECKPORTPCIELANECANBEMUXED PcieCheckPortPcieLaneCanBeMuxedTN; + extern F_PCIEFMGETSBCONFIGINFO PcieGetSbConfigInfoTN; + PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolTN = { + PcieGetComplexDataLengthTN, + PcieBuildComplexConfigurationTN, + PcieConfigureEnginesLaneAllocationTN, + PcieCheckPortPciDeviceMappingTN, + PcieMapPortPciAddressTN, + PcieCheckPortPcieLaneCanBeMuxedTN, + PcieGetSbConfigInfoTN + }; + + GNB_SERVICE GnbPcieCongigServicesTN = { + GnbPcieFamConfigService, + AMD_FAMILY_TN, + &GnbPcieConfigProtocolTN, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieCongigServicesTN +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) + extern F_PCIEFMGETCORECONFIGURATIONVALUE PcieGetCoreConfigurationValueTN; + extern F_PCIEFMGETLINKSPEEDCAP PcieGetLinkSpeedCapTN; + extern F_PCIEFMGETNATIVEPHYLANEBITMAP PcieGetNativePhyLaneBitmapTN; + extern F_PCIEFMSETLINKSPEEDCAP PcieSetLinkSpeedCapV4; + + PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolTN = { + PcieGetCoreConfigurationValueTN, + PcieGetLinkSpeedCapTN, + PcieGetNativePhyLaneBitmapTN, + PcieSetLinkSpeedCapV4 + }; + + GNB_SERVICE GnbPcieInitServicesTN = { + GnbPcieFamInitService, + AMD_FAMILY_TN, + &GnbPcieInitProtocolTN, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieInitServicesTN +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) + #if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_TRACING_ENABLED == TRUE + extern F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING PcieDebugGetHostRegAddressSpaceStringTN; + extern F_PCIEFMDEBUGGETWRAPPERNAMESTRING PcieDebugGetWrapperNameStringTN; + extern F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING PcieDebugGetCoreConfigurationStringTN; + + PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolTN = { + PcieDebugGetHostRegAddressSpaceStringTN, + PcieDebugGetWrapperNameStringTN, + PcieDebugGetCoreConfigurationStringTN + }; + + GNB_SERVICE GnbPcieDebugServicesTN = { + GnbPcieFamDebugService, + AMD_FAMILY_TN, + &GnbPcieDebugProtocolTN, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieDebugServicesTN + #endif + #endif +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + extern F_GNB_REGISTER_ACCESS GnbRegisterReadServiceTN; + extern F_GNB_REGISTER_ACCESS GnbRegisterWriteServiceTN; + + GNB_REGISTER_SERVICE GnbRegiterAccessProtocol = { + GnbRegisterReadServiceTN, + GnbRegisterWriteServiceTN + }; + + GNB_SERVICE GnbRegisterAccessServicesTN = { + GnbRegisterAccessService, + AMD_FAMILY_TN, + &GnbRegiterAccessProtocol, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbRegisterAccessServicesTN + + extern F_GNBFMCREATEIVRSENTRY GnbCreateIvrsEntryTN; + extern F_GNBFMCHECKIOMMUPRESENT GnbCheckIommuPresentTN; + + GNB_FAM_IOMMU_SERVICES GnbIommuConfigProtocolTN = { + GnbCheckIommuPresentTN, + GnbCreateIvrsEntryTN + }; + + GNB_SERVICE GnbIommuConfigServicesTN = { + GnbIommuService, + AMD_FAMILY_TN, + &GnbIommuConfigProtocolTN, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbIommuConfigServicesTN + +#endif +#endif // _GNB_INIT_TN_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c new file mode 100644 index 0000000000..8f176d77b0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c @@ -0,0 +1,289 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 64352 $ @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuLateInit.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbIommu.h" +#include "GnbIvrsLib.h" +#include "GnbSbIommuLib.h" +#include "GnbCommonLib.h" +#include "GnbNbInitLibV4.h" +#include "GnbIommuIvrs.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbCreateIvhdHeaderTN ( + IN IVRS_BLOCK_TYPE Type, + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbCreateIvhdTN ( + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbCreateIvhdrTN ( + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbCreateIvrsEntryTN ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbCheckIommuPresentTN ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if IOMMU unit present and enabled + * + * + * + * + * @param[in] GnbHandle Gnb handle + * @param[in] StdHeader Standard configuration header + * + */ +BOOLEAN +GnbCheckIommuPresentTN ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 0, 2, 0), StdHeader)) { + return TRUE; + } + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVRS entry + * + * + * @param[in] GnbHandle Gnb handle + * @param[in] Type Entry type + * @param[in] Ivrs IVRS table pointer + * @param[in] StdHeader Standard configuration header + * + */ + +AGESA_STATUS +GnbCreateIvrsEntryTN ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IVRS_IVHD_ENTRY *Ivhd; + UINT8 IommuCapabilityOffset; + UINT32 Value; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Entry\n"); + if (Type == IvrsIvhdBlock || Type == IvrsIvhdrBlock) { + // Update IVINFO + IommuCapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader); + GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, IommuCapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader); + ((IOMMU_IVRS_HEADER *) Ivrs)->IvInfo = Value & (IVINFO_HTATSRESV_MASK | IVINFO_VASIZE_MASK | IVINFO_GASIZE_MASK | IVINFO_PASIZE_MASK); + + // Address of IVHD entry + Ivhd = (IVRS_IVHD_ENTRY*) ((UINT8 *)Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength); + GnbCreateIvhdHeaderTN (Type, Ivhd, StdHeader); + if (Type == IvrsIvhdBlock) { + GnbCreateIvhdTN (Ivhd, StdHeader); + } else { + GnbCreateIvhdrTN (Ivhd, StdHeader); + } + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength = ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength + Ivhd->Length; + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVRS entry + * + * + * @param[in] Type Block type + * @param[in] Ivhd IVHD header pointer + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbCreateIvhdHeaderTN ( + IN IVRS_BLOCK_TYPE Type, + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + Ivhd->Type = (UINT8) Type; + Ivhd->Flags = IVHD_FLAG_COHERENT | IVHD_FLAG_IOTLBSUP | IVHD_FLAG_ISOC | IVHD_FLAG_RESPASSPW | IVHD_FLAG_PASSPW | IVHD_FLAG_PPRSUB | IVHD_FLAG_PREFSUP; + Ivhd->Length = sizeof (IVRS_IVHD_ENTRY); + Ivhd->DeviceId = 0x2; + Ivhd->CapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader); + Ivhd->PciSegment = 0; + GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x4), AccessWidth32, &Ivhd->BaseAddress, StdHeader); + GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x8), AccessWidth32, (UINT8 *) &Ivhd->BaseAddress + 4, StdHeader); + Ivhd->BaseAddress = Ivhd->BaseAddress & 0xfffffffffffffffe; + ASSERT (Ivhd->BaseAddress != 0x0); + GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader); + Ivhd->IommuInfo = (UINT16) (Value & 0x1f) | (0x13 << IVHD_INFO_UNITID_OFFSET); + Ivhd->IommuEfr = (0 << IVHD_EFR_XTSUP_OFFSET) | (0 << IVHD_EFR_NXSUP_OFFSET) | (1 << IVHD_EFR_GTSUP_OFFSET) | + (0 << IVHD_EFR_GLXSUP_OFFSET) | (1 << IVHD_EFR_IASUP_OFFSET) | (0 << IVHD_EFR_GASUP_OFFSET) | + (0 << IVHD_EFR_HESUP_OFFSET) | (0x8 << IVHD_EFR_PASMAX_OFFSET) | (0 << IVHD_EFR_MSINUMPPR_OFFSET) | + (4 << IVHD_EFR_PNCOUNTERS_OFFSET) | (2 << IVHD_EFR_PNBANKS_OFFSET); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVHD entry + * + * + * @param[in] Ivhd IVHD header pointer + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbCreateIvhdTN ( + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR Start; + PCI_ADDR End; + Start.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0); + End.AddressValue = MAKE_SBDFO (0, 0xFF, 0x1F, 6, 0); + GnbIvhdAddDeviceRangeEntry (Start, End, 0, Ivhd, StdHeader); + SbCreateIvhdEntries (Ivhd, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVHDR entry + * + * + * @param[in] Ivhd IVHD header pointer + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbCreateIvhdrTN ( + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c new file mode 100644 index 0000000000..626f33d3aa --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c @@ -0,0 +1,574 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 64352 $ @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbFuseTable.h" +#include "heapManager.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbGfxInitLibV1.h" +#include "GnbGfxConfig.h" +#include "GnbTable.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "OptionGnb.h" +#include "GfxLibTN.h" +#include "GnbFamServices.h" +#include "GnbGfxFamServices.h" +#include "GnbBapmCoeffCalcTN.h" +#include "PcieComplexDataTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern GNB_TABLE ROMDATA GnbMidInitTableTN[]; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +#define NUM_DPM_STATES 8 + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Registers needs to be set if no GFX PCIe ports beeing us + * + * + * + * @param[in] Pcie Pointer to PCIe_PLATFORM_CONFIG + */ + +VOID +STATIC +GnbIommuMidInitCheckGfxPciePorts ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_WRAPPER_CONFIG *WrapperList; + BOOLEAN GfxPciePortUsed; + D0F2xF4_x57_STRUCT D0F2xF4_x57; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Enter\n"); + GfxPciePortUsed = FALSE; + + WrapperList = PcieConfigGetChildWrapper (Pcie); + ASSERT (WrapperList != NULL); + if (WrapperList->WrapId == GFX_WRAP_ID) { + PCIe_ENGINE_CONFIG *EngineList; + EngineList = PcieConfigGetChildEngine (WrapperList); + while (EngineList != NULL) { + if (PcieConfigIsPcieEngine (EngineList)) { + IDS_HDT_CONSOLE (GNB_TRACE, "Checking Gfx ports device number %x\n", EngineList->Type.Port.NativeDevNumber); + if (PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) || + ((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard))) { + // GFX PCIe ports beeing used + GfxPciePortUsed = TRUE; + IDS_HDT_CONSOLE (GNB_TRACE, "GFX PCIe ports beeing used\n"); + break; + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + } + + if (!GfxPciePortUsed) { + //D0F2xF4_x57.Field.L1ImuPcieGfxDis needs to be set + GnbRegisterReadTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, 0, GnbLibGetHeader (Pcie)); + D0F2xF4_x57.Field.L1ImuPcieGfxDis = 1; + GnbRegisterWriteTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to for each PCIe port + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +GnbIommuMidInitOnPortCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + GNB_TOPOLOGY_INFO TopologyInfo; + D0F2xFC_x07_L1_STRUCT D0F2xFC_x07_L1; + D0F2xFC_x0D_L1_STRUCT D0F2xFC_x0D_L1; + UINT8 L1cfgSel; + TopologyInfo.PhantomFunction = FALSE; + TopologyInfo.PcieToPciexBridge = FALSE; + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + TopologyInfo.PhantomFunction = TRUE; + TopologyInfo.PcieToPciexBridge = TRUE; + } else { + if (PcieConfigIsSbPcieEngine (Engine)) { + PCI_ADDR StartSbPcieDev; + PCI_ADDR EndSbPcieDev; + StartSbPcieDev.AddressValue = MAKE_SBDFO (0, 0, 0x15, 0, 0); + EndSbPcieDev.AddressValue = MAKE_SBDFO (0, 0, 0x15, 7, 0); + GnbGetTopologyInfoV4 (StartSbPcieDev, EndSbPcieDev, &TopologyInfo, GnbLibGetHeader (Pcie)); + } else { + GnbGetTopologyInfoV4 (Engine->Type.Port.Address, Engine->Type.Port.Address, &TopologyInfo, GnbLibGetHeader (Pcie)); + } + } + L1cfgSel = (Engine->Type.Port.CoreId == 1) ? 1 : 0; + if (TopologyInfo.PhantomFunction) { + GnbRegisterReadTN ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1cfgSel), + &D0F2xFC_x07_L1.Value, + 0, + GnbLibGetHeader (Pcie) + ); + D0F2xFC_x07_L1.Value |= BIT0; + GnbRegisterWriteTN ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1cfgSel), + &D0F2xFC_x07_L1.Value, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + if (TopologyInfo.PcieToPciexBridge) { + GnbRegisterReadTN ( + D0F2xFC_x0D_L1_TYPE, + D0F2xFC_x0D_L1_ADDRESS (L1cfgSel), + &D0F2xFC_x0D_L1.Value, + 0, + GnbLibGetHeader (Pcie) + ); + D0F2xFC_x0D_L1.Field.VOQPortBits = 0x7; + GnbRegisterWriteTN ( + D0F2xFC_x0D_L1_TYPE, + D0F2xFC_x0D_L1_ADDRESS (L1cfgSel), + &D0F2xFC_x0D_L1.Value, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Orb/Ioc Cgtt Override setting + * + * + * @param[in] Property Property + * @param[in] StdHeader Standard configuration header + */ + +VOID +STATIC +GnbCgttOverrideTN ( + IN UINT32 Property, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CGINDx0_Value; + UINT32 CGINDx1_Value; + GFX_PLATFORM_CONFIG *Gfx; + AGESA_STATUS Status; + D0F0x64_x23_STRUCT D0F0x64_x23; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Enter\n"); + + CGINDx0_Value = 0xFFFFFFFF; + //When orb clock gating is enabled in the BIOS clear CG_ORB_cgtt_lclk_override - bit 13 + CGINDx1_Value = 0xFFFFFFFF; + if ((Property & TABLE_PROPERTY_ORB_CLK_GATING) == TABLE_PROPERTY_ORB_CLK_GATING) { + CGINDx1_Value &= 0xFFFFDFFF; + } + //When ioc clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 15 + if ((Property & TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) == TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) { + CGINDx1_Value &= 0xFFFF7FFF; + if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) != TABLE_PROPERTY_IOMMU_DISABLED) { + //only IOMMU enabled and IOC clock gating enable + GnbRegisterReadTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, 0, StdHeader); + D0F0x64_x23.Field.SoftOverrideClk0 = 1; + D0F0x64_x23.Field.SoftOverrideClk1 = 1; + D0F0x64_x23.Field.SoftOverrideClk3 = 1; + D0F0x64_x23.Field.SoftOverrideClk4 = 1; + GnbRegisterWriteTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + } + } + //When smu sclk clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 18 + if ((Property & TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) == TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) { + CGINDx1_Value &= 0xFFFBFFFF; + } + + Status = GfxLocateConfigData (StdHeader, &Gfx); + if (Status != AGESA_FATAL) { + if (Gfx->GmcClockGating) { + //In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks + // CGINDx0, clear bit 27, bit 28 + CGINDx0_Value &= 0xE7FFFFFF; + GnbRegisterWriteTN (TYPE_CGIND, 0x0, &CGINDx0_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + // CGINDx1, clear bit 11 + CGINDx1_Value &= 0xFFFFF7FF; + } + + } + + if (CGINDx1_Value != 0xFFFFFFFF) { + GnbRegisterWriteTN (TYPE_CGIND, 0x1, &CGINDx1_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Exit\n"); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * IOMMU Mid Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GnbIommuMidInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Enter\n"); + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + if (Status == AGESA_SUCCESS) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + GnbIommuMidInitOnPortCallback, + NULL, + Pcie + ); + } + + GnbIommuMidInitCheckGfxPciePorts (Pcie); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * IOMMU Mid Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GnbLclkDpmInitTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + PP_FUSE_ARRAY *PpFuseArray; + PCI_ADDR GnbPciAddress; + UINT32 Index; + UINT8 LclkDpmMode; + D0F0xBC_x1F200_STRUCT D0F0xBC_x1F200[NUM_DPM_STATES]; + D0F0xBC_x1F208_STRUCT D0F0xBC_x1F208[NUM_DPM_STATES]; + D0F0xBC_x1F210_STRUCT D0F0xBC_x1F210[NUM_DPM_STATES]; + D0F0xBC_x1F300_STRUCT D0F0xBC_x1F300; + ex1003_STRUCT ex1003 [NUM_DPM_STATES]; + DOUBLE PcieCacLut; + ex1072_STRUCT ex1072 ; + D0F0xBC_x1FE00_STRUCT D0F0xBC_x1FE00; + D0F0xBC_x1F30C_STRUCT D0F0xBC_x1F30C; + D18F3x64_STRUCT D18F3x64; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Enter\n"); + Status = AGESA_SUCCESS; + LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled; + IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader); + if (LclkDpmMode == LclkDpmRcActivity) { + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + if (PpFuseArray != NULL) { + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + if (Status == AGESA_SUCCESS) { + GnbPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + //Clear DPM_EN bit in LCLK_DPM_CNTL register + //Call BIOS service SMC_MSG_CONFIG_LCLK_DPM to disable LCLK DPM + GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader); + D0F0xBC_x1F300.Field.LclkDpmEn = 0x0; + GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbSmuServiceRequestV4 ( + GnbPciAddress, + SMC_MSG_CONFIG_LCLK_DPM, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + + //Initialize LCLK states + LibAmdMemFill (D0F0xBC_x1F200, 0x00, sizeof (D0F0xBC_x1F200), StdHeader); + LibAmdMemFill (D0F0xBC_x1F208, 0x00, sizeof (D0F0xBC_x1F208), StdHeader); + LibAmdMemFill (ex1003, 0x00, sizeof (D0F0xBC_x1F208), StdHeader); + + D0F0xBC_x1F200[0].Field.LclkDivider = PpFuseArray->LclkDpmDid[0]; + D0F0xBC_x1F200[0].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[0]]; + D0F0xBC_x1F200[0].Field.LowVoltageReqThreshold = 0xa; + D0F0xBC_x1F210[0].Field.ActivityThreshold = 0xf; + + D0F0xBC_x1F200[5].Field.LclkDivider = PpFuseArray->LclkDpmDid[1]; + D0F0xBC_x1F200[5].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[1]]; + D0F0xBC_x1F200[5].Field.LowVoltageReqThreshold = 0xa; + D0F0xBC_x1F210[5].Field.ActivityThreshold = 0x32; + D0F0xBC_x1F200[5].Field.StateValid = 0x1; + + D0F0xBC_x1F200[6].Field.LclkDivider = PpFuseArray->LclkDpmDid[2]; + D0F0xBC_x1F200[6].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[2]]; + D0F0xBC_x1F200[6].Field.LowVoltageReqThreshold = 0xa; + D0F0xBC_x1F210[6].Field.ActivityThreshold = 0x32; + D0F0xBC_x1F200[6].Field.StateValid = 0x1; + + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072.Value, 0, StdHeader); + PcieCacLut = 0.0000057028 * (1 << ex1072.Field.ex1072_0 ); + IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM1 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader)); + D0F0xBC_x1FE00.Field.Data = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader)); + GnbRegisterWriteTN (D0F0xBC_x1FE00_TYPE, D0F0xBC_x1FE00_ADDRESS, &D0F0xBC_x1FE00.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + PcieCacLut = 0.00000540239329 * (1 << ex1072.Field.ex1072_0 ); + ex1003[6].Field.ex1003_0 = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader)); + IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM2 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader)); + + for (Index = 0; Index < NUM_DPM_STATES; ++Index) { + GnbRegisterWriteTN ( + D0F0xBC_x1F200_TYPE, + D0F0xBC_x1F200_ADDRESS + Index * 0x20, + &D0F0xBC_x1F200[Index].Value, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteTN ( + D0F0xBC_x1F208_TYPE, + D0F0xBC_x1F208_ADDRESS + Index * 0x20, + &D0F0xBC_x1F208[Index].Value, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteTN ( + D0F0xBC_x1F210_TYPE, + D0F0xBC_x1F210_ADDRESS + Index * 0x20, + &D0F0xBC_x1F210[Index].Value, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteTN ( + TYPE_D0F0xBC , + 0x1f940 + Index * 4, + &ex1003[Index].Value, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + } + //Enable LCLK DPM Voltage Scaling + GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader); + D0F0xBC_x1F300.Field.VoltageChgEn = 0x1; + D0F0xBC_x1F300.Field.LclkDpmEn = 0x1; + D0F0xBC_x1F300.Field.LclkDpmBootState = 0x5; + GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + //Programming Lclk Thermal Throttling Threshold + GnbRegisterReadTN (D18F3x64_TYPE, D18F3x64_ADDRESS, &D18F3x64.Value, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, 0, StdHeader); + D0F0xBC_x1F30C.Field.LowThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) - 1 + 49) * 8); + D0F0xBC_x1F30C.Field.HighThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) + 49) * 8); + GnbRegisterWriteTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + GnbSmuServiceRequestV4 ( + GnbPciAddress, + SMC_MSG_CONFIG_LCLK_DPM, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + } + } else { + Status = AGESA_ERROR; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Exit [0x%x]\n", Status); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Mid Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + UINT32 Property; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + UINT8 SclkDid; + + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Enter\n"); + + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + + Property = TABLE_PROPERTY_DEAFULT; + Property |= GfxLibIsControllerPresent (StdHeader) ? 0 : TABLE_PROPERTY_IGFX_DISABLED; + Property |= GnbBuildOptions.LclkDeepSleepEn ? TABLE_PROPERTY_LCLK_DEEP_SLEEP : 0; + Property |= GnbBuildOptions.CfgOrbClockGatingEnable ? TABLE_PROPERTY_ORB_CLK_GATING : 0; + Property |= GnbBuildOptions.CfgIocLclkClockGatingEnable ? TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING : 0; + Property |= GnbBuildOptions.CfgIocSclkClockGatingEnable ? TABLE_PROPERTY_IOC_SCLK_CLOCK_GATING : 0; + Property |= GnbFmCheckIommuPresent (GnbHandle, StdHeader) ? 0: TABLE_PROPERTY_IOMMU_DISABLED; + Property |= GnbBuildOptions.SmuSclkClockGatingEnable ? TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING : 0; + + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + + if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) == 0) { + Status = GnbEnableIommuMmioV4 (GnbHandle, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + Status = GnbIommuMidInit (StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + // + // Set sclk to 100Mhz + // + SclkDid = GfxRequestSclkTNS3Save ( + GfxLibCalculateDidTN (98 * 100, StdHeader), + StdHeader + ); + + Status = GnbProcessTable ( + GnbHandle, + GnbMidInitTableTN, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + // + // Restore Sclk + // + GfxRequestSclkTNS3Save ( + SclkDid, + StdHeader + ); + + GnbCgttOverrideTN (Property, StdHeader); + + Status = GnbLclkDpmInitTN (StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c new file mode 100644 index 0000000000..efa2af1256 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c @@ -0,0 +1,128 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbNbInitLibV1.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbPostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbPostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCI_ADDR GnbAddress; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceTN Enter\n"); + GnbAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + Status = GnbSetTom (GnbAddress, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceTN Exit [0x%x]\n", Status); + return Status; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c new file mode 100644 index 0000000000..8d36a1f620 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c @@ -0,0 +1,1334 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize PP/DPM fuse table. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 64211 $ @e \$Date: 2012-01-17 23:00:25 -0600 (Tue, 17 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbNbInitLibV4.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define GNB_IGNORED_PARAM 0xFF +#define ORB_WRITE_ENABLE 0x100 +#define IOMMU_L1_WRITE_ENABLE 0x80000000ul +#define IOMMU_L2_WRITE_ENABLE 0x100 + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbRegisterWriteTNDump ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value + ); +AGESA_STATUS +GnbRegisterReadServiceTN ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbRegisterWriteServiceTN ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/*----------------------------------------------------------------------------------------*/ +/* + * Config Dct and Mp. + * + * + * + * @param[in] DctCfgSel Dct0/Dct1 + * @param[in] MemPsSel Mp0/Mp1 + * @param[in] StdHeader Standard configuration header + * + * @return true - Memory Pstate context has been changed + * @return false - Memory Pstate context has not been changed + */ +STATIC BOOLEAN +GnbDctMpConfigTN ( + IN UINT8 DctCfgSel, + IN UINT8 MemPsSel, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // Select DCT and memory P-state, D18F1x10C[DctCfgSel], D18F1x10C[MemPsSel] + D18F1x10C_STRUCT D18F1x10C; + BOOLEAN MemPsChangd; + ACCESS_WIDTH Width; + + MemPsChangd = FALSE; + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 1, D18F1x10C_ADDRESS), + Width, + &D18F1x10C.Value, + StdHeader + ); + + if ((DctCfgSel != 0xFF) && (DctCfgSel < 2)) { + D18F1x10C.Field.DctCfgSel = DctCfgSel; + } + + if ((MemPsSel != 0xFF) && (MemPsSel < 2) && (D18F1x10C.Field.MemPsSel != MemPsSel)) { + //Switches Mem Pstate + D18F1x10C.Field.MemPsSel = MemPsSel; + MemPsChangd = TRUE; + } + + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 1, D18F1x10C_ADDRESS), + Width, + &D18F1x10C.Value, + StdHeader + ); + + return MemPsChangd; + +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to Read Dct Additional Data. + * + * + * + * @param[in] Address D18F2x9c Register offset + * @param[in] DctCfgSel Dct0/Dct1 + * @param[in] MemPsSel Mp0/Mp1 + * @param[out] Value Read value + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbDctAdditionalDataReadTN ( + IN UINT32 Address, + IN UINT8 DctCfgSel, + IN UINT8 MemPsSel, + IN UINT32 Flags, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F2x98_dct0_STRUCT D18F2x98; + BOOLEAN PstateChanged; + ACCESS_WIDTH Width; + + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + + PstateChanged = GnbDctMpConfigTN ( + DctCfgSel, + MemPsSel, + Flags, + StdHeader + ); + + // Clear DctAccessWrite + D18F2x98.Field.DctOffset = Address & 0x3FFFFFFF; + D18F2x98.Field.DctAccessWrite = 0; + + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x98_dct0_ADDRESS : D18F2x98_dct1_ADDRESS)), + Width, + &D18F2x98.Value, + StdHeader + ); + + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x9C_dct0_ADDRESS : D18F2x9C_dct1_ADDRESS)), + Width, + Value, + StdHeader + ); + + if (PstateChanged) { + GnbDctMpConfigTN ( + DctCfgSel, + ((MemPsSel == 0) ? 1 : 0), + Flags, + StdHeader + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to Write Dct Additional Data. + * + * + * + * @param[in] Address D18F2x9c Register offset + * @param[in] DctCfgSel Dct0/Dct1 + * @param[in] MemPsSel Mp0/Mp1 + * @param[in] Value Write value + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbDctAdditionalDataWriteTN ( + IN UINT32 Address, + IN UINT8 DctCfgSel, + IN UINT8 MemPsSel, + IN UINT32 Flags, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F2x98_dct0_STRUCT D18F2x98; + BOOLEAN PstateChanged; + ACCESS_WIDTH Width; + + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + + PstateChanged = GnbDctMpConfigTN ( + DctCfgSel, + MemPsSel, + Flags, + StdHeader + ); + + // Put write data on + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x9C_dct0_ADDRESS : D18F2x9C_dct1_ADDRESS)), + Width, + Value, + StdHeader + ); + + // Set DctAccessWrite + D18F2x98.Field.DctOffset = Address & 0x3FFFFFFF; + D18F2x98.Field.DctAccessWrite = 1; + + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x98_dct0_ADDRESS : D18F2x98_dct1_ADDRESS)), + Width, + &D18F2x98.Value, + StdHeader + ); + + if (PstateChanged) { + GnbDctMpConfigTN ( + DctCfgSel, + ((MemPsSel == 0) ? 1 : 0), + Flags, + StdHeader + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to read all register spaces. + * + * + * + * @param[in] GnbHandle GNB handle + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value Return value + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterReadServiceTN ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return GnbRegisterReadTN (RegisterSpaceType, Address, Value, Flags, StdHeader); +} +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to read all register spaces. + * + * + * + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value Return value + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterReadTN ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ACCESS_WIDTH Width; + UINT32 TempValue; + UINT32 TempAddress; + BOOLEAN PstateChanged; + + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + TempAddress = 0; + TempValue = 0; + + + switch (RegisterSpaceType) { + case TYPE_D0F0: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D0F2: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D1F0: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 1, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D1F1: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 1, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_DxF0: + // Treat it as complete address for ports + GnbLibPciRead ( + Address, + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F1: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F2: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F3: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 3, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F4: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 4, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F5: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 5, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0x64: + // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00] + // Write enable bit7 + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0x98: + // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00] + // Write enable bit8 + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x94_ADDRESS), + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0xBC: + { + //SMU, access D0F0xBC_x[FFFFFFFF:00000000] + // No write enable + UINT64 TempData; + //ASSERT ((Address < 0xE0100000 || Address > 0xE0108FFFF) && (Address & 0x3) == 0); + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0xB8_ADDRESS), + (Address & (~0x3ull)), + Width, + &TempData, + StdHeader + ); + if ((Address & 0x3) != 0) { + //Non aligned access allowed to fuse block + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0xB8_ADDRESS), + (Address & (~0x3ull)) + 4, + Width, + ((UINT32 *) &TempData) + 1, + StdHeader + ); + } + * ((UINT32*) Value) = (UINT32) (TempData >> ((Address & 0x3) * 8)); + break; + } + case TYPE_D0F0xE4: + // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000] + // No write enable + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0xE0_ADDRESS), + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F2xF4: + // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00]. + // Write enable bit8 + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 2, 0xF0),//D0F2xF0_ADDRESS + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F2xFC: + // IOMMU L1 Config Index, access the registers D0F2xFC_x[FFFF:0000]_L1[3:0] + // Write enable bit31 + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 2, 0xF8),//D0F2xF8_ADDRESS + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_DxF0xE4: + // D[8:2]F0xE0 Root Port Index, access the registers D[8:2]F0xE4_x[FF:00] + // No write enable + TempValue = ((Address >> 16) & 0xFF); + TempAddress = Address & 0xFF; + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, (TempValue), 0, 0xE0),//DxF0xE0_ADDRESS + TempAddress, + Width, + Value, + StdHeader + ); + break; + + case TYPE_MSR: + LibAmdMsrRead (Address, Value, StdHeader); + break; + + case TYPE_GMM: + ASSERT (Address < 0x40000); + + if ((Address >= 0x600) && (Address <= 0x8FF)) { + // CG + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (Address - 0x600)), + Width, + Value, + StdHeader + ); + } else { + // SRBM + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0x80080000 | (Address & 0x3FFFF)), + Width, + Value, + StdHeader + ); + } + break; + + case TYPE_D18F2x9C_dct0: + GnbDctAdditionalDataReadTN ( + Address, + 0, + GNB_IGNORED_PARAM, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct0_mp0: + GnbDctAdditionalDataReadTN ( + Address, + 0, + 0, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct0_mp1: + GnbDctAdditionalDataReadTN ( + Address, + 0, + 1, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1: + GnbDctAdditionalDataReadTN ( + Address, + 1, + GNB_IGNORED_PARAM, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1_mp0: + GnbDctAdditionalDataReadTN ( + Address, + 1, + 0, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1_mp1: + GnbDctAdditionalDataReadTN ( + Address, + 1, + 1, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct0: + GnbDctMpConfigTN ( + 0, + GNB_IGNORED_PARAM, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct0_mp0: + PstateChanged = GnbDctMpConfigTN ( + 0, + 0, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 0, + 1, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct0_mp1: + PstateChanged = GnbDctMpConfigTN ( + 0, + 1, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 0, + 0, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct1: + GnbDctMpConfigTN ( + 1, + GNB_IGNORED_PARAM, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct1_mp0: + PstateChanged = GnbDctMpConfigTN ( + 1, + 0, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 1, + 1, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct1_mp1: + PstateChanged = GnbDctMpConfigTN ( + 1, + 1, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 1, + 0, + Flags, + StdHeader + ); + } + break; + + case TYPE_CGIND: + // CG index + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (0x8F8 - 0x600)), + Width, + &Address, + StdHeader + ); + // CG data + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (0x8FC - 0x600)), + Width, + Value, + StdHeader + ); + break; + + default: + ASSERT (FALSE); + break; + } + + + + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to write all register spaces. + * + * + * + * @param[in] GnbHandle GnbHandle + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value The value to write + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterWriteServiceTN ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return GnbRegisterWriteTN (RegisterSpaceType, Address, Value, Flags, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to write all register spaces. + * + * + * + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value The value to write + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterWriteTN ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + ACCESS_WIDTH Width; + UINT32 TempValue; + UINT32 TempAddress; + PCI_ADDR PciAddress; + BOOLEAN PstateChanged; + + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + TempAddress = 0; + TempValue = 0; + + GNB_DEBUG_CODE ( + GnbRegisterWriteTNDump (RegisterSpaceType, Address, Value); + ); + + switch (RegisterSpaceType) { + case TYPE_D0F0: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D0F2: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D1F0: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 1, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D1F1: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 1, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_DxF0: + // Treat it as complete address for ports + GnbLibPciWrite ( + Address, + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F1: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F2: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F3: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 3, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F4: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 4, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F5: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 5, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0x64: + // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00] + // Write enable bit7 + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + Address | IOC_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0x98: + // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00] + // Write enable bit8 + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x94_ADDRESS), + Address | ORB_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0xBC: + //SMU, access D0F0xBC_x[FFFFFFFF:00000000] + // No write enable + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0xE4: + // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000] + // No write enable + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, D0F0xE0_ADDRESS), + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F2xF4: + // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00]. + // Write enable bit8 + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 2, 0xF0),//D0F2xF0_ADDRESS + Address | IOMMU_L2_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F2xFC: + // IOMMU L1 Config Index, access the registers D0F2xFC_x[FFFF:0000]_L1[3:0] + // Write enable bit31 + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 2, 0xF8),//D0F2xF8_ADDRESS + Address | IOMMU_L1_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case TYPE_DxF0xE4: + // D[8:2]F0xE0 Root Port Index, access the registers D[8:2]F0xE4_x[FF:00] + // No write enable + TempValue = ((Address >> 16) & 0xFF); + TempAddress = Address & 0xFF; + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, (TempValue), 0, 0xE0),//DxF0xE0_ADDRESS + TempAddress, + Width, + Value, + StdHeader + ); + break; + + case TYPE_MSR: + LibAmdMsrWrite (Address, Value, StdHeader); + break; + + case TYPE_GMM: + ASSERT (Address < 0x40000); + + if ((Address >= 0x600) && (Address <= 0x8FF)) { + // CG + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (Address - 0x600)), + Width, + Value, + StdHeader + ); + } else { + // SRBM + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0x80080000 | (Address & 0x3FFFF)), + Width, + Value, + StdHeader + ); + } + break; + + case TYPE_D18F2x9C_dct0: + GnbDctAdditionalDataWriteTN ( + Address, + 0, + GNB_IGNORED_PARAM, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct0_mp0: + GnbDctAdditionalDataWriteTN ( + Address, + 0, + 0, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct0_mp1: + GnbDctAdditionalDataWriteTN ( + Address, + 0, + 1, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1: + GnbDctAdditionalDataWriteTN ( + Address, + 1, + GNB_IGNORED_PARAM, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1_mp0: + GnbDctAdditionalDataWriteTN ( + Address, + 1, + 0, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1_mp1: + GnbDctAdditionalDataWriteTN ( + Address, + 1, + 1, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct0: + GnbDctMpConfigTN ( + 0, + GNB_IGNORED_PARAM, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct0_mp0: + PstateChanged = GnbDctMpConfigTN ( + 0, + 0, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 0, + 1, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct0_mp1: + PstateChanged = GnbDctMpConfigTN ( + 0, + 1, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 0, + 0, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct1: + GnbDctMpConfigTN ( + 1, + GNB_IGNORED_PARAM, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct1_mp0: + PstateChanged = GnbDctMpConfigTN ( + 1, + 0, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 1, + 1, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct1_mp1: + PstateChanged = GnbDctMpConfigTN ( + 1, + 1, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 1, + 0, + Flags, + StdHeader + ); + } + break; + + case TYPE_CGIND: + // CG index + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (0x8F8 - 0x600)), + Width, + &Address, + StdHeader + ); + // CG data + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (0x8FC - 0x600)), + Width, + Value, + StdHeader + ); + break; + case TYPE_SMU_MSG: + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + GnbSmuServiceRequestV4 (PciAddress, (UINT8) Address, Flags, StdHeader); + break; + default: + ASSERT (FALSE); + break; + } + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to dump all write register spaces. + * + * + * + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset + * @param[in] Value The value to write + */ +VOID +GnbRegisterWriteTNDump ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value + ) +{ + IDS_HDT_CONSOLE (NB_MISC, " R WRITE Space %s Address 0x%04x, Value 0x%04x\n", + (RegisterSpaceType == TYPE_D0F0) ? "TYPE_D0F0" : ( + (RegisterSpaceType == TYPE_D0F0x64) ? "TYPE_D0F0x64" : ( + (RegisterSpaceType == TYPE_D0F0x98) ? "TYPE_D0F0x98" : ( + (RegisterSpaceType == TYPE_D0F0xBC) ? "TYPE_D0F0xBC" : ( + (RegisterSpaceType == TYPE_D0F0xE4) ? "TYPE_D0F0xE4" : ( + (RegisterSpaceType == TYPE_DxF0) ? "TYPE_DxF0" : ( + (RegisterSpaceType == TYPE_DxF0xE4) ? "TYPE_DxF0xE4" : ( + (RegisterSpaceType == TYPE_D0F2) ? "TYPE_D0F2" : ( + (RegisterSpaceType == TYPE_D0F2xF4) ? "TYPE_D0F2xF4" : ( + (RegisterSpaceType == TYPE_D0F2xFC) ? "TYPE_D0F2xFC" : ( + (RegisterSpaceType == TYPE_D18F1) ? "TYPE_D18F1" : ( + (RegisterSpaceType == TYPE_D18F2) ? "TYPE_D18F2" : ( + (RegisterSpaceType == TYPE_D18F3) ? "TYPE_D18F3" : ( + (RegisterSpaceType == TYPE_D18F4) ? "TYPE_D18F4" : ( + (RegisterSpaceType == TYPE_D18F5) ? "TYPE_D18F5" : ( + (RegisterSpaceType == TYPE_MSR) ? "TYPE_MSR" : ( + (RegisterSpaceType == TYPE_D1F0) ? "TYPE_D1F0" : ( + (RegisterSpaceType == TYPE_D1F1) ? "TYPE_D1F1" : ( + (RegisterSpaceType == TYPE_GMM) ? "TYPE_GMM" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0) ? "TYPE_D18F2x9C_dct0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp0) ? "TYPE_D18F2x9C_dct0_mp0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp1) ? "TYPE_D18F2x9C_dct0_mp1" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1) ? "TYPE_D18F2x9C_dct1" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp0) ? "TYPE_D18F2x9C_dct1_mp0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp1) ? "TYPE_D18F2x9C_dct1_mp1" : ( + (RegisterSpaceType == TYPE_D18F2_dct0) ? "TYPE_D18F2_dct0" : ( + (RegisterSpaceType == TYPE_D18F2_dct0_mp0) ? "TYPE_D18F2_dct0_mp0" : ( + (RegisterSpaceType == TYPE_D18F2_dct0_mp1) ? "TYPE_D18F2_dct0_mp1" : ( + (RegisterSpaceType == TYPE_D18F2_dct1) ? "TYPE_D18F2_dct1" : ( + (RegisterSpaceType == TYPE_D18F2_dct1_mp0) ? "TYPE_D18F2_dct1_mp0" : ( + (RegisterSpaceType == TYPE_SMU_MSG) ? "TYPE_SMU_MSG" : ( + (RegisterSpaceType == TYPE_D18F2_dct1_mp1) ? "TYPE_D18F2_dct1_mp1" : "Invalid"))))))))))))))))))))))))))))))), + Address, + *((UINT32*)Value) + ); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h new file mode 100644 index 0000000000..6de5c469ae --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h @@ -0,0 +1,101 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * various service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBREGISTERACCTN_H_ +#define _GNBREGISTERACCTN_H_ + +AGESA_STATUS +GnbRegisterWriteTN ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbRegisterReadTN ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +// Marco +// DxF0 Port space +#define PORT_SPACE(Dev, Offset) MAKE_SBDFO (0, 0, Dev, 0, Offset) + +// DxF0xE4 Port indirect space +#define PORTINDT_SPACE(Dev , Func, Offset) ((((UINT32) (Dev)) << 16) | (((UINT32) (Func)) << 8) | \ + ((UINT32)(Offset))) + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h new file mode 100644 index 0000000000..8c44a71d89 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h @@ -0,0 +1,14126 @@ +/** + * @file + * + * SMU firmware + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 65874 $ @e \$Date: 2012-02-26 21:24:59 -0600 (Sun, 26 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBSMUFIRMWARETN_H_ +#define _GNBSMUFIRMWARETN_H_ + +UINT32 FirmwareTN[] = { + 0x000a0004, + 0x00000040, + 0x000036a1, + 0x00010100, + 0xeee2b111, + 0x724cbe84, + 0xf7cde4cd, + 0xbf04e85e, + 0x9bdebdfc, + 0x0001d7f4, + 0x0001d904, + 0x00000000, + 0x0001d925, + 0x0001d934, + 0x0001d848, + 0x0001da6c, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xaa55aa55, + 0x98000000, + 0x98000000, + 0xd0000000, + 0x78010001, + 0x38210100, + 0xd0e10000, + 0xd1210000, + 0xf8000039, + 0x5b9d0000, + 0xf8000062, + 0xf80033ff, + 0xe0000098, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0x37de0004, + 0xf8000044, + 0xf8003456, + 0xe000007d, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0xf8000052, + 0xf800344e, + 0xe0000088, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0x37de0004, + 0xf8000034, + 0xf8003458, + 0xe000006d, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0x37de0004, + 0xf800002c, + 0xf8003462, + 0xe0000065, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0xf8000025, + 0x34010002, + 0xf8003476, + 0xe000005d, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0x37de0004, + 0xf800001c, + 0xf8003464, + 0xe0000055, + 0x34000000, + 0x34000000, + 0x34000000, + 0x98000000, + 0x781c0001, + 0x3b9cebfc, + 0x781a0002, + 0x3b5a5b80, + 0x78010001, + 0x3821db84, + 0x78030001, + 0x3863e038, + 0x44230004, + 0x58200000, + 0x34210004, + 0xe3fffffd, + 0x34010000, + 0x34020000, + 0x78030001, + 0x3863fe80, + 0x58610000, + 0x58610018, + 0x34030000, + 0xf80002b5, + 0xf800013d, + 0x379cff80, + 0x5b810004, + 0x5b820008, + 0x5b83000c, + 0x5b840010, + 0x5b850014, + 0x5b860018, + 0x5b87001c, + 0x5b880020, + 0x5b890024, + 0x5b8a0028, + 0x5b9e0078, + 0x5b9f007c, + 0x2b810080, + 0x5b810074, + 0xbb800800, + 0x34210080, + 0x5b810070, + 0x98210800, + 0xd0010000, + 0xc3a00000, + 0x379cff80, + 0x5b810004, + 0x5b820008, + 0x5b83000c, + 0x5b840010, + 0x5b850014, + 0x5b860018, + 0x5b87001c, + 0x5b880020, + 0x5b890024, + 0x5b8a0028, + 0x5b8b002c, + 0x5b8c0030, + 0x5b8d0034, + 0x5b8e0038, + 0x5b8f003c, + 0x5b900040, + 0x5b910044, + 0x5b920048, + 0x5b93004c, + 0x5b940050, + 0x5b950054, + 0x5b960058, + 0x5b97005c, + 0x5b980060, + 0x5b990064, + 0x5b9a0068, + 0x5b9b006c, + 0x5b9e0078, + 0x5b9f007c, + 0x2b810080, + 0x5b810074, + 0xbb800800, + 0x34210080, + 0x5b810070, + 0x98210800, + 0xd0010000, + 0xc3a00000, + 0x34010002, + 0xd0010000, + 0x2b810004, + 0x2b820008, + 0x2b83000c, + 0x2b840010, + 0x2b850014, + 0x2b860018, + 0x2b87001c, + 0x2b880020, + 0x2b890024, + 0x2b8a0028, + 0x2b9d0074, + 0x2b9e0078, + 0x2b9f007c, + 0x2b9c0070, + 0x34000000, + 0xc3c00000, + 0x34010002, + 0xd0010000, + 0x2b810004, + 0x2b820008, + 0x2b83000c, + 0x2b840010, + 0x2b850014, + 0x2b860018, + 0x2b87001c, + 0x2b880020, + 0x2b890024, + 0x2b8a0028, + 0x2b8b002c, + 0x2b8c0030, + 0x2b8d0034, + 0x2b8e0038, + 0x2b8f003c, + 0x2b900040, + 0x2b910044, + 0x2b920048, + 0x2b93004c, + 0x2b940050, + 0x2b950054, + 0x2b960058, + 0x2b97005c, + 0x2b980060, + 0x2b990064, + 0x2b9a0068, + 0x2b9b006c, + 0x2b9d0074, + 0x2b9e0078, + 0x2b9f007c, + 0x2b9c0070, + 0x34000000, + 0xc3e00000, + 0x379cfffc, + 0x5b9d0004, + 0xf80000cc, + 0x2b9d0004, + 0x379c0004, + 0xc3a00000, + 0x379cfffc, + 0x5b9d0004, + 0xf80000cd, + 0x2b9d0004, + 0x379c0004, + 0xc3a00000, + 0x379cfff4, + 0x5b8b000c, + 0x5b8c0008, + 0x5b9d0004, + 0x780c0001, + 0xb9801000, + 0x3842db84, + 0x34010001, + 0x58410000, + 0x90201000, + 0x90401800, + 0x340b0001, + 0xa0621800, + 0x34050000, + 0x44650018, + 0x78020001, + 0x3842db8c, + 0xb8402000, + 0xa1630800, + 0x44200009, + 0x28430000, + 0x5c60000c, + 0x90201000, + 0xa5600800, + 0xa0411000, + 0xd0220000, + 0xd04b0000, + 0xe3ffffee, + 0x3d6b0001, + 0x34a50001, + 0x34840008, + 0x34420008, + 0xe3fffff2, + 0x28820004, + 0xb8a00800, + 0xd8600000, + 0xd04b0000, + 0xe3ffffe4, + 0x398cdb84, + 0x34010000, + 0x59810000, + 0x2b8b000c, + 0x2b8c0008, + 0x2b9d0004, + 0x379c000c, + 0xc3a00000, + 0x78020001, + 0x3842db88, + 0x28440000, + 0x5c80000f, + 0x34010001, + 0x58410000, + 0x78030001, + 0xb8801000, + 0x3863db8c, + 0x3401001f, + 0x58620000, + 0x58620004, + 0x3421ffff, + 0x34630008, + 0x4c20fffc, + 0x90000800, + 0x38210001, + 0xd0010000, + 0xc3a00000, + 0x379cfff0, + 0x5b8b0010, + 0x5b8c000c, + 0x5b8d0008, + 0x5b9d0004, + 0xb8205800, + 0xb8406800, + 0xb8606000, + 0xfbffffe5, + 0x34010001, + 0xbc2b2000, + 0x3402fffe, + 0x3401001f, + 0x502b0002, + 0xe0000019, + 0x90001800, + 0x3401fffe, + 0xa0611800, + 0xd0030000, + 0x78010001, + 0x3d620003, + 0x3821db8c, + 0xb4411000, + 0x584d0004, + 0x584c0000, + 0x90200800, + 0xa4801000, + 0x5d800003, + 0xa0220800, + 0xe0000002, + 0xb8240800, + 0xd0210000, + 0x78010001, + 0x3821db84, + 0x28210000, + 0x38630001, + 0x5c200002, + 0xd0030000, + 0x34020000, + 0xb8400800, + 0x2b8b0010, + 0x2b8c000c, + 0x2b8d0008, + 0x2b9d0004, + 0x379c0010, + 0xc3a00000, + 0x34020001, + 0xbc411000, + 0x3403fffe, + 0xa4402000, + 0x3402001f, + 0x50410002, + 0xe000000f, + 0x90001000, + 0x3401fffe, + 0xa0411000, + 0xd0020000, + 0x90200800, + 0xa0240800, + 0xd0210000, + 0x78010001, + 0x3821db84, + 0x28210000, + 0x38420001, + 0x5c200002, + 0xd0020000, + 0x34030000, + 0xb8600800, + 0xc3a00000, + 0x379cfff8, + 0x5b8b0008, + 0x5b9d0004, + 0xb8205800, + 0xfbffffa4, + 0x34010001, + 0xbc2b1800, + 0x3402fffe, + 0x3401001f, + 0x502b0002, + 0xe000000f, + 0x90001000, + 0x3401fffe, + 0xa0411000, + 0xd0020000, + 0x90200800, + 0xb8230800, + 0xd0210000, + 0x78010001, + 0x3821db84, + 0x28210000, + 0x38420001, + 0x5c200002, + 0xd0020000, + 0x34020000, + 0xb8400800, + 0x2b8b0008, + 0x2b9d0004, + 0x379c0008, + 0xc3a00000, + 0x379cfff8, + 0x5b8b0008, + 0x5b9d0004, + 0xb8205800, + 0xfbffff86, + 0x90001000, + 0x3401fffe, + 0xa0411000, + 0xd0020000, + 0xd02b0000, + 0x78010001, + 0x3821db84, + 0x28210000, + 0x38420001, + 0x5c200002, + 0xd0020000, + 0x2b8b0008, + 0x2b9d0004, + 0x379c0008, + 0xc3a00000, + 0x90000800, + 0x3402fffe, + 0xa0220800, + 0xd0010000, + 0x90200800, + 0x34020000, + 0xd0220000, + 0xc3a00000, + 0x34080001, + 0xac000007, + 0x34010001, + 0xd0810000, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0xc3a00000, + 0x34010001, + 0xd0610000, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0xc3a00000, + 0xc3a00000, + 0x78038000, + 0x78018000, + 0x38630000, + 0x38210040, + 0x58610180, + 0x34010000, + 0x58610100, + 0x78014000, + 0x34020001, + 0x58620104, + 0x38210003, + 0x5861010c, + 0x34010003, + 0x5861010c, + 0x34010002, + 0x58610110, + 0x34010004, + 0x5861000c, + 0x28610004, + 0x38210002, + 0x58610004, + 0xc3a00000, + 0x379cffe8, + 0x5b8b0018, + 0x5b8c0014, + 0x5b8d0010, + 0x5b8e000c, + 0x5b8f0008, + 0x5b9d0004, + 0x7805e000, + 0xb8a00800, + 0x38211000, + 0x28210004, + 0x780d0001, + 0x780c0001, + 0x202101fc, + 0x00220002, + 0x780b0001, + 0x780e0001, + 0x780f0001, + 0x78040001, + 0x74410007, + 0x39add848, + 0x398cd7f4, + 0x396bd925, + 0x39ced904, + 0x39eff160, + 0x3884e02c, + 0x5c200003, + 0x34022000, + 0xe0000014, + 0x7441003f, + 0x5c200003, + 0x3c42000a, + 0xe0000010, + 0x7441005f, + 0x5c200006, + 0x3c42000b, + 0x7801ffff, + 0x38210000, + 0xb4411000, + 0xe0000009, + 0x3c41000c, + 0x7443007e, + 0x7802fffc, + 0x38420000, + 0xb4221000, + 0x44600003, + 0x78020008, + 0x38420000, + 0x7801e000, + 0x38213048, + 0x58220000, + 0x7801e000, + 0x58820000, + 0x38212000, + 0x28210000, + 0x2021007f, + 0xb8201000, + 0x5c200007, + 0x38a51000, + 0x28a20004, + 0x78010003, + 0x3821f800, + 0xa0411000, + 0x0042000b, + 0xb8400800, + 0xf80029f4, + 0x7801e000, + 0x38211000, + 0x283d001c, + 0x7802e000, + 0x38422208, + 0x28410000, + 0x78090001, + 0x78030001, + 0x38210001, + 0x58410000, + 0x3929f000, + 0x3863ffff, + 0x340a0000, + 0x592a0000, + 0x35290004, + 0x55230002, + 0xe3fffffd, + 0x78020001, + 0x78018000, + 0x3842f15c, + 0x38210000, + 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0xb5470800, + 0x28210000, + 0xd8200000, + 0x78018001, + 0x38210000, + 0x28210058, + 0xe3ffff99, + 0xb9a01800, + 0x3863e028, + 0x40610000, + 0x34040001, + 0x3422ffff, + 0x202100ff, + 0x50810008, + 0x30620000, + 0x2b8b0010, + 0x2b8c000c, + 0x2b8d0008, + 0x2b9d0004, + 0x379c0010, + 0xc3a00000, + 0x30620000, + 0x204100ff, + 0x5c20ff7f, + 0x78018000, + 0x38210000, + 0x58240008, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0xe3ffff76, + 0x78060001, + 0x38c6f1a0, + 0x78050001, + 0x38a5d7f4, + 0x30c1000b, + 0x28a70028, + 0xb8202000, + 0x34080000, + 0x34030003, + 0x48e30009, + 0x28a10038, + 0x34220060, + 0x40410003, + 0x3442ffe0, + 0x5c200010, + 0x3463ffff, + 0x48e30002, + 0xe3fffffb, + 0x28a10010, + 0x4501000f, + 0x7c810010, + 0x5c20000b, + 0x40c10002, + 0x34020000, + 0x30c10008, + 0x40c10000, + 0x30c10009, + 0x78010001, + 0x3821db7c, + 0xe000000c, + 0xb8604000, + 0xe3fffff3, + 0x7c810020, + 0x5c20001a, + 0x40c10003, + 0x34020001, + 0x30c10008, + 0x40c10001, + 0x30c10009, + 0x78010001, + 0x3821db7c, + 0x7804e000, + 0x30220000, + 0x38842018, + 0x28820000, + 0x40c10008, + 0x3405ff80, + 0xa0451000, + 0x2021007f, + 0xb8411000, + 0x7803e000, + 0x58820000, + 0x38632010, + 0x40c20009, + 0x28610000, + 0x2042007f, + 0xa0250800, + 0xb8220800, + 0x58610000, + 0xc3a00000, + 0x379cfffc, + 0x5b9d0004, + 0x78010001, + 0x3821f150, + 0x40210002, + 0x78028000, + 0x78038008, + 0x78040001, + 0x38420010, + 0x38630000, + 0x3884f1a0, + 0x4420000a, + 0x28420000, + 0x34010000, + 0x58610220, + 0x4083000a, + 0x20420030, + 0xb8400800, + 0x3082000b, + 0x44430002, + 0xfbffffb0, + 0x2b9d0004, + 0x379c0004, + 0xc3a00000, + 0x379cfff4, + 0x5b8b000c, + 0x5b8c0008, + 0x5b9d0004, + 0xfbffd231, + 0xb8206000, + 0x780b0001, + 0xfbffd232, + 0x396bf1a0, + 0x41620007, + 0x78030001, + 0x3863db7c, + 0x3022000f, + 0x78010001, + 0x3182000f, + 0x3821f150, + 0x40210002, + 0x34020010, + 0x44200007, + 0x40610000, + 0x7c210001, + 0x5c200002, + 0x34020020, + 0xb8400800, + 0xfbffff94, + 0x2b8b000c, + 0x2b8c0008, + 0x2b9d0004, + 0x379c000c, + 0xc3a00000, + 0xc3a00000, + 0xc3a00000, + 0xc3a00000, + 0x01300000, + 0x01310000, + 0x01310000, + 0x01320000, + 0x01330000, + 0x01100000, + 0x01110000, + 0x02110000, + 0x01120000, + 0x01130000, + 0x01200000, + 0x01210000, + 0x02210000, + 0x01220000, + 0x01230000, + 0x00000100, + 0x00000000, + 0x000a0003, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000007, + 0x0001f000, + 0x0001f000, + 0x0001f000, + 0x000113dc, + 0x00011318, + 0x01010101, + 0x01010101, + 0x7fff0000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x000a0003, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000007, + 0x0001f200, + 0x0001f200, + 0x0001f200, + 0x00011bf8, + 0x00011b58, + 0x0001f8f0, + 0x00015000, + 0x0001420c, + 0x00010e64, + 0x00011928, + 0x0001b748, + 0x0001b8dc, + 0x00000000, + 0x00017510, + 0x000156bc, + 0x00015d18, + 0x00016528, + 0x000169d0, + 0x00016e2c, + 0x000174d0, + 0x00012f3c, + 0x0001d6d4, + 0x0000ea60, + 0x00004e20, + 0x64000000, + 0x000186a0, + 0x0001f480, + 0x80402010, + 0x08040200, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x01010000, + 0x01000100, + 0x00000000, + 0x00000000, + 0x01010101, + 0x00000000, + 0x00000000, + 0x00000000, + 0x0001f120, + 0x00000000, + 0x04000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00003178, + 0x00000000, + 0x00003171, + 0x00000000, + 0x00003172, + 0x00000000, + 0x00007103, + 0x00000000, + 0x00007116, + 0x00000000, + 0x0000317d, + 0x00000000, + 0x00007103, + 0x00000000, + 0x0000712e, + 0x00000000, + 0x0000710f, + 0x00000000, + 0x00007110, + 0x00000000, + 0x00007111, + 0x00000000, + 0x00007112, + 0x00000000, + 0x00007113, + 0x00000000, + 0x0000715c, + 0x00000000, + 0x0000715d, + 0x00000000, + 0x00007162, + 0x00000000, + 0x00007117, + 0x00000000, + 0x00007157, + 0x00000000, + 0x00007106, + 0x00000000, + 0x0001ab20, + 0x00010788, + 0x0001a8d8, + 0x00019fec, + 0x0001a4a0, + 0x00019a00, + 0x0001a450, + 0x000199b4, + 0x0001a420, + 0x00011d94, + 0x00010418, + 0x00010430, + 0x00013138, + 0x00013d5c, + 0x00012398, + 0x00015970, + 0x0001244c, + 0x0001bb5c, + 0x0001b864, + 0x00012c48, + 0x00012300, + 0x00012354, + 0x00016834, + 0x00012530, + 0x00016e2c, + 0x0001a984, + 0x0001396c, + 0x0001aa60, + 0x00011e80, + 0x0001d380, + 0x00011bf8, + 0x00011b58, + 0x00014c0c, + 0x00014e28, + 0x0001a704, + 0x00019d34, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x0001c1a8, + 0x0001c1e0, + 0x00012f3c, + 0x0001724c, + 0x0001aab8, + 0x00010788, + 0x00010788, + 0x00010788, + 0x0001af7c, + 0x00010788, + 0x00010788, + 0x00010788, + 0x0001adb4, + 0x00012f34, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x0001d7ac, + 0x0001d7b0, + 0x00010788, + 0x000121b8, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00013340, + 0x0001420c, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c new file mode 100644 index 0000000000..75f8c9cb56 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c @@ -0,0 +1,1121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbRegistersTN.h" +#include "GnbInitTN.h" +#include "cpuFamRegisters.h" +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN [] = { + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_SMUCsrIsocEn_MASK, + (1 << D0F0x98_x07_SMUCsrIsocEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x98_x1E_TYPE, + D0F0x98_x1E_ADDRESS, + D0F0x98_x1E_HiPriEn_MASK, + (1 << D0F0x98_x1E_HiPriEn_OFFSET) + ), + + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN [] = { + // Config GFX to legacy mode initially + GNB_ENTRY_RMW ( + D0F0x64_x1D_TYPE, + D0F0x64_x1D_ADDRESS, + D0F0x64_x1D_IntGfxAsPcieEn_MASK, + 0 + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F87C_TYPE, + D0F0xBC_x1F87C_ADDRESS, + D0F0xBC_x1F87C_LL_PCIE_LoadStep_MASK | D0F0xBC_x1F87C_LL_VddNbLoadStepBase_MASK, + 0 + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F880_TYPE, + D0F0xBC_x1F880_ADDRESS, + D0F0xBC_x1F880_LL_VCE_LoadStep_MASK | D0F0xBC_x1F880_LL_UVD_LoadStep_MASK, + 0 + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F884_TYPE, + D0F0xBC_x1F884_ADDRESS, + D0F0xBC_x1F884_LL_DCE2_LoadStep_MASK | D0F0xBC_x1F884_LL_DCE_LoadStep_MASK, + 0 + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F888_TYPE, + D0F0xBC_x1F888_ADDRESS, + D0F0xBC_x1F888_LL_GPU_LoadStep_MASK, + 0 + ), + // Configure load line VID + GNB_ENTRY_WR ( + D0F0xBC_x1F3D8_TYPE, + D0F0xBC_x1F3D8_ADDRESS, + (0x00 << D0F0xBC_x1F3D8_LoadLineTrim3_OFFSET) | + (0xFE << D0F0xBC_x1F3D8_LoadLineTrim2_OFFSET) | + (0xFC << D0F0xBC_x1F3D8_LoadLineTrim1_OFFSET) | + (0xF6 << D0F0xBC_x1F3D8_LoadLineTrim0_OFFSET) + ), + GNB_ENTRY_WR ( + D0F0xBC_x1F3DC_TYPE, + D0F0xBC_x1F3DC_ADDRESS, + (0x08 << D0F0xBC_x1F3DC_LoadLineTrim7_OFFSET) | + (0x06 << D0F0xBC_x1F3DC_LoadLineTrim6_OFFSET) | + (0x04 << D0F0xBC_x1F3DC_LoadLineTrim5_OFFSET) | + (0x02 << D0F0xBC_x1F3DC_LoadLineTrim4_OFFSET) + ), + GNB_ENTRY_WR ( + D0F0xBC_x1F404_TYPE, + D0F0xBC_x1F404_ADDRESS, + (0x19 << D0F0xBC_x1F404_LoadLineOffset3_OFFSET) | + (0x00 << D0F0xBC_x1F404_LoadLineOffset2_OFFSET) | + (0xE7 << D0F0xBC_x1F404_LoadLineOffset1_OFFSET) | + (0x00 << D0F0xBC_x1F404_LoadLineOffset0_OFFSET) + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F3F8_TYPE, + D0F0xBC_x1F3F8_ADDRESS, + D0F0xBC_x1F3F8_SviInitLoadLineVdd_OFFSET, D0F0xBC_x1F3F8_SviInitLoadLineVdd_WIDTH, + D0F0xBC_xE01040A8_TYPE, + D0F0xBC_xE01040A8_ADDRESS, + D0F0xBC_xE01040A8_SviLoadLineVdd_OFFSET, D0F0xBC_xE01040A8_SviLoadLineVdd_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F3F8_TYPE, + D0F0xBC_x1F3F8_ADDRESS, + D0F0xBC_x1F3F8_SviInitLoadLineVddNB_OFFSET, D0F0xBC_x1F3F8_SviInitLoadLineVddNB_WIDTH, + D0F0xBC_xE01040A8_TYPE, + D0F0xBC_xE01040A8_ADDRESS, + D0F0xBC_xE01040A8_SviLoadLineVddNb_OFFSET, D0F0xBC_xE01040A8_SviLoadLineVddNb_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F3F8_TYPE, + D0F0xBC_x1F3F8_ADDRESS, + D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET, D0F0xBC_x1F3F8_SviTrimValueVdd_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH + ), + GNB_ENTRY_COPY ( + D18F5x12C_TYPE, + D18F5x12C_ADDRESS, + D18F5x12C_CoreLoadLineTrim_OFFSET, D18F5x12C_CoreLoadLineTrim_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F3F8_TYPE, + D0F0xBC_x1F3F8_ADDRESS, + D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET, D0F0xBC_x1F3F8_SviTrimValueVddNB_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH + ), + GNB_ENTRY_COPY ( + D18F5x188_TYPE, + D18F5x188_ADDRESS, + D18F5x188_NbLoadLineTrim_OFFSET, D18F5x188_NbLoadLineTrim_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F3FC_TYPE, + D0F0xBC_x1F3FC_ADDRESS, + D0F0xBC_x1F3FC_SviVidStepBase_MASK | D0F0xBC_x1F3FC_SviVidStep_MASK, + (0x1838 << D0F0xBC_x1F3FC_SviVidStepBase_OFFSET) | (0x19 << D0F0xBC_x1F3FC_SviVidStep_OFFSET) + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F400_TYPE, + D0F0xBC_x1F400_ADDRESS, + D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_x1F400_SviLoadLineOffsetVdd_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH + ), + GNB_ENTRY_COPY ( + D18F5x12C_TYPE, + D18F5x12C_ADDRESS, + D18F5x12C_CoreOffsetTrim_OFFSET, D18F5x12C_CoreOffsetTrim_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F400_TYPE, + D0F0xBC_x1F400_ADDRESS, + D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET, D0F0xBC_x1F400_SviLoadLineOffsetVddNB_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F400_TYPE, + D0F0xBC_x1F400_ADDRESS, + D0F0xBC_x1F400_SviLoadLineOffsetVddNB_MASK | D0F0xBC_x1F400_SviLoadLineOffsetVdd_MASK, + (2 << D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET) | (2 << D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET) + ), +// GNB_ENTRY_COPY ( +// D18F5x188_TYPE, +// D18F5x188_ADDRESS, +// D18F5x188_NbOffsetTrim_OFFSET, D18F5x188_NbOffsetTrim_WIDTH, +// D0F0xBC_xE0104184_TYPE, +// D0F0xBC_xE0104184_ADDRESS, +// D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH +// ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D18F5x188_TYPE, + D18F5x188_ADDRESS, + D18F5x188_NbLoadLineTrim_MASK,// | D18F5x188_NbOffsetTrim_MASK, + (3 << D18F5x188_NbLoadLineTrim_OFFSET)// | (2 << D18F5x188_NbOffsetTrim_OFFSET) + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D18F5x12C_TYPE, + D18F5x12C_ADDRESS, + D18F5x12C_CoreLoadLineTrim_MASK | D18F5x12C_CoreOffsetTrim_MASK, + (3 << D18F5x12C_CoreLoadLineTrim_OFFSET) | (2 << D18F5x12C_CoreOffsetTrim_OFFSET) + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F3F8_TYPE, + D0F0xBC_x1F3F8_ADDRESS, + D0F0xBC_x1F3F8_SviTrimValueVdd_MASK | D0F0xBC_x1F3F8_SviTrimValueVddNB_MASK, + (3 << D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET) | (3 << D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET) + ), + // Enable SVI2 + GNB_ENTRY_RMW ( + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_SviMode_MASK, + (1 << D0F0xBC_x1F428_SviMode_OFFSET) + ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbEarlyInitTableTN [] = { + GNB_ENTRY_WR ( + D0F0x04_TYPE, + D0F0x04_ADDRESS, + (0x1 << D0F0x04_MemAccessEn_OFFSET) | (0x1 << D0F0x04_BusMasterEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x4C_TYPE, + D0F0x4C_ADDRESS, + D0F0x4C_CfgRdTime_MASK, + 0x2 << D0F0x4C_CfgRdTime_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x84_TYPE, + D0F0x84_ADDRESS, + D0F0x84_Ev6Mode_MASK, + 0x1 << D0F0x84_Ev6Mode_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x64_x46_TYPE, + D0F0x64_x46_ADDRESS, + 0x6 , + 1 << D0F0x64_x46_Msi64bitEn_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x0C_TYPE, + D0F0x98_x0C_ADDRESS, + D0F0x98_x0C_StrictSelWinnerEn_MASK, + 1 << D0F0x98_x0C_StrictSelWinnerEn_OFFSET + ), + // Configure PM timer + GNB_ENTRY_RMW ( + D0F0xBC_x1F468_TYPE, + D0F0xBC_x1F468_ADDRESS, + D0F0xBC_x1F468_TimerPeriod_MASK, + D0F0xBC_x1F468_TimerPeriod_Value << D0F0xBC_x1F468_TimerPeriod_OFFSET + ), + GNB_ENTRY_WR ( + SMU_MSG_TYPE, + SMC_MSG_EN_PM_CNTL, + 0 + ), + //Enable voltage controller + GNB_ENTRY_RMW ( + D0F0xBC_x1F460_TYPE, + D0F0xBC_x1F460_ADDRESS, + D0F0xBC_x1F460_VoltageCntl_MASK, + 1 << D0F0xBC_x1F460_VoltageCntl_OFFSET + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F384_TYPE, + D0F0xBC_x1F384_ADDRESS, + D0F0xBC_x1F384_FirmwareVid_OFFSET, + D0F0xBC_x1F384_FirmwareVid_WIDTH, + D0F0xBC_xE0001008_TYPE , + D0F0xBC_xE0001008_ADDRESS, + D0F0xBC_xE0001008_SClkVid0_OFFSET, + D0F0xBC_xE0001008_SClkVid0_WIDTH + ), + GNB_ENTRY_WR ( + SMU_MSG_TYPE, + SMC_MSG_CONFIG_VOLTAGE_CNTL, + 0 + ), + GNB_ENTRY_POLL ( + GMMx7B0_TYPE, + GMMx7B0_ADDRESS, + GMMx7B0_SMU_VOLTAGE_EN_MASK, + 0x1 << GMMx7B0_SMU_VOLTAGE_EN_OFFSET + ), + // Enable thermal controller + GNB_ENTRY_RMW ( + D0F0xBC_x1F460_TYPE, + D0F0xBC_x1F460_ADDRESS, + D0F0xBC_x1F460_ThermalCntl_MASK, + 30 << D0F0xBC_x1F460_ThermalCntl_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F388_TYPE, + D0F0xBC_x1F388_ADDRESS, + D0F0xBC_x1F388_CsrAddr_MASK | D0F0xBC_x1F388_TcenId_MASK, + (0x9 << D0F0xBC_x1F388_CsrAddr_OFFSET) | (0xE << D0F0xBC_x1F388_TcenId_OFFSET) + ), + GNB_ENTRY_WR ( + SMU_MSG_TYPE, + SMC_MSG_CONFIG_THERMAL_CNTL, + 0 + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F400_TYPE, + D0F0xBC_x1F400_ADDRESS, + D0F0xBC_x1F400_PstateMax_OFFSET, + D0F0xBC_x1F400_PstateMax_WIDTH, + TYPE_D18F3 , + 0xdc , + 8 , + 3 + ), + // Configure VPC + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_BAPM, + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_EnableVpcAccumulators_MASK, + (1 << D0F0xBC_x1F428_EnableVpcAccumulators_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_PstateAllCpusIdle_MASK | D0F0xBC_x1F428_NbPstateAllCpusIdle_MASK, + (1 << D0F0xBC_x1F428_NbPstateAllCpusIdle_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F46C_TYPE, + D0F0xBC_x1F46C_ADDRESS, + D0F0xBC_x1F46C_VpcPeriod_MASK, + (0x1B58 << D0F0xBC_x1F46C_VpcPeriod_OFFSET) + ), + + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_BAPM, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_VPC_ACCUMULATOR, + 0 + ), + // Enable TDC + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_BAPM, + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_EnableTdcLimit_MASK, + (1 << D0F0xBC_x1F428_EnableTdcLimit_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F638_TYPE, + D0F0xBC_x1F638_ADDRESS, + D0F0xBC_x1F638_TdcPeriod_MASK, + (0x1 << D0F0xBC_x1F638_TdcPeriod_OFFSET) + ), + + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_BAPM, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_TDC_LIMIT, + 0 + ), + + // Enable LPMx + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_BAPM, + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_EnableLpmx_MASK, + (1 << D0F0xBC_x1F428_EnableLpmx_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F46C_TYPE, + D0F0xBC_x1F46C_ADDRESS, + D0F0xBC_x1F46C_LpmxPeriod_MASK, + (1 << D0F0xBC_x1F46C_LpmxPeriod_OFFSET) + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_BAPM, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_LPMx, + 0 + ), + // Enable BAPM + GNB_ENTRY_RMW ( + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_BapmCoeffOverride_MASK, + (0x1 << D0F0xBC_x1F428_BapmCoeffOverride_OFFSET) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_BAPM, + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_EnableBapm_MASK, + (1 << D0F0xBC_x1F428_EnableBapm_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F46C_TYPE, + D0F0xBC_x1F46C_ADDRESS, + D0F0xBC_x1F46C_BapmPeriod_MASK, + (D0F0xBC_x1F46C_BapmPeriod_Value << D0F0xBC_x1F46C_BapmPeriod_OFFSET) + ), + // Config BAPM + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_BAPM, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_BAPM, + 0 + ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbEnvInitTableTN [] = { +//--------------------------------------------------------------------------- +// ORB Init +//D0F0x98_x07[IocBwOptEn] +//D0F0x98_x07[DropZeroMaskWrEn] +//D0F0x98_x28[ForceCoherentIntr] = 1 +//D0F0x98_x07[UnadjustThrottlingStpclk ] = 1 +//D0F0x98_x07[MSIHTIntConversionEn] = 0 +//D0F0x98_x07[IommuBwOptEn] = 1 +//D0F0x98_x07[IommuIsocPassPWMode] = 1 +//D0F0x98_x08[NpWrrLenC] = 1 +//D0F0x98_x28[ForceCoherentIntr] = 1 +//D0F0x98_x2C[NBOutbWakeMask] = 1 +//D0F0x98_x2C[OrbRxIdlesMask] = 1 + + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_UnadjustThrottlingStpclk_MASK | D0F0x98_x07_MSIHTIntConversionEn_MASK | + D0F0x98_x07_IommuBwOptEn_MASK | D0F0x98_x07_IommuIsocPassPWMode_MASK | + D0F0x98_x07_IocBwOptEn_MASK | D0F0x98_x07_DropZeroMaskWrEn_MASK, + (0x1 << D0F0x98_x07_UnadjustThrottlingStpclk_OFFSET) | (0x0 << D0F0x98_x07_MSIHTIntConversionEn_OFFSET) | + (0x1 << D0F0x98_x07_IommuBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_IommuIsocPassPWMode_OFFSET) | + (0x1 << D0F0x98_x07_IocBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x98_x08_TYPE, + D0F0x98_x08_ADDRESS, + D0F0x98_x08_NpWrrLenC_MASK, + 0x1 << D0F0x98_x08_NpWrrLenC_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x28_TYPE, + D0F0x98_x28_ADDRESS, + D0F0x98_x28_ForceCoherentIntr_MASK, + 0x1 << D0F0x98_x28_ForceCoherentIntr_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x2C_TYPE, + D0F0x98_x2C_ADDRESS, + D0F0x98_x2C_NBOutbWakeMask_MASK | D0F0x98_x2C_OrbRxIdlesMask_MASK, + (0x1 << D0F0x98_x2C_NBOutbWakeMask_OFFSET) | (0x1 << D0F0x98_x2C_OrbRxIdlesMask_OFFSET) + ), +//--------------------------------------------------------------------------- +//IOMMU L2 Initialization + GNB_ENTRY_RMW ( + D0F2xF4_x10_TYPE, + D0F2xF4_x10_ADDRESS, + D0F2xF4_x10_DTCInvalidationSel_MASK, + 0x2 << D0F2xF4_x10_DTCInvalidationSel_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x11_TYPE, + D0F2xF4_x11_ADDRESS, + D0F2xF4_x11_DtcAddressMask_MASK | D0F2xF4_x11_DtcAltHashEn_MASK, + (0x0 << D0F2xF4_x11_DtcAddressMask_OFFSET) | (0x1 << D0F2xF4_x11_DtcAltHashEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x14_TYPE, + D0F2xF4_x14_ADDRESS, + D0F2xF4_x14_ITCInvalidationSel_MASK, + 0x2 << D0F2xF4_x14_ITCInvalidationSel_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x15_TYPE, + D0F2xF4_x15_ADDRESS, + D0F2xF4_x15_ITCAddressMask_MASK | D0F2xF4_x15_ItcAltHashEn_MASK, + (0x0 << D0F2xF4_x15_ITCAddressMask_OFFSET) | (1 << D0F2xF4_x15_ItcAltHashEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x18_TYPE, + D0F2xF4_x18_ADDRESS, + D0F2xF4_x18_PTCAInvalidationSel_MASK, + 0x2 << D0F2xF4_x18_PTCAInvalidationSel_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x19_TYPE, + D0F2xF4_x19_ADDRESS, + D0F2xF4_x19_PTCAAddressMask_MASK | D0F2xF4_x19_PtcAltHashEn_MASK, + (0x0 << D0F2xF4_x19_PTCAAddressMask_OFFSET) | (1 << D0F2xF4_x19_PtcAltHashEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x30_TYPE, + D0F2xF4_x30_ADDRESS, + D0F2xF4_x30_ERRRuleLock1_MASK, + 0x1 << D0F2xF4_x30_ERRRuleLock1_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x34_TYPE, + D0F2xF4_x34_ADDRESS, + D0F2xF4_x34_L2aregHostPgsize_MASK | D0F2xF4_x34_L2aregGstPgsize_MASK, + (0x2 << D0F2xF4_x34_L2aregHostPgsize_OFFSET) | (0x2 << D0F2xF4_x34_L2aregGstPgsize_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x47_TYPE, + D0F2xF4_x47_ADDRESS, + D0F2xF4_x47_TwAtomicFilterEn_MASK | D0F2xF4_x47_TwNwEn_MASK, + (0x1 << D0F2xF4_x47_TwAtomicFilterEn_OFFSET) | (1 << D0F2xF4_x47_TwNwEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x4C_TYPE, + D0F2xF4_x4C_ADDRESS, + D0F2xF4_x4C_GstPartialPtcCntrl_MASK, + 0x3 << D0F2xF4_x4C_GstPartialPtcCntrl_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x50_TYPE, + D0F2xF4_x50_ADDRESS, + D0F2xF4_x50_PDCInvalidationSel_MASK, + 0x2 << D0F2xF4_x50_PDCInvalidationSel_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x51_TYPE, + D0F2xF4_x51_ADDRESS, + D0F2xF4_x51_PDCAddressMask_MASK | D0F2xF4_x51_PdcAltHashEn_MASK, + (0x0 << D0F2xF4_x51_PDCAddressMask_OFFSET) | (1 << D0F2xF4_x51_PdcAltHashEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x56_TYPE, + D0F2xF4_x56_ADDRESS, + D0F2xF4_x56_CPFlushOnInv_MASK | D0F2xF4_x56_CPFlushOnWait_MASK, + (0x0 << D0F2xF4_x56_CPFlushOnInv_OFFSET) | (1 << D0F2xF4_x56_CPFlushOnWait_OFFSET) + ), + + GNB_ENTRY_RMW ( + D0F2xF4_x80_TYPE, + D0F2xF4_x80_ADDRESS, + D0F2xF4_x80_ERRRuleLock0_MASK, + 0x1 << D0F2xF4_x80_ERRRuleLock0_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x90_TYPE, + D0F2xF4_x90_ADDRESS, + D0F2xF4_x90_CKGateL2BMiscDisable_MASK | D0F2xF4_x90_CKGateL2BDynamicDisable_MASK | D0F2xF4_x90_CKGateL2BRegsDisable_MASK | D0F2xF4_x90_CKGateL2BCacheDisable_MASK, + (0x1 << D0F2xF4_x90_CKGateL2BMiscDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BDynamicDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BRegsDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BCacheDisable_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x92_TYPE, + D0F2xF4_x92_ADDRESS, + D0F2xF4_x92_PprIntcoallesceEn_MASK | D0F2xF4_x92_PprIntreqdelay_MASK | D0F2xF4_x92_PprInttimedelay_MASK, + (0x0 << D0F2xF4_x92_PprIntcoallesceEn_OFFSET) | (0x20 << D0F2xF4_x92_PprIntreqdelay_OFFSET) | (0x15 << D0F2xF4_x92_PprInttimedelay_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x94_TYPE, + D0F2xF4_x94_ADDRESS, + D0F2xF4_x94_L2bregHostPgsize_MASK | D0F2xF4_x94_L2bregGstPgsize_MASK, + (0x2 << D0F2xF4_x94_L2bregHostPgsize_OFFSET) | (0x2ull << D0F2xF4_x94_L2bregGstPgsize_OFFSET) + ), +//IOMMU L1 Initialization + GNB_ENTRY_RMW ( + D0F2xFC_x0C_L1_TYPE, + D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GFX), + D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK, + 0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xFC_x32_L1_TYPE, + D0F2xFC_x32_L1_ADDRESS (L1_SEL_GFX), + D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK, + (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1_SEL_GFX), + D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK | + D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK, + (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) | + (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x0C_L1_TYPE, + D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GPPSB), + D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK, + 0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xFC_x32_L1_TYPE, + D0F2xFC_x32_L1_ADDRESS (L1_SEL_GPPSB), + D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK, + (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1_SEL_GPPSB), + D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK | + D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK, + (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) | + (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x0C_L1_TYPE, + D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GBIF), + D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK, + 0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xFC_x32_L1_TYPE, + D0F2xFC_x32_L1_ADDRESS (L1_SEL_GBIF), + D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK, + (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1_SEL_GBIF), + D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK | + D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK, + (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) | + (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x0C_L1_TYPE, + D0F2xFC_x0C_L1_ADDRESS (L1_SEL_INTGEN), + D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK, + 0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xFC_x32_L1_TYPE, + D0F2xFC_x32_L1_ADDRESS (L1_SEL_INTGEN), + D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK, + (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1_SEL_INTGEN), + D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK | + D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK, + (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) | + (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET) + ), +//--------------------------------------------------------------------------- +// IOMMU Initialization + GNB_ENTRY_RMW ( + D0F2x70_TYPE, + D0F2x70_ADDRESS, + D0F2x70_PcSupW_MASK, + (0x0 << D0F2x70_PcSupW_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x64_x0D_TYPE, + D0F0x64_x0D_ADDRESS, + D0F0x64_x0D_PciDev0Fn2RegEn_MASK, + (0x1 << D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET) + ), +// IOMMU L2 clock gating + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING, + D0F2xF4_x33_TYPE, + D0F2xF4_x33_ADDRESS, + D0F2xF4_x33_CKGateL2ARegsDisable_MASK | D0F2xF4_x33_CKGateL2ADynamicDisable_MASK | D0F2xF4_x33_CKGateL2ACacheDisable_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING, + D0F2xF4_x90_TYPE, + D0F2xF4_x90_ADDRESS, + D0F2xF4_x90_CKGateL2BRegsDisable_MASK | D0F2xF4_x90_CKGateL2BDynamicDisable_MASK | D0F2xF4_x90_CKGateL2BMiscDisable_MASK | D0F2xF4_x90_CKGateL2BCacheDisable_MASK, + 0x0 + ), +// IOMMU L1 clock gating + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING, + D0F2xFC_x33_L1_TYPE, + D0F2xFC_x33_L1_ADDRESS (L1_SEL_GFX), + D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK | + D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK | + D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK | + D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK, + (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING, + D0F2xFC_x33_L1_TYPE, + D0F2xFC_x33_L1_ADDRESS (L1_SEL_GPPSB), + D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK | + D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK | + D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK | + D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK, + (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING, + D0F2xFC_x33_L1_TYPE, + D0F2xFC_x33_L1_ADDRESS (L1_SEL_GBIF), + D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK | + D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK | + D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK | + D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK, + (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING, + D0F2xFC_x33_L1_TYPE, + D0F2xFC_x33_L1_ADDRESS (L1_SEL_INTGEN), + D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK | + D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK | + D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK | + D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK, + (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET) + ), +//--------------------------------------------------------------------------- +// Configure IOMMU Power Island + GNB_ENTRY_WR ( + D0F0xBC_xE030001C_TYPE, + D0F0xBC_xE030001C_ADDRESS, + (10 << 0 ) | (50 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300018_TYPE, + D0F0xBC_xE0300018_ADDRESS, + (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300018_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE030001C_TYPE, + D0F0xBC_xE030001C_ADDRESS, + (50 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300018_TYPE, + D0F0xBC_xE0300018_ADDRESS, + (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300018_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE030001C_TYPE, + D0F0xBC_xE030001C_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300018_TYPE, + D0F0xBC_xE0300018_ADDRESS, + (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) | + (1 << D0F0xBC_xE0300018_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_RMW ( + D0F0xBC_xE0300320_TYPE, + D0F0xBC_xE0300320_ADDRESS, + D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK, + 0x0 + ), +// Hide IOMMU function if disabled + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_DISABLED, + D0F0x64_x0D_TYPE, + D0F0x64_x0D_ADDRESS, + D0F0x64_x0D_PciDev0Fn2RegEn_MASK, + 0x0 + ), + //NB P-state Configuration for Runtime + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_NBDPM, + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_EnableNbDpm_MASK, + (1 << D0F0xBC_x1F428_EnableNbDpm_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F638_TYPE, + D0F0xBC_x1F638_ADDRESS, + D0F0xBC_x1F638_NbdpmPeriod_MASK | D0F0xBC_x1F638_PginterlockPeriod_MASK, + (1 << D0F0xBC_x1F638_NbdpmPeriod_OFFSET) | (1 << D0F0xBC_x1F638_PginterlockPeriod_OFFSET) + ), + + GNB_ENTRY_COPY ( + D0F0xBC_x1F5F8_TYPE, + D0F0xBC_x1F5F8_ADDRESS, + D0F0xBC_x1F5F8_Dpm0PgNbPsLo_OFFSET, D0F0xBC_x1F5F8_Dpm0PgNbPsLo_WIDTH, + D0F0xBC_xE010703C_TYPE, + D0F0xBC_xE010703C_ADDRESS, + D0F0xBC_xE010703C_NbPstateLo_OFFSET, D0F0xBC_xE010703C_NbPstateLo_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F5F8_TYPE, + D0F0xBC_x1F5F8_ADDRESS, + D0F0xBC_x1F5F8_Dpm0PgNbPsHi_OFFSET, D0F0xBC_x1F5F8_Dpm0PgNbPsHi_WIDTH, + D0F0xBC_xE010703C_TYPE, + D0F0xBC_xE010703C_ADDRESS, + D0F0xBC_xE010703C_NbPstateHi_OFFSET, D0F0xBC_xE010703C_NbPstateHi_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F5F8_TYPE, + D0F0xBC_x1F5F8_ADDRESS, + D0F0xBC_x1F5F8_DpmXNbPsLo_OFFSET, D0F0xBC_x1F5F8_DpmXNbPsLo_WIDTH, + D0F0xBC_xE010703C_TYPE, + D0F0xBC_xE010703C_ADDRESS, + D0F0xBC_xE010703C_NbPstateLo_OFFSET, D0F0xBC_xE010703C_NbPstateLo_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F5F8_TYPE, + D0F0xBC_x1F5F8_ADDRESS, + D0F0xBC_x1F5F8_DpmXNbPsHi_OFFSET, D0F0xBC_x1F5F8_DpmXNbPsHi_WIDTH, + D0F0xBC_xE010703C_TYPE, + D0F0xBC_xE010703C_ADDRESS, + D0F0xBC_xE010703C_NbPstateHi_OFFSET, D0F0xBC_xE010703C_NbPstateHi_WIDTH + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F5F8_TYPE, + D0F0xBC_x1F5F8_ADDRESS, + D0F0xBC_x1F5F8_Hysteresis_MASK | D0F0xBC_x1F5F8_SkipDPM0_MASK | + D0F0xBC_x1F5F8_SkipPG_MASK | D0F0xBC_x1F5F8_EnableNbPsi1_MASK | D0F0xBC_x1F5F8_EnableDpmPstatePoll_MASK, + (10 << D0F0xBC_x1F5F8_Hysteresis_OFFSET) | (1 << D0F0xBC_x1F5F8_SkipDPM0_OFFSET) | + (1 << D0F0xBC_x1F5F8_EnableNbPsi1_OFFSET) | (1 << D0F0xBC_x1F5F8_EnableDpmPstatePoll_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F6E4_TYPE, + D0F0xBC_x1F6E4_ADDRESS, + D0F0xBC_x1F6E4_DdrVoltFloor_MASK | D0F0xBC_x1F6E4_BapmDdrVoltFloor_MASK, + (0xFF << D0F0xBC_x1F6E4_DdrVoltFloor_OFFSET) | (0xFF << D0F0xBC_x1F6E4_BapmDdrVoltFloor_OFFSET) + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_NBDPM, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_NBDPM, + 0 + ), + +//--------------------------------------------------------------------------- +// Configure PCIe Power Island + GNB_ENTRY_WR ( + D0F0xBC_xE0300010_TYPE, + D0F0xBC_xE0300010_ADDRESS, + (10 << 0 ) | (50 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030000C_TYPE, + D0F0xBC_xE030000C_ADDRESS, + (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) | + (2 << D0F0xBC_xE030000C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300010_TYPE, + D0F0xBC_xE0300010_ADDRESS, + (50 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030000C_TYPE, + D0F0xBC_xE030000C_ADDRESS, + (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) | + (3 << D0F0xBC_xE030000C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300010_TYPE, + D0F0xBC_xE0300010_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030000C_TYPE, + D0F0xBC_xE030000C_ADDRESS, + (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) | (1 << D0F0xBC_xE030000C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LOADLINE_ENABLE, + TYPE_D0F0xBC , + 0x1f428 , + 0x40 , + (1 << 6 ) + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_LOADLINE_ENABLE, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_LOADLINE, + 0 + ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbMidInitTableTN [] = { +//--------------------------------------------------------------------------- +// Enable LCLK Deep Sleep + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LCLK_DEEP_SLEEP, + TYPE_GMM, + GMMx7A0_ADDRESS, + GMMx7A0_DivId_MASK | GMMx7A0_RampDis_MASK | GMMx7A0_Hysteresis_MASK | GMMx7A0_SclkRunningMask_MASK | GMMx7A0_SmuBusyMask_MASK | GMMx7A0_PcieLclkIdle1Mask_MASK | GMMx7A0_PcieLclkIdle2Mask_MASK | GMMx7A0_L1imugfxIdleMask_MASK | GMMx7A0_L1imugppsbIdleMask_MASK | GMMx7A0_L1imubifIdleMask_MASK | GMMx7A0_L1imuintgenIdleMask_MASK | GMMx7A0_L2imuIdleMask_MASK | GMMx7A0_OrbIdleMask_MASK | GMMx7A0_OnInbWakeMask_MASK | GMMx7A0_OnInbWakeAckMask_MASK | GMMx7A0_OnOutbWakeMask_MASK | GMMx7A0_OnOutbWakeAckMask_MASK | GMMx7A0_DmaactiveMask_MASK, + (0x5 << GMMx7A0_DivId_OFFSET) | (0x0 << GMMx7A0_RampDis_OFFSET) | (0xF << GMMx7A0_Hysteresis_OFFSET) | (0x1 << GMMx7A0_SclkRunningMask_OFFSET) | (0x1 << GMMx7A0_SmuBusyMask_OFFSET) | (0x1 << GMMx7A0_PcieLclkIdle1Mask_OFFSET) | (0x1 << GMMx7A0_PcieLclkIdle2Mask_OFFSET) | (0x1 << GMMx7A0_L1imugfxIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imugppsbIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imubifIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imuintgenIdleMask_OFFSET) | (0x1 << GMMx7A0_L2imuIdleMask_OFFSET) | (0x1 << GMMx7A0_OrbIdleMask_OFFSET) | (0x1 << GMMx7A0_OnInbWakeMask_OFFSET) | (0x1 << GMMx7A0_OnInbWakeAckMask_OFFSET) | (0x1 << GMMx7A0_OnOutbWakeMask_OFFSET) | (0x1 << GMMx7A0_OnOutbWakeAckMask_OFFSET) | (0x1 << GMMx7A0_DmaactiveMask_OFFSET) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + TYPE_GMM, + GMMx7A0_ADDRESS, + GMMx7A0_SclkRunningMask_MASK, + 0x0 + ), +// Reset : 0, Enable : 1 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LCLK_DEEP_SLEEP, + TYPE_GMM, + GMMx7A0_ADDRESS, + GMMx7A0_EnableDs_MASK, + (0x1 << GMMx7A0_EnableDs_OFFSET) + ), +//--------------------------------------------------------------------------- +// LCLK DPM init + GNB_ENTRY_RMW ( + D0F0xBC_xE0000120_TYPE, + D0F0xBC_xE0000120_ADDRESS, + D0F0xBC_xE0000120_BusyCntSel_MASK | D0F0xBC_xE0000120_ActivityCntRst_MASK | + D0F0xBC_xE0000120_PeriodCntRst_MASK | D0F0xBC_xE0000120_EnOrbUsCnt_MASK | + D0F0xBC_xE0000120_EnOrbDsCnt_MASK, + (0x3 << D0F0xBC_xE0000120_BusyCntSel_OFFSET) | (0 << D0F0xBC_xE0000120_ActivityCntRst_OFFSET) | + (0x0 << D0F0xBC_xE0000120_PeriodCntRst_OFFSET) | (0x1 << D0F0xBC_xE0000120_EnOrbUsCnt_OFFSET) | + (0x1 << D0F0xBC_xE0000120_EnOrbDsCnt_OFFSET) + ), + //Programming Lclk Thermal Throttling Threshold in GnbLclkDpmInitTN() + GNB_ENTRY_RMW ( + D0F0xBC_x1F308_TYPE, + D0F0xBC_x1F308_ADDRESS, + D0F0xBC_x1F308_LclkThermalThrottlingEn_MASK, + (0x1 << D0F0xBC_x1F308_LclkThermalThrottlingEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F460_TYPE, + D0F0xBC_x1F460_ADDRESS, + D0F0xBC_x1F460_LclkDpm_MASK, + (0x1 << D0F0xBC_x1F460_LclkDpm_OFFSET) + ), +//--------------------------------------------------------------------------- +// ORB clock gating + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_ORB_CLK_GATING, + D0F0x98_x49_TYPE, + D0F0x98_x49_ADDRESS, + D0F0x98_x49_SoftOverrideClk6_MASK | D0F0x98_x49_SoftOverrideClk5_MASK | D0F0x98_x49_SoftOverrideClk4_MASK | D0F0x98_x49_SoftOverrideClk3_MASK | D0F0x98_x49_SoftOverrideClk2_MASK | D0F0x98_x49_SoftOverrideClk1_MASK | D0F0x98_x49_SoftOverrideClk0_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_ORB_CLK_GATING, + D0F0x98_x4A_TYPE, + D0F0x98_x4A_ADDRESS, + D0F0x98_x4A_SoftOverrideClk6_MASK | D0F0x98_x4A_SoftOverrideClk5_MASK | D0F0x98_x4A_SoftOverrideClk4_MASK | D0F0x98_x4A_SoftOverrideClk3_MASK | D0F0x98_x4A_SoftOverrideClk2_MASK | D0F0x98_x4A_SoftOverrideClk1_MASK | D0F0x98_x4A_SoftOverrideClk0_MASK, + (1 << D0F0x98_x4A_SoftOverrideClk0_OFFSET) + ), + +//--------------------------------------------------------------------------- +// IOC clock gating + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING, + D0F0x64_x22_TYPE, + D0F0x64_x22_ADDRESS, + D0F0x64_x22_SoftOverrideClk4_MASK | D0F0x64_x22_SoftOverrideClk3_MASK | D0F0x64_x22_SoftOverrideClk2_MASK | D0F0x64_x22_SoftOverrideClk1_MASK | D0F0x64_x22_SoftOverrideClk0_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING, + D0F0x64_x23_TYPE, + D0F0x64_x23_ADDRESS, + D0F0x64_x23_SoftOverrideClk4_MASK | D0F0x64_x23_SoftOverrideClk3_MASK | D0F0x64_x23_SoftOverrideClk2_MASK | D0F0x64_x23_SoftOverrideClk1_MASK | D0F0x64_x23_SoftOverrideClk0_MASK, + 0x0 + ), + +//--------------------------------------------------------------------------- +// Shutdown IOMMU if disabled + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_DISABLED, + D0F0xBC_xE0300320_TYPE, + D0F0xBC_xE0300320_ADDRESS, + D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK, + 1 << D0F0xBC_xE0300320_IommuPgfsmClockEn_OFFSET + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IOMMU_DISABLED, + D0F0xBC_xE0300018_TYPE, + D0F0xBC_xE0300018_ADDRESS, + (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300018_P1Select_OFFSET) | (1 << D0F0xBC_xE0300018_P2Select_OFFSET) + ), + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IOMMU_DISABLED, + D0F0xBC_xE0300208_TYPE, + 0xe0300208 , + D0F0xBC_xE0300208_P1IsoN_MASK, + 0 << D0F0xBC_xE0300208_P1IsoN_OFFSET + ), + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IOMMU_DISABLED, + TYPE_D0F0xBC , + 0xe0300208 , + 0x2000 , + 1 << 13 + ), + GNB_ENTRY_STALL (10), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_DISABLED, + D0F0xBC_xE0300320_TYPE, + D0F0xBC_xE0300320_ADDRESS, + D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK, + 0x0 + ), +//--------------------------------------------------------------------------- + GNB_ENTRY_TERMINATE +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h new file mode 100644 index 0000000000..f3bf14af5a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h @@ -0,0 +1,242 @@ +/** + * @file + * + * ALIB SSDT table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63659 $ @e \$Date: 2012-01-03 00:42:47 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEALIBSSDTTNFM2_H_ +#define _PCIEALIBSSDTTNFM2_H_ + +UINT8 AlibSsdtTNFM2[] = { + 0x53, 0x53, 0x44, 0x54, 0x1F, 0x05, 0x00, 0x00, + 0x02, 0xE2, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, + 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, + 0x00, 0x00, 0x00, 0x04, 0x10, 0x4A, 0x4F, 0x5C, + 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, 0x30, + 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30, 0x31, + 0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41, 0x44, + 0x30, 0x31, 0x41, 0x30, 0x31, 0x33, 0x14, 0x31, + 0x41, 0x30, 0x30, 0x36, 0x0A, 0x72, 0x41, 0x30, + 0x31, 0x33, 0x79, 0x68, 0x0A, 0x0C, 0x00, 0x60, + 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41, 0x30, + 0x31, 0x34, 0x00, 0x60, 0x0A, 0x04, 0x5B, 0x81, + 0x0B, 0x41, 0x30, 0x31, 0x34, 0x03, 0x41, 0x30, + 0x31, 0x35, 0x20, 0xA4, 0x41, 0x30, 0x31, 0x35, + 0x14, 0x32, 0x41, 0x30, 0x30, 0x37, 0x0B, 0x72, + 0x41, 0x30, 0x31, 0x33, 0x79, 0x68, 0x0A, 0x0C, + 0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, + 0x41, 0x30, 0x31, 0x34, 0x00, 0x60, 0x0A, 0x04, + 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x31, 0x34, 0x03, + 0x41, 0x30, 0x31, 0x35, 0x20, 0x70, 0x6A, 0x41, + 0x30, 0x31, 0x35, 0x14, 0x1C, 0x41, 0x30, 0x31, + 0x36, 0x0C, 0x70, 0x41, 0x30, 0x30, 0x36, 0x68, + 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, + 0x60, 0x41, 0x30, 0x30, 0x37, 0x68, 0x69, 0x60, + 0x5B, 0x01, 0x41, 0x30, 0x31, 0x37, 0x00, 0x14, + 0x32, 0x41, 0x30, 0x31, 0x38, 0x02, 0x5B, 0x23, + 0x41, 0x30, 0x31, 0x37, 0xFF, 0xFF, 0x70, 0x79, + 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, + 0x60, 0x41, 0x30, 0x30, 0x37, 0x60, 0x0A, 0xE0, + 0x69, 0x70, 0x41, 0x30, 0x30, 0x36, 0x60, 0x0A, + 0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x31, 0x37, + 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x31, 0x39, + 0x03, 0x5B, 0x23, 0x41, 0x30, 0x31, 0x37, 0xFF, + 0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, + 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x30, 0x37, + 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x30, 0x37, + 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, 0x30, + 0x31, 0x37, 0x14, 0x1C, 0x41, 0x30, 0x32, 0x30, + 0x04, 0x70, 0x41, 0x30, 0x31, 0x38, 0x68, 0x69, + 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, 0x60, + 0x41, 0x30, 0x31, 0x39, 0x68, 0x69, 0x60, 0x5B, + 0x01, 0x41, 0x30, 0x32, 0x31, 0x00, 0x14, 0x29, + 0x41, 0x30, 0x30, 0x38, 0x03, 0x5B, 0x23, 0x41, + 0x30, 0x32, 0x31, 0xFF, 0xFF, 0x41, 0x30, 0x30, + 0x37, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, 0x30, + 0x36, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, 0x60, + 0x5B, 0x27, 0x41, 0x30, 0x32, 0x31, 0xA4, 0x60, + 0x14, 0x26, 0x41, 0x30, 0x31, 0x32, 0x04, 0x5B, + 0x23, 0x41, 0x30, 0x32, 0x31, 0xFF, 0xFF, 0x41, + 0x30, 0x30, 0x37, 0x68, 0x69, 0x6A, 0x41, 0x30, + 0x30, 0x37, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, + 0x6B, 0x5B, 0x27, 0x41, 0x30, 0x32, 0x31, 0x14, + 0x1E, 0x41, 0x30, 0x32, 0x32, 0x05, 0x70, 0x41, + 0x30, 0x30, 0x38, 0x68, 0x69, 0x6A, 0x60, 0x7D, + 0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41, 0x30, + 0x31, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x14, 0x42, + 0x05, 0x41, 0x30, 0x32, 0x33, 0x02, 0x70, 0x0A, + 0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30, 0x30, + 0x36, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, 0xFF, + 0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01, 0x60, + 0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70, 0x7B, + 0x41, 0x30, 0x30, 0x36, 0x68, 0x61, 0x0A, 0xFF, + 0x00, 0x61, 0xA0, 0x06, 0x93, 0x61, 0x0A, 0x00, + 0xA5, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, 0x30, + 0x36, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, 0x70, + 0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61, 0xA4, + 0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x32, 0x34, + 0x0A, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, 0x01, + 0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81, 0x10, + 0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D, 0x52, + 0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08, 0x5B, + 0x86, 0x12, 0x50, 0x4D, 0x52, 0x49, 0x50, 0x4D, + 0x52, 0x44, 0x01, 0x00, 0x40, 0x70, 0x41, 0x42, + 0x41, 0x52, 0x20, 0x5B, 0x80, 0x41, 0x43, 0x46, + 0x47, 0x01, 0x41, 0x42, 0x41, 0x52, 0x0A, 0x08, + 0x5B, 0x81, 0x10, 0x41, 0x43, 0x46, 0x47, 0x03, + 0x41, 0x42, 0x49, 0x58, 0x20, 0x41, 0x42, 0x44, + 0x41, 0x20, 0x70, 0x0A, 0x00, 0x60, 0xA0, 0x17, + 0x93, 0x69, 0x0A, 0x00, 0x70, 0x0C, 0x68, 0x00, + 0x00, 0x80, 0x41, 0x42, 0x49, 0x58, 0x70, 0x41, + 0x42, 0x44, 0x41, 0x60, 0xA4, 0x60, 0xA1, 0x22, + 0x70, 0x0C, 0x68, 0x00, 0x00, 0x80, 0x41, 0x42, + 0x49, 0x58, 0x70, 0x41, 0x42, 0x44, 0x41, 0x60, + 0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF, 0xFF, + 0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42, 0x44, + 0x41, 0x08, 0x41, 0x30, 0x32, 0x35, 0x11, 0x04, + 0x0B, 0x00, 0x01, 0x14, 0x46, 0x08, 0x41, 0x30, + 0x30, 0x39, 0x01, 0xA2, 0x16, 0x92, 0x93, 0x7B, + 0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, 0xB8, + 0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x02, 0x00, + 0x0A, 0x02, 0x70, 0x41, 0x30, 0x30, 0x38, 0x0A, + 0x00, 0x0A, 0xB8, 0x0C, 0x00, 0x30, 0x00, 0xE0, + 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0xFE, + 0xFF, 0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0A, 0x01, + 0x00, 0x00, 0x0A, 0x01, 0x00, 0x60, 0x7D, 0x60, + 0x79, 0x68, 0x0A, 0x01, 0x00, 0x60, 0x41, 0x30, + 0x31, 0x32, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00, + 0x30, 0x00, 0xE0, 0x60, 0xA2, 0x16, 0x92, 0x93, + 0x7B, 0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, + 0xB8, 0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x01, + 0x00, 0x0A, 0x01, 0xA2, 0x16, 0x92, 0x93, 0x7B, + 0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, 0xB8, + 0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x02, 0x00, + 0x0A, 0x02, 0x08, 0x41, 0x30, 0x30, 0x32, 0x0A, + 0x00, 0x08, 0x41, 0x30, 0x30, 0x33, 0x0A, 0x00, + 0x08, 0x41, 0x30, 0x30, 0x34, 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b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h new file mode 100644 index 0000000000..e9776d0be3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h @@ -0,0 +1,1065 @@ +/** + * @file + * + * ALIB SSDT table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 65976 $ @e \$Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEALIBSSDTTNFS1_H_ +#define _PCIEALIBSSDTTNFS1_H_ + +UINT8 AlibSsdtTNFS1[] = { + 0x53, 0x53, 0x44, 0x54, 0xD4, 0x1E, 0x00, 0x00, + 0x02, 0x5C, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, + 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, + 0x00, 0x00, 0x00, 0x04, 0x10, 0x8F, 0xEA, 0x01, + 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, + 0x30, 0x31, 0x0A, 0x06, 0x08, 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+#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c new file mode 100644 index 0000000000..862909513e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c @@ -0,0 +1,119 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. 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BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "PcieAlibSsdtTNFM2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFM2_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID * +PcieAlibGetBaseTableTNFM2 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Get base SSDT table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @retval pointer to SSTD table + */ +VOID * +PcieAlibGetBaseTableTNFM2 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return &AlibSsdtTNFM2[0]; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl new file mode 100644 index 0000000000..49bae5f302 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl @@ -0,0 +1,196 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63659 $ @e \$Date: 2012-01-03 00:42:47 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +DefinitionBlock ( + "PcieAlibSsdtTN.aml", + "SSDT", + 2, + "AMD", + "ALIB", + 0x1 + ) +{ + Scope(\_SB) { + + Name (varMaxPortIndexNumber, 6) + + include ("PcieAlibMmioData.asl") + include ("PcieAlibPciLib.asl") + include ("PcieAlibDebugLib.asl") + include ("PcieSmuServiceV4.asl") + + + Name (varBapmControl, 0) + Name (varCstateIntControlState, 0) + Name (varIsStateInitialized, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * APM/PDM stub + * + * Arg0 - AC/DC state + * + */ + Method (procApmPdmActivate, 1, NotSerialized) { + Store (Or(ShiftLeft (0x18, 3), 4), Local2) + if (LEqual (varIsStateInitialized, 0)) { + Store (procPciDwordRead (Local2, 0x124), varCstateIntControlState) + Store (1, varIsStateInitialized) + } + + Store (procPciDwordRead (Local2, 0x124), Local3) + if (LEqual (Arg0,DEF_PSPP_STATE_AC)) { + // Disable PC6 on AC + Or (Local3, And (varCstateIntControlState, 0x00400000), Local3) + } else { + // Enable PC6 on DC + And (Local3, 0xFFBFFFFF, Local3) + } + procPciDwordWrite (Local2, 0x124, Local3) + + if (LEqual (varBapmControl, 0)) { + // If GFX present driver manage BAPM if not ALIB manage BAPM + if (LEqual (procPciDwordRead (0x08, 0x00), 0xffffffff)) { + And (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), 0x2, Local1); + // check if BAPM was enable during BIOS post + if (LEqual (Local1, 0x2)) { + Store (1, varBapmControl) + } + } + } + if (LEqual (varBapmControl,1)) { + if (LEqual (Arg0,DEF_PSPP_STATE_AC)) { + // Enable BAPM on AC + Store (32, Local0) + } else { + // Disable BAPM on DC + Store (33, Local0) + } + procNbSmuServiceRequest (Local0); + } + } + + Name (varRestoreNbps, 0) + Name (varRestoreNbDpmState, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * _WAK + * + * + * + */ + Method (AWAK, 1) { + if (LEqual (Arg0, 3)) { + // Clear D18F5x170 [SwNbPstateLoDis] only if it was 0 in APTS + if (LEqual (varRestoreNbps, 1)) { + Store (procPciDwordRead (0xC5, 0x170), Local0) + procPciDwordWrite (0xC5, 0x170, And (Local0, Not (ShiftLeft (1, 14)))) + Store (0, varRestoreNbps); + } + if (LEqual (varRestoreNbDpmState, 1)) { + Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0) + procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, Or (Local0, ShiftLeft (1, 5))) + procNbSmuServiceRequest (22); + Store (0, varRestoreNbDpmState) + } + } + } + /*----------------------------------------------------------------------------------------*/ + /** + * _PTS + * + * + * + */ + Method (APTS, 1) { + if (LEqual (Arg0, 3)) { + procApmPdmActivate (DEF_PSPP_STATE_DC); + // Disable NBDPM + Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0) + if (LNotEqual (And (Local0, ShiftLeft (1, 5)), 0)) { + // NBDPM enabled lets disable it + procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, And (Local0, Not (ShiftLeft (1, 5)))) + procNbSmuServiceRequest (22); + // Indicate needs to restore NBDPM + Store (1, varRestoreNbDpmState); + } + // Save state of D18F5x170 [SwNbPstateLoDis] + Store (procPciDwordRead (0xC5, 0x170), Local0) + if (LEqual (And (Local0, ShiftLeft (1, 14)), 0)) { + // Set D18F5x170 [SwNbPstateLoDis] = 1 + procPciDwordWrite (0xC5, 0x170, Or (Local0, ShiftLeft (1, 14))) + Store (1, varRestoreNbps); + } + } + } + } //End of Scope(\_SB) +} //End of DefinitionBlock + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c new file mode 100644 index 0000000000..baa0f85ac1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c @@ -0,0 +1,119 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "PcieAlibSsdtTNFS1.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFS1_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID * +PcieAlibGetBaseTableTNFS1 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Get base SSDT table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @retval pointer to SSTD table + */ +VOID * +PcieAlibGetBaseTableTNFS1 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return &AlibSsdtTNFS1[0]; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c new file mode 100644 index 0000000000..9c55714b93 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c @@ -0,0 +1,491 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe configuration data definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "PcieComplexDataTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIECOMPLEXDATATN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +TN_COMPLEX_CONFIG ComplexDataTN = { + //Silicon + { + { + DESCRIPTOR_SILICON | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + 0, + 0, + offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon) + }, + 0, + 0 + }, + //Gfx Wrapper + { + { + DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, + offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), + offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper) + }, + + GFX_WRAP_ID, + GFX_NUMBER_OF_PIFs, + GFX_START_PHY_LANE, + GFX_END_PHY_LANE, + GFX_CORE_ID, + GFX_CORE_ID, + 16, + { + 1, //PowerOffUnusedLanesEnabled, + 1, //PowerOffUnusedPllsEnabled + 1, //ClkGating + 1, //LclkGating + 1, //TxclkGatingPllPowerDown + 1, //PllOffInL1 + 0 //AccessEncoding + }, + }, + //Gpp Wrapper + { + { + DESCRIPTOR_PCIE_WRAPPER, + offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), + offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper) + }, + GPP_WRAP_ID, + GPP_NUMBER_OF_PIFs, + GPP_START_PHY_LANE, + GPP_END_PHY_LANE, + GPP_CORE_ID, + GPP_CORE_ID, + 8, + { + 1, //PowerOffUnusedLanesEnabled, + 1, //PowerOffUnusedPllsEnabled + 1, //ClkGating + 1, //LclkGating + 1, //TxclkGatingPllPowerDown + 1, //PllOffInL1 + 0 //AccessEncoding + }, + }, + //DDI Wrapper + { + { + DESCRIPTOR_DDI_WRAPPER, + offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), + offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper), + offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper) + }, + DDI_WRAP_ID, + DDI_NUMBER_OF_PIFs, + DDI_START_PHY_LANE, + DDI_END_PHY_LANE, + 0xf, + 0x0, + 8, + { + 1, //PowerOffUnusedLanesEnabled, + 1, //PowerOffUnusedPllsEnabled + 1, //ClkGating + 1, //LclkGating + 1, //TxclkGatingPllPowerDown + 0, //PllOffInL1 + 0 //AccessEncoding + }, + }, + //DDI2 Wrapper + { + { + DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), + 0, + offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) + }, + DDI2_WRAP_ID, + DDI2_NUMBER_OF_PIFs, + DDI2_START_PHY_LANE, + DDI2_END_PHY_LANE, + 0xf, + 0x0, + 8, + { + 1, //PowerOffUnusedLanesEnabled, + 1, //PowerOffUnusedPllsEnabled + 1, //ClkGating + 1, //LclkGating + 1, //TxclkGatingPllPowerDown + 0, //PllOffInL1 + 0 //AccessEncoding + }, + }, + //Port 2 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, Port2), + 0 + }, + { PciePortEngine, 8, 23}, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 0, + 15, + 2, + 0, + GFX_CORE_ID, + 0, + {0}, + LinkStateResetExit, + 0, + 2, + 1 + }, + }, + }, + //Port 3 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, Port3), + 0 + }, + { PciePortEngine, UNUSED_LANE_ID, UNUSED_LANE_ID }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + UNUSED_LANE_ID, + UNUSED_LANE_ID, + 3, + 0, + GFX_CORE_ID, + 1, + {0}, + LinkStateResetExit, + 1, + 3, + 1 + }, + }, + }, + //DdiB + { + { + DESCRIPTOR_DDI_ENGINE, + offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, DpB), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //DdiC + { + { + DESCRIPTOR_DDI_ENGINE, + offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, DpC), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //DdiD + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST, + offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, DpD), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + + //Port 4 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, Port4), + 0 + }, + { PciePortEngine, 4, 4}, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 4, + 4, + 4, + 0, + GPP_CORE_ID, + 1, + {0}, + LinkStateResetExit, + 2, + 0, + 0 + }, + }, + }, + //Port 5 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, Port5), + 0 + }, + { PciePortEngine, 5, 5}, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 5, + 5, + 5, + 0, + GPP_CORE_ID, + 2, + {0}, + LinkStateResetExit, + 3, + 0, + 0 + }, + }, + }, + //Port 6 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, Port6), + 0 + }, + { PciePortEngine, 6, 6 }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 6, + 6, + 6, + 0, + GPP_CORE_ID, + 3, + {0}, + LinkStateResetExit, + 4, + 0, + 0 + }, + }, + }, + //Port 7 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, Port7), + 0 + }, + { PciePortEngine, 7, 7 }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 7, + 7, + 7, + 0, + GPP_CORE_ID, + 4, + {0}, + LinkStateResetExit, + 5, + 0, + 0 + }, + }, + }, + //Port 8 + { + { + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST, + offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, Port8), + 0 + }, + { PciePortEngine, 0, 3 }, + INIT_STATUS_PCIE_TRAINING_SUCCESS, //Initialization Status + 0xFF, //Scratch + { + { + {PortEnabled, 0, 8, 0, PcieGenMaxSupported, AspmL0sL1, HotplugDisabled, 0x0, {0}}, + 0, + 3, + 8, + 0, + GPP_CORE_ID, + 0, + {MAKE_SBDFO (0, 0, 8, 0, 0)}, + LinkStateTrainingSuccess, + 6, + 0, + 0 + }, + }, + }, + //DpE + { + { + DESCRIPTOR_DDI_ENGINE, + offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper), + offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DpE), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //DpF + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST, + offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper), + offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, DpF), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //DpA + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper), + 0, + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //F12 specific Silicon + { + OscFuses, + {0, 0, 0, 0, 0, 0} + } +}; + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h new file mode 100644 index 0000000000..623636cc06 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h @@ -0,0 +1,160 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIECOMPLEXDATATN_H_ +#define _PCIECOMPLEXDATATN_H_ + +#define SOCKET_ID 0 + +#define MAX_NUM_PHYs 2 +#define MAX_NUM_LANE_PER_PHY 8 + +#define NUMBER_OF_PORTS 8 +#define NUMBER_OF_GPP_PORTS 5 +#define NUMBER_OF_GFX_PORTS 2 +#define NUMBER_OF_GFX_DDIS 3 +#define NUMBER_OF_DDIS 2 +#define NUMBER_OF_DDIS2 1 +#define NUMBER_OF_WRAPPERS 3 +#define NUMBER_OF_SILICONS 1 + +#define GFX_WRAP_ID 1 +#define GFX_NUMBER_OF_PIFs 2 +#define GFX_START_PHY_LANE 8 +#define GFX_END_PHY_LANE 23 +#define GFX_CORE_ID 2 + +#define GFX_CORE_x16 ((16 << 8) | 0) +#define GFX_CORE_x8x8 ((8 << 8) | 8) + +#define GPP_WRAP_ID 0 +#define GPP_NUMBER_OF_PIFs 1 +#define GPP_START_PHY_LANE 0 +#define GPP_END_PHY_LANE 7 +#define GPP_CORE_ID 1 + +#define GPP_CORE_x4x1x1x1x1 ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x1x1 ((2ull << 32) | (1ull << 24) | (1ull << 16) | (0ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x1x1_ST ((2ull << 32) | (0ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x2 ((2ull << 32) | (2ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x2_ST ((2ull << 32) | (0ull << 24) | (2ull << 16) | (0ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x4 ((4ull << 32) | (0ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) + +#define DDI_WRAP_ID 2 +#define DDI_NUMBER_OF_PIFs 1 +#define DDI_START_PHY_LANE 24 +#define DDI_END_PHY_LANE 31 + +#define DDI2_WRAP_ID 3 +#define DDI2_NUMBER_OF_PIFs 1 +#define DDI2_START_PHY_LANE 32 +#define DDI2_END_PHY_LANE 38 + +///Gen2 capability +typedef enum { + OscFuses, ///< Not capable + OscRO, ///< Gen2 with RO + OscLC, ///< Gen2 with LC + OscDefault, ///< Skip initialization of OSC +} OSC_MODE; + +///Family specific silicon configuration +typedef struct { + OSC_MODE OscMode; ///WrapId) { + case GFX_WRAP_ID: + Status = PcieConfigureGfxEnginesLaneAllocationTN (Wrapper, EngineType, ConfigurationId); + break; + case GPP_WRAP_ID: + if (EngineType != PciePortEngine) { + return AGESA_UNSUPPORTED; + } + Status = PcieConfigureGppEnginesLaneAllocationTN (Wrapper, ConfigurationId); + break; + case DDI_WRAP_ID: + if (EngineType != PcieDdiEngine) { + return AGESA_UNSUPPORTED; + } + Status = PcieConfigureDdiEnginesLaneAllocationTN (Wrapper, ConfigurationId); + break; + case DDI2_WRAP_ID: + if (EngineType != PcieDdiEngine) { + return AGESA_UNSUPPORTED; + } + Status = PcieConfigureDdi2EnginesLaneAllocationTN (Wrapper, ConfigurationId); + break; + default: + ASSERT (FALSE); + } + return Status; +} + +CONST UINT8 GfxPortLaneConfigurationTable [][NUMBER_OF_GFX_PORTS * 2] = { +{0, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, +{0, 7, 8, 15} +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure GFX engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + +AGESA_STATUS +STATIC +PcieConfigureGfxPortEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + UINTN CoreLaneIndex; + PCIe_ENGINE_CONFIG *EnginesList; + if (ConfigurationId > ((sizeof (GfxPortLaneConfigurationTable) / (NUMBER_OF_GFX_PORTS * 2)) - 1)) { + return AGESA_ERROR; + } + EnginesList = PcieConfigGetChildEngine (Wrapper); + CoreLaneIndex = 0; + while (EnginesList != NULL) { + if (PcieLibIsPcieEngine (EnginesList)) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->Type.Port.StartCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; + EnginesList->Type.Port.EndCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; + } + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + +CONST UINT8 GfxDdiLaneConfigurationTable [][NUMBER_OF_GFX_DDIS * 2] = { + {0, 7, 8, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, + {4, 7, 8, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, + {0, 7, 8, 11, 12, 15}, + {4, 7, 8, 11, 12, 15} +}; +/*----------------------------------------------------------------------------------------*/ +/** + * Configure GFX engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + +AGESA_STATUS +STATIC +PcieConfigureGfxDdiEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + UINTN LaneIndex; + PCIe_ENGINE_CONFIG *EnginesList; + if (ConfigurationId > ((sizeof (GfxDdiLaneConfigurationTable) / (NUMBER_OF_GFX_DDIS * 2)) - 1)) { + return AGESA_ERROR; + } + LaneIndex = 0; + EnginesList = PcieConfigGetChildEngine (Wrapper); + while (EnginesList != NULL) { + if (PcieLibIsDdiEngine (EnginesList)) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->EngineData.StartLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + EnginesList->EngineData.EndLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + } + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure GFX engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] EngineType Engine Type + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_UNSUPPORTED Configuration not applicable + * @retval AGESA_ERROR Requested configuration not supported + */ + +AGESA_STATUS +STATIC +PcieConfigureGfxEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ) +{ + AGESA_STATUS Status; + + switch (EngineType) { + case PciePortEngine: + Status = PcieConfigureGfxPortEnginesLaneAllocationTN (Wrapper, ConfigurationId); + break; + case PcieDdiEngine: + Status = PcieConfigureGfxDdiEnginesLaneAllocationTN (Wrapper, ConfigurationId); + break; + default: + Status = AGESA_UNSUPPORTED; + } + return Status; +} + + + +CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = { +//4 5 6 7 8 (SB) + {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3}, + {4, 4, 5, 5, 6, 6, 7, 7, 0, 3} +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure GFX engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + + +AGESA_STATUS +STATIC +PcieConfigureGppEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + PCIe_ENGINE_CONFIG *EnginesList; + UINTN CoreLaneIndex; + UINTN PortIdIndex; + if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) { + return AGESA_ERROR; + } + EnginesList = PcieConfigGetChildEngine (Wrapper); + CoreLaneIndex = 0; + PortIdIndex = 0; + while (EnginesList != NULL) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; + EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + + +CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = { + {0, 3, 4, 7}, + {0, 7, UNUSED_LANE_ID, UNUSED_LANE_ID} +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure DDI engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + + +AGESA_STATUS +STATIC +PcieConfigureDdiEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + PCIe_ENGINE_CONFIG *EnginesList; + UINTN LaneIndex; + EnginesList = PcieConfigGetChildEngine (Wrapper); + if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) { + return AGESA_ERROR; + } + LaneIndex = 0; + while (EnginesList != NULL) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + + +CONST UINT8 Ddi2LaneConfigurationTable [][NUMBER_OF_DDIS2 * 2] = { + {0, 6}, + {0, 3} +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure DDI engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + + +AGESA_STATUS +STATIC +PcieConfigureDdi2EnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + PCIe_ENGINE_CONFIG *EnginesList; + UINTN LaneIndex; + EnginesList = PcieConfigGetChildEngine (Wrapper); + if (ConfigurationId > ((sizeof (Ddi2LaneConfigurationTable) / (NUMBER_OF_DDIS2 * 2)) - 1)) { + return AGESA_ERROR; + } + LaneIndex = 0; + while (EnginesList != NULL) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->EngineData.StartLane = Ddi2LaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + EnginesList->EngineData.EndLane = Ddi2LaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get configuration Value for GFX wrapper + * + * + * + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value + * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue + * @retval AGESA_ERROR ConfigurationSignature is incorrect. + */ +STATIC AGESA_STATUS +PcieGetGfxConfigurationValueTN ( + IN UINT64 ConfigurationSignature, + OUT UINT8 *ConfigurationValue + ) +{ + switch (ConfigurationSignature) { + case GFX_CORE_x16: + *ConfigurationValue = 0; + break; + case GFX_CORE_x8x8: + *ConfigurationValue = 0x5; + break; + default: + ASSERT (FALSE); + return AGESA_ERROR; + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get configuration Value for GPP wrapper + * + * + * + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value + * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue + * @retval AGESA_ERROR ConfigurationSignature is incorrect + */ +STATIC AGESA_STATUS +PcieGetGppConfigurationValueTN ( + IN UINT64 ConfigurationSignature, + OUT UINT8 *ConfigurationValue + ) +{ + switch (ConfigurationSignature) { + case GPP_CORE_x4x1x1x1x1: + *ConfigurationValue = 0x4; + break; + case GPP_CORE_x4x2x1x1: + *ConfigurationValue = 0x3; + break; + case GPP_CORE_x4x2x2: + *ConfigurationValue = 0x2; + break; + case GPP_CORE_x4x4: + *ConfigurationValue = 0x1; + break; + default: + ASSERT (FALSE); + return AGESA_ERROR; + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration value + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] CoreId Core ID + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value (for core configuration) + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Core configuration value can not be determined + */ +AGESA_STATUS +PcieGetCoreConfigurationValueTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ) +{ + AGESA_STATUS Status; + + if (Wrapper->WrapId == GFX_WRAP_ID) { + Status = PcieGetGfxConfigurationValueTN (ConfigurationSignature, ConfigurationValue); + } else if (Wrapper->WrapId == GPP_WRAP_ID) { + Status = PcieGetGppConfigurationValueTN (ConfigurationSignature, ConfigurationValue); + } else { + Status = AGESA_ERROR; + } + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if engine can be remapped to Device/function number requested by user + * defined engine descriptor + * + * Function only called if requested device/function does not much native device/function + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieCheckPortPciDeviceMappingTN ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + BOOLEAN Result; + if (PortDescriptor->Port.DeviceNumber >= 2 && PortDescriptor->Port.DeviceNumber <= 7 && PortDescriptor->Port.FunctionNumber == 0 && !PcieConfigIsSbPcieEngine (Engine)) { + Result = TRUE; + } else { + Result = FALSE; + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration string + * + * Debug function for logging configuration + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] ConfigurationValue Configuration value + * @retval Configuration string + */ + +CONST CHAR8* +PcieDebugGetCoreConfigurationStringTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ) +{ + switch (ConfigurationValue) { + case 0: + return "1x16"; + case 5: + return "2x8"; + case 4: + return "1x4, 4x1"; + case 3: + return "1x4, 1x2, 2x1"; + case 2: + return "1x4, 2x2"; + case 1: + return "1x4, 1x4"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get wrapper name + * + * Debug function for logging wrapper name + * + * @param[in] Wrapper Pointer to internal configuration data area + * @retval Wrapper Name string + */ + +CONST CHAR8* +PcieDebugGetWrapperNameStringTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + switch (Wrapper->WrapId) { + case GPP_WRAP_ID: + return "GPPSB"; + case GFX_WRAP_ID: + return "GFX"; + case DDI_WRAP_ID: + return "DDI"; + case DDI2_WRAP_ID: + return "DDI2"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get register address name + * + * Debug function for logging register trace + * + * @param[in] Silicon Silicon config descriptor + * @param[in] AddressFrame Address Frame + * @retval Register address name + */ +CONST CHAR8* +PcieDebugGetHostRegAddressSpaceStringTN ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ) +{ + switch (AddressFrame) { + case 0x130: + return "GPP WRAP"; + case 0x131: + return "GFX WRAP"; + case 0x132: + return "DDI WRAP"; + case 0x133: + return "DDI2 WRAP"; + case 0x110: + return "GPP PIF0"; + case 0x111: + return "GFX PIF0"; + case 0x211: + return "GFX PIF1"; + case 0x112: + return "DDI PIF0"; + case 0x113: + return "DDI2 PIF0"; + case 0x120: + return "GPP PHY0"; + case 0x121: + return "GFX PHY0"; + case 0x221: + return "GFX PHY1"; + case 0x122: + return "DDI PHY0"; + case 0x123: + return "DDI2 PHY0"; + case 0x101: + return "GPP CORE"; + case 0x201: + return "GFX CORE"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if the lane can be muxed by link width requested by user + * defined engine descriptor + * + * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). + * Check Engine StartCoreLane could be aligned by user requested link width x2. + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Lane can be muxed + * @retval FALSE Lane can NOT be muxed + */ + +BOOLEAN +PcieCheckPortPcieLaneCanBeMuxedTN ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT16 DescriptorHiLane; + UINT16 DescriptorLoLane; + UINT16 DescriptorNumberOfLanes; + PCIe_WRAPPER_CONFIG *Wrapper; + UINT16 NormalizedLoPhyLane; + BOOLEAN Result; + + Result = FALSE; + Wrapper = PcieConfigGetParentWrapper (Engine); + DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); + DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; + + NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane; + + if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) { + Result = TRUE; + } else { + if (((PortDescriptor->Port.MiscControls.SbLink == 0x0) && ((Engine->Type.Port.StartCoreLane % 2) == 0)) || (Engine->Type.Port.StartCoreLane == 0)) { + if (NormalizedLoPhyLane == 0) { + Result = TRUE; + } else { + if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) { + Result = TRUE; + } + } + } + } + return Result; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Map engine to specific PCI device address + * + * + * + * @param[in] Engine Pointer to engine configuration + * @retval AGESA_ERROR Fail to map PCI device address + * @retval AGESA_SUCCESS Successfully allocate PCI address + */ + +AGESA_STATUS +PcieMapPortPciAddressTN ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + TN_COMPLEX_CONFIG *ComplexConfig; + PCIe_PLATFORM_CONFIG *Pcie; + UINT8 PortDevMap[6]; + UINT8 FreeDevMap[6]; + UINT8 PortIndex; + UINT8 EnginePortIndex; + UINT8 FreeIndex; + D0F0x64_x20_STRUCT D0F0x64_x20; + D0F0x64_x21_STRUCT D0F0x64_x21; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Enter\n"); + if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) { + Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber; + Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber; + } + if (!PcieConfigIsSbPcieEngine (Engine)) { + ComplexConfig = (TN_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); + LibAmdMemFill (&FreeDevMap[0], 0x0, sizeof (FreeDevMap), GnbLibGetHeader (Pcie)); + LibAmdMemCopy (&PortDevMap[0], &ComplexConfig->FmSilicon.PortDevMap, sizeof (PortDevMap), GnbLibGetHeader (Pcie)); + for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) { + if (PortDevMap[PortIndex] != 0) { + FreeDevMap[PortDevMap[PortIndex] - 2] = 1; + } + } + EnginePortIndex = Engine->Type.Port.PortData.DeviceNumber - 2; + if (FreeDevMap[EnginePortIndex] == 0) { + // Dev number not yet allocated + ComplexConfig->FmSilicon.PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber; + FreeDevMap[EnginePortIndex] = 1; + PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber; + for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) { + if (PortDevMap[PortIndex] == 0) { + for (FreeIndex = 0; FreeIndex < sizeof (FreeDevMap); FreeIndex++) { + if (FreeDevMap[FreeIndex] == 0) { + FreeDevMap[FreeIndex] = 1; + break; + } + } + PortDevMap[PortIndex] = FreeIndex + 2; + } + } + + GnbRegisterReadTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie)); + D0F0x64_x20.Field.ProgDevMapEn = 0; + GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie)); + D0F0x64_x21.Field.GfxPortADevmap = PortDevMap[2 - 2]; + D0F0x64_x21.Field.GfxPortBDevmap = PortDevMap[3 - 2]; + D0F0x64_x20.Field.GppPortBDevmap = PortDevMap[4 - 2]; + D0F0x64_x20.Field.GppPortCDevmap = PortDevMap[5 - 2]; + D0F0x64_x20.Field.GppPortDDevmap = PortDevMap[6 - 2]; + D0F0x64_x20.Field.GppPortEDevmap = PortDevMap[7 - 2]; + D0F0x64_x20.Field.ProgDevMapEn = 0x1; + GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie)); + GnbRegisterWriteTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie)); + D0F0x64_x20.Field.ProgDevMapEn = 1; + GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie)); + } else { + IDS_HDT_CONSOLE (GNB_TRACE, " Fail device %d to port %d\n", Engine->Type.Port.PortData.DeviceNumber, Engine->Type.Port.NativeDevNumber); + Status = AGESA_ERROR; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get total number of silicons/wrappers/engines for this complex + * + * + * + * @param[in] SocketId Socket ID. + * @param[out] Length Length of configuration info block + * @param[out] StdHeader Standard configuration header + * @retval AGESA_SUCCESS Configuration data length is correct + */ +AGESA_STATUS +PcieGetComplexDataLengthTN ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *Length = sizeof (TN_COMPLEX_CONFIG); + return AGESA_SUCCESS; +} + + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Build configuration + * + * + * + * @param[in] SocketId Socket ID. + * @param[out] Buffer Pointer to buffer to build internal complex data structure + * @param[out] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieBuildComplexConfigurationTN ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdMemCopy (Buffer, &ComplexDataTN, sizeof (TN_COMPLEX_CONFIG), StdHeader); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * get native PHY lane bitmap + * + * + * @param[in] PhyLaneBitmap Package PHY lane bitmap + * @param[in] Engine Standard configuration header. + * @retval Native PHY lane bitmap + */ +UINT32 +PcieGetNativePhyLaneBitmapTN ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + return PhyLaneBitmap; +} + +STATIC PCIe_PORT_DESCRIPTOR DefaultSbPortTN = { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0) +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Build default SB configuration descriptor + * + * + * @param[in] SocketId Socket Id + * @param[out] SbPort Pointer to SB configuration descriptor + * @param[in] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieGetSbConfigInfoTN ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdMemCopy (SbPort, &DefaultSbPortTN, sizeof (DefaultSbPortTN), StdHeader); + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c new file mode 100644 index 0000000000..642f41ff89 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c @@ -0,0 +1,810 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 64781 $ @e \$Date: 2012-01-30 21:19:50 -0600 (Mon, 30 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV1.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "GnbNbInitLibV4.h" +#include "PcieLibTN.h" +#include "PcieComplexDataTN.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "cpuFamilyTranslation.h" +#include "cpuFamRegisters.h" +#include "F15TnPackageType.h" +#include "GeneralServices.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN; +extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN; +extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * PHY lane parameter Init + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +STATIC AGESA_STATUS +PciePhyLaneInitInitCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Phy; + UINT8 PhyLaneIndex; + UINT8 Lane; + UINT32 LaneBitmap; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Enter\n"); + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper); + for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) { + if ((LaneBitmap & (1 << Lane)) != 0) { + Phy = Lane / MAX_NUM_LANE_PER_PHY; + PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY; + PcieRegisterRMW ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_400A_ADDRESS + PhyLaneIndex * 0x80), + D0F0xE4_PHY_400A_BiasDisInLs2_MASK | D0F0xE4_PHY_400A_Ls2ExitTime_MASK, + (1 << D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET) | (1 << D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET), + FALSE, + Pcie + ); + PcieRegisterRMW ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4002_ADDRESS + PhyLaneIndex * 0x80), + D0F0xE4_PHY_4002_LfcMax_MASK, + (8 << D0F0xE4_PHY_4002_LfcMax_OFFSET), + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Satic init for various registers. + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +STATIC +PcieEarlyStaticInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINTN Index; + + for (Index = 0; Index < PcieInitEarlyTableTN.Length; Index++) { + GnbLibPciIndirectRMW ( + MAKE_SBDFO (0,0,0,0, D0F0xE0_ADDRESS), + PcieInitEarlyTableTN.Table[Index].Reg, + AccessWidth32, + (UINT32)~PcieInitEarlyTableTN.Table[Index].Mask, + PcieInitEarlyTableTN.Table[Index].Data, + GnbLibGetHeader (Pcie) + ); + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init core registers. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +STATIC +PcieEarlyCoreInitTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 CoreId; + UINTN Index; + if (PcieLibIsPcieWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Enter\n"); + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + for (Index = 0; Index < CoreInitTableTN.Length; Index++) { + UINT32 Value; + Value = PcieRegisterRead ( + Wrapper, + CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg), + Pcie + ); + Value &= (~CoreInitTableTN.Table[Index].Mask); + Value |= CoreInitTableTN.Table[Index].Data; + PcieRegisterWrite ( + Wrapper, + CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg), + Value, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Dll Cap based on fuses + * + * + * + * @param[in] Wrapper Pointer to Wrapper configuration data area + * @param[in] Pcie Pointer to PCIe configuration data area + */ +STATIC VOID +PcieSetDllCapTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D18F3x1FC_STRUCT D18F3x1FC; + D0F0xE4_PHY_500F_STRUCT D0F0xE4_PHY_500F; + D0F0xE4_PHY_4010_STRUCT D0F0xE4_PHY_4010; + D0F0xE4_PHY_4011_STRUCT D0F0xE4_PHY_4011; + UINT32 Gen1Index; + UINT32 Gen2Index; + CPU_LOGICAL_ID LogicalId; + GNB_HANDLE *GnbHandle; + + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Enter\n"); + + D0F0xE4_PHY_500F.Value = 0; + GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie)); + ASSERT (GnbHandle != NULL); + GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Pcie)); + + //Read SWDllCapTableEn + GnbRegisterReadTN (D18F3x1FC_TYPE, D18F3x1FC_ADDRESS, &D18F3x1FC, 0, GnbLibGetHeader (Pcie)); + IDS_HDT_CONSOLE (GNB_TRACE, "Read D18F3x1FC value %x\n", D18F3x1FC.Value); + + if ((D18F3x1FC.Field.SWDllCapTableEn != 0) || ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull )) { + IDS_HDT_CONSOLE (GNB_TRACE, "Executing DLL configuration\n"); + // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]0 Phy Receiver Functional Fuse Control (FuseFuncDllProcessCompCtl[1:0]) + + IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4010 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS)); + D0F0xE4_PHY_4010.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS), Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "Read 4010 value = %x\n", D0F0xE4_PHY_4010.Value); + // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]1 Phy Receiver Process Fuse Control (FuseProcDllProcessComp[2:0]) + IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4011 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS)); + D0F0xE4_PHY_4011.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS), Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "Read 4011 value = %x\n", D0F0xE4_PHY_4011.Value); + + // If FuseProcDllProcessCompCtl[1:0] == 2'b11 Then Gen1Index[3:0] = FuseProcDllProcessComp[2:0], 0 + // Else... + // If FuseProcDllProcessComp[2:0] == 3'b000 Then Gen1Index[3:0] =4'b1101 //Typical + // If FuseProcDllProcessComp[2:0] == 3'b001 Then Gen1Index[3:0] =4'b1111 //Fast + // If FuseProcDllProcessComp[2:0] == 3'b010 Then Gen1Index[3:0] =4'b1010 //Slow + IDS_HDT_CONSOLE (GNB_TRACE, "FuseFuncDllProcessCompCtl %x\n", D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl); + if (D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl == 3) { + IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from FuseFuncDllProcessComp %x\n", D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp); + Gen1Index = D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp << 1; + } else { + IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from switch case..."); + switch (D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp) { + case 0: + IDS_HDT_CONSOLE (GNB_TRACE, "case 0 - using 0xd\n"); + Gen1Index = 0xd; + break; + case 1: + IDS_HDT_CONSOLE (GNB_TRACE, "case 1 - using 0xf\n"); + Gen1Index = 0xf; + break; + case 2: + IDS_HDT_CONSOLE (GNB_TRACE, "case 2 - using 0xa\n"); + Gen1Index = 0xa; + break; + default: + IDS_HDT_CONSOLE (GNB_TRACE, "default - using 0xd\n"); + Gen1Index = 0xd; //Use typical for default case + break; + } + } + D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex1 = Gen1Index; + IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen1Index to %x\n", Gen1Index); + // Bits 3:0 = Gen1Index[3:0] + // Bits 10:7 = DllProcessFreqCtlIndex2Rate50[3:0] + if (D18F3x1FC.Field.SWDllCapTableEn != 0) { + IDS_HDT_CONSOLE (GNB_TRACE, "Gen2Index - using DllProcFreqCtlIndex2Rate50 = %x\n", D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50); + Gen2Index = D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50; + } else { + Gen2Index = 0x03; // Hard coded default + } + D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex2 = Gen2Index; + IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen2Index to %x\n", Gen2Index); + PcieRegisterWrite ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS), + D0F0xE4_PHY_500F.Value, + FALSE, + Pcie + ); + // Set DllProcessFreqCtlOverride on second write + D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1; + PcieRegisterWrite ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS), + D0F0xE4_PHY_500F.Value, + FALSE, + Pcie + ); + if (Wrapper->WrapId == 1) { + // For Wrapper 1, configure PHY0 and PHY1 + D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 0; + PcieRegisterWrite ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS), + D0F0xE4_PHY_500F.Value, + FALSE, + Pcie + ); + // Set DllProcessFreqCtlOverride on second write + D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1; + PcieRegisterWrite ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS), + D0F0xE4_PHY_500F.Value, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * TN FP2 PCIE allocation x8 check + * + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ + + +STATIC AGESA_STATUS +PcieFP2x8CheckCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 LaneBitmap; + AGESA_STATUS Status; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Enter\n"); + + Status = AGESA_SUCCESS; + if (Wrapper->WrapId == GFX_WRAP_ID) { + + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); + IDS_HDT_CONSOLE (GNB_TRACE, "FP2 GFX Wrpper phy LaneBitmap = %x\n", LaneBitmap); + + if (((LaneBitmap & 0xFF) != 0) && ((LaneBitmap & 0xFF00) != 0)) { + IDS_HDT_CONSOLE (GNB_TRACE, "Error!! FP2 GFX Wrpper cannot use both phy#\n"); + Status = AGESA_ERROR; + PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_LANES_CONFIGURATION, + (LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane), + (LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane), + 0, + 0, + GnbLibGetHeader (Pcie) + ); + + ASSERT (FALSE); + } + } + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Exit\n"); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * TN FP2 PCIE critera check + * + * + * + * @param[in] Pcie Pointer to PICe configuration data area + */ + + +STATIC AGESA_STATUS +PcieFP2CriteriaTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Enter\n"); + + // PACKAGE_TYPE_FP2 1 + // PACKAGE_TYPE_FS1r2 2 + // PACKAGE_TYPE_FM2 4 + if (LibAmdGetPackageType (GnbLibGetHeader (Pcie)) != PACKAGE_TYPE_FP2) { + return AGESA_SUCCESS; + } + // FP2 force gen1 + Pcie->PsppPolicy = PsppPowerSaving; + // FP2 only use x8 on the same PHY + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieFP2x8CheckCallbackTN, NULL, Pcie); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Exit\n"); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * RX offset cancellation enablement + * + * + * + * @param[in] Wrapper Pointer to Wrapper configuration data area + * @param[in] Pcie Pointer to PCIe configuration data area + */ +STATIC VOID +PcieOffsetCancelCalibration ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 LaneBitmap; + D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C; + + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper); + if ((Wrapper->WrapId != GFX_WRAP_ID) && (Wrapper->WrapId != GPP_WRAP_ID)) { + return; + } + + if (LaneBitmap != 0) { + D0F0xBC_x1F39C.Value = 0; + D0F0xBC_x1F39C.Field.Tx = 1; + D0F0xBC_x1F39C.Field.Rx = 1; + D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane; + D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane; + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Wrapper)->Address, + SMC_MSG_PHY_LN_OFF, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Wrapper)->Address, + SMC_MSG_PHY_LN_ON, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + PcieTopologyLaneControl ( + EnableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, 0, Wrapper), + Wrapper, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +STATIC AGESA_STATUS +PcieInitSrbmCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); + PcieOffsetCancelCalibration (Wrapper, Pcie); + PciePifApplyGanging (Wrapper, Pcie); + PciePhyApplyGanging (Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PHY Pll Personality Init Callback + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +STATIC AGESA_STATUS +PciePhyLetPllPersonalityInitCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Enter\n"); + PciePifPllPowerControl (PowerDownPifs, Wrapper, Pcie); + PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PcieTopologyLaneControl ( + DisableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper), + Wrapper, + Pcie + ); + PciePollPifForCompeletion (Wrapper, Pcie); + PcieSetPhyPersonalityTN (Wrapper, Pcie); + PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PcieTopologyLaneControl ( + EnableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper), + Wrapper, + Pcie + ); + PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PciePifPllPowerControl (PowerUpPifs, Wrapper, Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Exit\n"); + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Init prior training. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +STATIC +PcieEarlyInitCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + BOOLEAN CoreConfigChanged; + BOOLEAN PllConfigChanged; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Enter\n"); + CoreConfigChanged = FALSE; + PllConfigChanged = FALSE; + PcieTopologyPrepareForReconfig (Wrapper, Pcie); + Status = PcieTopologySetCoreConfig (Wrapper, &CoreConfigChanged, Pcie); + ASSERT (Status == AGESA_SUCCESS); + PcieTopologyApplyLaneMux (Wrapper, Pcie); + PciePifSetRxDetectPowerMode (Wrapper, Pcie); + PciePifSetLs2ExitTime (Wrapper, Pcie); + PcieTopologySelectMasterPll (Wrapper, &PllConfigChanged, Pcie); + if (CoreConfigChanged || PllConfigChanged) { + PcieTopologyExecuteReconfigV4 (Wrapper, Pcie); + } + PcieTopologyCleanUpReconfig (Wrapper, Pcie); + PcieTopologySetLinkReversalV4 (Wrapper, Pcie); + + if (Wrapper->Features.PowerOffUnusedPlls != 0) { + PciePifPllPowerDown ( + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC | LANE_TYPE_DDI_PHY_NATIVE, Wrapper), + Wrapper, + Pcie + ); + PciePifPllInitForDdi (Wrapper, Pcie); + PciePwrPowerDownDdiPllsV4 (Wrapper, Pcie); + } + PcieTopologyLaneControl ( + DisableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper), + Wrapper, + Pcie + ); + PcieSetDdiOwnPhyV4 (Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PciePhyAvertClockPickers (Wrapper, Pcie); + PcieEarlyCoreInitTN (Wrapper, Pcie); + PcieSetSsidV4 (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie); + if (PcieConfigIsPcieWrapper (Wrapper)) { + PcieSetDllCapTN (Wrapper, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Exit [%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Init + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PcieEarlyInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieFP2CriteriaTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallbackTN, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PcieEarlyStaticInitTN (Pcie); + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLetPllPersonalityInitCallbackTN, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PcieOscInitTN (Pcie); + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLaneInitInitCallbackTN, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieEarlyInitCallbackTN, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PcieSetVoltageTN (PcieGen1, Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Exit [%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieEarlyPortInitCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Enter\n"); + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + PciePortProgramRegisterTable (PortInitEarlyTableTN.Table, PortInitEarlyTableTN.Length, Engine, FALSE, Pcie); + PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie); + PcieSetLinkWidthCap (Engine, Pcie); + PcieCompletionTimeout (Engine, Pcie); + PcieLinkSetSlotCap (Engine, Pcie); + PcieLinkInitHotplug (Engine, Pcie); + //PciePhyChannelCharacteristic (Engine, Pcie); + if (Engine->Type.Port.PortData.PortPresent == PortDisabled || + (Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent && + Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced && + Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) { + ASSERT (!PcieConfigIsSbPcieEngine (Engine)); + // + // Pass endpoint tstaus in scratch + // + PciePortRegisterRMW ( + Engine, + DxF0xE4_x01_ADDRESS, + 0x1, + 0x1, + FALSE, + Pcie + ); + PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PcieEarlyPortInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateResetExit; + } + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieEarlyPortInitCallbackTN, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PcieEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceTN Enter\n"); + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlTN (UnhidePorts, Pcie); + + Status = PcieEarlyInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieEarlyPortInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader); + PciePortsVisibilityControlTN (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c new file mode 100644 index 0000000000..f0cf287a7f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Env Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + S3_SAVE_DISPATCH (StdHeader, PcieLateRestoreTNS3Script_ID, 0, NULL); + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c new file mode 100644 index 0000000000..3d00bdb6e2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c @@ -0,0 +1,639 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * TN specific PCIe configuration data services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbFuseTable.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbSbLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbNbInitLibV1.h" +#include "PcieComplexDataTN.h" +#include "PcieLibTN.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +PCIE_LINK_SPEED_CAP +PcieGetLinkSpeedCapTN ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Control port visibility in PCI config space + * + * + * @param[in] Control Make port Hide/Unhide ports + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePortsVisibilityControlTN ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SILICON_CONFIG *Silicon; + Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header); + ASSERT (Silicon != NULL); + switch (Control) { + case UnhidePorts: + PcieSiliconUnHidePorts (Silicon, Pcie); + break; + case HidePorts: + PcieSiliconHidePorts (Silicon, Pcie); + break; + default: + ASSERT (FALSE); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down inactive lanes + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePowerDownPllInL1TN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + + UINT32 LaneBitmapForPllOffInL1; + UINT32 ActiveLaneBitmap; + UINT8 PllPowerUpLatency; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1TN Enter\n"); + ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper); + if (ActiveLaneBitmap != 0) { + PllPowerUpLatency = PciePifGetPllPowerUpLatencyTN (Wrapper, Pcie); + LaneBitmapForPllOffInL1 = PcieLanesToPowerDownPllInL1 (PllPowerUpLatency, Wrapper, Pcie); + if ((LaneBitmapForPllOffInL1 != 0) && ((ActiveLaneBitmap & LaneBitmapForPllOffInL1) == ActiveLaneBitmap)) { + LaneBitmapForPllOffInL1 &= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper); + LaneBitmapForPllOffInL1 |= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, 0, Wrapper); + PciePifSetPllModeForL1 (LaneBitmapForPllOffInL1, Wrapper, Pcie); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1TN Exit\n"); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Request boot up voltage + * + * + * + * @param[in] LinkCap Global GEN capability + * @param[in] Pcie Pointer to PCIe configuration data area + */ +VOID +PcieSetVoltageTN ( + IN PCIE_LINK_SPEED_CAP LinkCap, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 TargetVid; + D0F0xBC_xE010705C_STRUCT D0F0xBC_xE010705C; + GMMx63C_STRUCT GMMx63C; + GMMx640_STRUCT GMMx640; + UINT8 MinVidIndex; + D0F0xBC_xE0001008_STRUCT D0F0xBC_xE0001008; + UINT8 SclkVid[4]; + UINT8 Index; + PP_FUSE_ARRAY *PpFuseArray; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageTN Enter\n"); + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Pcie)); + if (PpFuseArray == NULL) { + GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, GnbLibGetHeader (Pcie)); + SclkVid[0] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid0; + SclkVid[1] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid1; + SclkVid[2] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid2; + SclkVid[3] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid3; + GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE010705C_ADDRESS, &D0F0xBC_xE010705C, 0, GnbLibGetHeader (Pcie)); + Index = (UINT8) D0F0xBC_xE010705C.Field.PcieGen2Vid; + } else { + SclkVid[0] = PpFuseArray->SclkVid[0]; + SclkVid[1] = PpFuseArray->SclkVid[1]; + SclkVid[2] = PpFuseArray->SclkVid[2]; + SclkVid[3] = PpFuseArray->SclkVid[3]; + Index = PpFuseArray->PcieGen2Vid; + } + if (LinkCap > PcieGen1) { + ASSERT (SclkVid[Index] != 0); + TargetVid = SclkVid[Index]; + } else { + + MinVidIndex = 0; + for (Index = 0; Index < 4; Index++) { + if (SclkVid[Index] > SclkVid[MinVidIndex]) { + MinVidIndex = (UINT8) Index; + } + } + ASSERT (SclkVid[MinVidIndex] != 0); + TargetVid = SclkVid[MinVidIndex]; + } + IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid code %d\n", LinkCap, TargetVid); + + GnbRegisterReadTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, 0, GnbLibGetHeader (Pcie)); + //Wait for voltage change to complete before it can issue next voltage change request + do { + GnbRegisterReadTN (GMMx640_TYPE, GMMx640_ADDRESS, &GMMx640, 0, GnbLibGetHeader (Pcie)); + } while (GMMx640.Field.VoltageChangeAck != GMMx63C.Field.VoltageChangeReq); + //Enable voltage client + if (LinkCap == PcieGen1) { + GMMx63C.Field.VoltageChangeEn = 0; + } else { + GMMx63C.Field.VoltageChangeEn = 1; + } + GnbRegisterWriteTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + //Program level and toggle request + GMMx63C.Field.VoltageLevel = TargetVid; + GMMx63C.Field.VoltageChangeReq = !GMMx63C.Field.VoltageChangeReq; + GnbRegisterWriteTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + //Wait for voltage change to complete before it can issue next voltage change request + do { + GnbRegisterReadTN (GMMx640_TYPE, GMMx640_ADDRESS, &GMMx640, 0, GnbLibGetHeader (Pcie)); + } while (GMMx640.Field.VoltageChangeAck != GMMx63C.Field.VoltageChangeReq); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PLL power up latency + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + * @retval Pll wake up latency in us + */ +UINT8 +PciePifGetPllPowerUpLatencyTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + return 35; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get max link speed capability supported by this port + * + * + * + * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX + * @param[in] Engine Pointer to engine config descriptor + * @retval PcieGen1/PcieGen2 Max supported link gen capability + */ +PCIE_LINK_SPEED_CAP +PcieGetLinkSpeedCapTN ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + TN_COMPLEX_CONFIG *ComplexData; + PCIe_PLATFORM_CONFIG *Pcie; + + ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); + LinkSpeedCapability = PcieGen2; + ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header); + if (ComplexData->FmSilicon.OscMode == OscRO || ComplexData->FmSilicon.OscMode == OscLC || ComplexData->FmSilicon.OscMode == OscDefault) { + LinkSpeedCapability = PcieGen2; + } else { + LinkSpeedCapability = PcieGen1; + } + if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) { + Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability; + } + if (Pcie->PsppPolicy == PsppPowerSaving) { + LinkSpeedCapability = PcieGen1; + } + if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) { + LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability; + } + if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) { + if ((Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) { + LinkSpeedCapability = PcieGen1; + } + } + return LinkSpeedCapability; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set PLL personality + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieSetPhyPersonalityTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Phy; + UINT8 Mode; + if (Wrapper->WrapId == GFX_WRAP_ID || Wrapper->WrapId == DDI_WRAP_ID || Wrapper->WrapId == DDI2_WRAP_ID) { + for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { + if (Wrapper->WrapId == GFX_WRAP_ID) { + Mode = (Phy == 0)? 0x1 : 0; + } else { + Mode = 0x2; + } + PcieRegisterWriteField ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2005_ADDRESS), + D0F0xE4_PHY_2005_PllMode_OFFSET, + D0F0xE4_PHY_2005_PllMode_WIDTH, + Mode, + FALSE, + Pcie + ); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * DCC recalibration + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in,out] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC AGESA_STATUS +PcieForceDccRecalibrationCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePhyForceDccRecalibration (Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Prepare for Osc switch + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC AGESA_STATUS +PcieOscPifInitPrePowerdownCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePifFullPowerStateControl (PowerDownPifs, Wrapper, Pcie); + PcieTopologyLaneControl ( + DisableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper), + Wrapper, + Pcie + ); + PciePifSetPllRampTime (LongRampup, Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Do Osc switch + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC AGESA_STATUS +PcieOscInitPllModeCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + TN_COMPLEX_CONFIG *ComplexData; + TN_PCIe_SILICON_CONFIG *FmSilicon; + UINT8 Phy; + ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetParentSilicon (Wrapper); + ASSERT (ComplexData != NULL); + FmSilicon = &ComplexData->FmSilicon; + if (Wrapper->WrapId == GFX_WRAP_ID) { + Phy = 1; + } else if (Wrapper->WrapId == GPP_WRAP_ID) { + Phy = 0; + } else { + ASSERT (FALSE); + return AGESA_ERROR; + } + switch (FmSilicon->OscMode) { + case OscLC: + PcieRegisterWriteField ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS), + D0F0xE4_PHY_2002_IsLc_OFFSET, + D0F0xE4_PHY_2002_IsLc_WIDTH, + 0x1, + FALSE, + Pcie + ); + break; + case OscRO: + PcieRegisterWriteField ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS), + D0F0xE4_PHY_2002_RoCalEn_OFFSET, + D0F0xE4_PHY_2002_RoCalEn_WIDTH, + 0x0, + FALSE, + Pcie + ); + PcieRegisterWriteField ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS), + D0F0xE4_PHY_2002_RoCalEn_OFFSET, + D0F0xE4_PHY_2002_RoCalEn_WIDTH, + 0x1, + FALSE, + Pcie + ); + break; + default: + ASSERT (FALSE); + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Post Osc init + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC AGESA_STATUS +PcieOscPifInitPostPowerdownCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PcieTopologyLaneControl ( + EnableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper), + Wrapper, + Pcie + ); + PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie); + PciePifFullPowerStateControl (PowerUpPifs, Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Prepare PHY for Gen2 + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieOscInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + TN_COMPLEX_CONFIG *ComplexData; + TN_PCIe_SILICON_CONFIG *FmSilicon; + D0F0xE4_WRAP_FFF1_STRUCT D0F0xE4_WRAP_FFF1; + AGESA_STATUS Status; + UINT8 SaveSbLinkAspm; + UINT32 Value; + + Value = 0; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieOscInitTN Enter\n"); + ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header); + ASSERT (ComplexData != NULL); + FmSilicon = &ComplexData->FmSilicon; + + IDS_HDT_CONSOLE (GNB_TRACE, " OSC Mode - %s\n", + (FmSilicon->OscMode == OscFuses) ? "Fuses" : ( + (FmSilicon->OscMode == OscRO) ? "RO" : ( + (FmSilicon->OscMode == OscLC) ? "LC" : ( + (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown"))) + ); + + if (FmSilicon->OscMode == OscFuses) { + D0F0xE4_WRAP_FFF1.Value = PcieRegisterRead ( + &ComplexData->GppWrapper, + WRAP_SPACE (ComplexData->GppWrapper.WrapId, D0F0xE4_WRAP_FFF1_ADDRESS), + Pcie + ); + + if (D0F0xE4_WRAP_FFF1.Field.ROSupportGen2) { + FmSilicon->OscMode = OscRO; + } else if (D0F0xE4_WRAP_FFF1.Field.LcSupportGen2) { + FmSilicon->OscMode = OscLC; + } else { + FmSilicon->OscMode = OscDefault; + } + + IDS_HDT_CONSOLE (GNB_TRACE, " OSC Mode From Fuses - %s\n", + (FmSilicon->OscMode == OscFuses) ? "Fuses" : ( + (FmSilicon->OscMode == OscRO) ? "RO" : ( + (FmSilicon->OscMode == OscLC) ? "LC" : ( + (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown"))) + ); + } + if (FmSilicon->OscMode != OscDefault) { + + PcieConfigRunProcForAllWrappers ( + DESCRIPTOR_PCIE_WRAPPER, + PcieOscPifInitPrePowerdownCallback, + NULL, + Pcie + ); + PcieConfigRunProcForAllWrappers ( + DESCRIPTOR_PCIE_WRAPPER, + PcieOscInitPllModeCallback, + NULL, + Pcie + ); + PcieConfigRunProcForAllWrappers ( + DESCRIPTOR_PCIE_WRAPPER, + PcieForceDccRecalibrationCallbackTN, + NULL, + Pcie + ); + + SaveSbLinkAspm = ComplexData->Port8.Type.Port.PortData.LinkAspm; + ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmL1; + + Status = SbPcieLinkAspmControl (&ComplexData->Port8, Pcie); + ASSERT (Status == AGESA_SUCCESS); +#ifdef USE_L1_POLLING + //Use L1 Entry pooling + PciePollLinkForL1Entry (&ComplexData->Port8, Pcie); +#else + { + D0F0xBC_x1F630_STRUCT D0F0xBC_x1F630; + + GnbRegisterReadTN (D0F0xBC_x1F630_TYPE, D0F0xBC_x1F630_ADDRESS, &D0F0xBC_x1F630.Value, 0, GnbLibGetHeader (Pcie)); + D0F0xBC_x1F630.Field.RECONF_WAIT = 60; + GnbRegisterWriteTN (D0F0xBC_x1F630_TYPE, D0F0xBC_x1F630_ADDRESS, &D0F0xBC_x1F630.Value, 0, GnbLibGetHeader (Pcie)); + + GnbSmuServiceRequestV4 ( + ComplexData->Silicon.Address, + SMC_MSG_PCIE_PLLSWITCH, + 0, + GnbLibGetHeader (Pcie) + ); + } +#endif + ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmDisabled; + + SbPcieLinkAspmControl (&ComplexData->Port8, Pcie); + PciePollLinkForL0Exit (&ComplexData->Port8, Pcie); + + ComplexData->Port8.Type.Port.PortData.LinkAspm = SaveSbLinkAspm; + + PcieConfigRunProcForAllWrappers ( + DESCRIPTOR_PCIE_WRAPPER, + PcieOscPifInitPostPowerdownCallback, + NULL, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieOscInitTN Exit\n"); +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h new file mode 100644 index 0000000000..1f65ce2ecf --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h @@ -0,0 +1,110 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * TN specific PCIe configuration data services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIELIBTN_H_ +#define _PCIELIBTN_H_ + +VOID +PciePortsVisibilityControlTN ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePowerDownPllInL1TN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetVoltageTN ( + IN PCIE_LINK_SPEED_CAP LinkCap, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT8 +PciePifGetPllPowerUpLatencyTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetPhyPersonalityTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieOscInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c new file mode 100644 index 0000000000..2a751be1b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c @@ -0,0 +1,283 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "GnbFamServices.h" +#include "PcieLibTN.h" +#include "PciePowerGateTN.h" +#include "PciePortServicesV4.h" +#include "PcieMaxPayloadV4.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieMidPortInitCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePortProgramRegisterTable (PortInitMidTableTN.Table, PortInitMidTableTN.Length, Engine, TRUE, Pcie); + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + PcieEnableSlotPowerLimit (Engine, Pcie); + if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) { + PcieInitPortForIommuV4 (Engine, Pcie); + } + } + PcieEnableAspm (Engine, Pcie); + if (GnbBuildOptions.CfgMaxPayloadEnable) { + PcieSetMaxPayload (Engine->Type.Port.Address, GnbLibGetHeader (Pcie)); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PcieMidPortInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + PCIE_LINK_SPEED_CAP GlobalSpeedCap; + + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieMidPortInitCallbackTN, + NULL, + Pcie + ); + + GlobalSpeedCap = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, + Pcie + ); + + + PcieSetVoltageTN (GlobalSpeedCap, Pcie); + + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Late Init. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +STATIC +PcieMidInitCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePwrPowerDownUnusedLanes (Wrapper, Pcie); + PciePowerDownPllInL1TN (Wrapper, Pcie); + PciePwrClockGatingV4 (Wrapper, Pcie); + PcieLockRegisters (Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Late Init + * + * Late PCIe initialization + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PcieMidInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieMidInitCallbackTN, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = PciePowerGateTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Mid Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlTN (UnhidePorts, Pcie); + + Status = PcieMidPortInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieMidInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlTN (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c new file mode 100644 index 0000000000..b30e92b437 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c @@ -0,0 +1,498 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63818 $ @e \$Date: 2012-01-09 03:02:03 -0600 (Mon, 09 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV1.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "PcieLibTN.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PciePostEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PciePostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PciePostS3InterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieLateRestoreInitTNS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePostPortInitCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); + PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie); + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) { + PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); + PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieForceCompliance (Engine, Pcie); + PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePostS3PortInitCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + PCIE_LINK_TRAINING_STATE State; + + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + + LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); + PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie); + + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + + if (!PcieConfigIsSbPcieEngine (Engine)) { + // + // General Port + // + State = LinkStateDeviceNotPresent; + if (Engine->Type.Port.PortData.LinkHotplug == HotplugDisabled || Engine->Type.Port.PortData.LinkHotplug == HotplugInboard) { + // + // Non hotplug device: we only check status from previous boot + // + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + State = LinkStateResetExit; + } + } else { + UINT32 PcieScratch; + // + // Get endpoint staus from scratch + // + PcieScratch = PciePortRegisterRead (Engine, DxF0xE4_x01_ADDRESS, Pcie); + // + // Hotplug device: we check ep status if reported + // + if ((PcieScratch & 0x1) == 0) { + State = LinkStateResetExit; + } + } + // + // For compialnce we always leave link in enabled state + // + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode) { + State = LinkStateResetExit; + } + PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); + } else { + // + // SB port + // + State = LinkStateTrainingSuccess; + } + PcieTrainingSetPortState (Engine, State, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostEarlyPortInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + // Distributed Training started at PciePortInit complete it now to get access to PCIe devices + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateTrainingCompleted; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostPortInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePostPortInitCallbackTN, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostS3PortInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePostS3PortInitCallbackTN, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Init + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PciePostInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP GlobalSpeedCap; + + GlobalSpeedCap = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, + Pcie + ); + + + PcieSetVoltageTN (GlobalSpeedCap, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PciePostEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlTN (UnhidePorts, Pcie); + + Status = PciePostEarlyPortInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlTN (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PciePostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlTN (UnhidePorts, Pcie); + + Status = PciePostInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PciePostPortInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlTN (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PciePostS3InterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlTN (UnhidePorts, Pcie); + + Status = PciePostInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Status = PciePostS3PortInitTN (Pcie); + } else { + Status = PciePostPortInitTN (Pcie); + } + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlTN (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe S3 restore + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context Length (not used) + * @param[in] Context Context pointer (not used) + */ +VOID +PcieLateRestoreInitTNS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ) +{ + PciePostS3InterfaceTN (StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c new file mode 100644 index 0000000000..4197fd842c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c @@ -0,0 +1,383 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe power gate initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "OptionGnb.h" +#include "GnbPcieConfig.h" +#include "GnbPcieFamServices.h" +#include "GnbPcieInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PciePowerGateTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Report used lanes + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePowerGateReportActiveLanesCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C; + UINT32 LaneBitmap; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateReportActiveLanesCallbackTN Enter\n"); + LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Engine); + if (LaneBitmap != 0) { + D0F0xBC_x1F39C.Value = 0; + D0F0xBC_x1F39C.Field.Tx = 0; + D0F0xBC_x1F39C.Field.Rx = 0; + D0F0xBC_x1F39C.Field.Core = 0; + D0F0xBC_x1F39C.Field.SkipPhy = 1; + D0F0xBC_x1F39C.Field.SkipCore = 1; + D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + IDS_HDT_CONSOLE ( + PCIE_MISC, + " LowerLaneID - %02d UpperLaneID - %02d Tx - %d Rx - %d Core - %d Exit\n", + D0F0xBC_x1F39C.Field.LowerLaneID, + D0F0xBC_x1F39C.Field.UpperLaneID, + D0F0xBC_x1F39C.Field.Tx, + D0F0xBC_x1F39C.Field.Rx, + D0F0xBC_x1F39C.Field.Core + ); + if (PcieConfigIsPcieEngine (Engine) && PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine) == PcieGen2) { + D0F0xBC_x1F610_STRUCT D0F0xBC_x1F610; + UINT32 Gen2LaneBitmap; + Gen2LaneBitmap = ((1 << (D0F0xBC_x1F39C.Field.UpperLaneID - D0F0xBC_x1F39C.Field.LowerLaneID + 1)) - 1) << D0F0xBC_x1F39C.Field.LowerLaneID; + GnbRegisterReadTN (D0F0xBC_x1F610_TYPE, D0F0xBC_x1F610_ADDRESS, &D0F0xBC_x1F610.Value, 0, GnbLibGetHeader (Pcie)); + D0F0xBC_x1F610.Field.GFXH |= (Gen2LaneBitmap >> 16) & 0xFF; + D0F0xBC_x1F610.Field.GFXL |= (Gen2LaneBitmap >> 8) & 0xFF; + D0F0xBC_x1F610.Field.GPPSB |= (Gen2LaneBitmap & 0xFF ); + GnbRegisterWriteTN (D0F0xBC_x1F610_TYPE, D0F0xBC_x1F610_ADDRESS, &D0F0xBC_x1F610.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + } + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Engine)->Address, + SMC_MSG_PHY_LN_ON, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateReportActiveLanesCallbackTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down unused lanes + * + * + * + * + * @param[in] Wrapper Pointer to wrapper configuration + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS + * + */ + +AGESA_STATUS +STATIC +PciePowerGatePowerDownUnusedLanesCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Index; + UINTN State; + UINT32 LaneBitmap; + UINT16 StartLane; + UINT16 EndLane; + D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownUnusedLanesCallbackTN Enter\n"); + + LaneBitmap = PcieUtilGetWrapperLaneBitMap ( + LANE_TYPE_PHY_NATIVE_ALL, + LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, + Wrapper + ); + IDS_HDT_CONSOLE (GNB_TRACE, " Lane Bitmap 0x%x\n", LaneBitmap); + if (LaneBitmap != 0) { + State = 0; + StartLane = 0; + EndLane = 0; + for (Index = 0; Index <= (LibAmdBitScanReverse (LaneBitmap) + 1); Index++) { + if ((State == 0) && ((LaneBitmap & (1 << Index)) != 0)) { + StartLane = Index; + State = 1; + } else if ((State == 1) && ((LaneBitmap & (1 << Index)) == 0)) { + EndLane = Index - 1; + State = 0; + GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie)); + D0F0xBC_x1F39C.Field.Tx = 1; + D0F0xBC_x1F39C.Field.Rx = 1; + D0F0xBC_x1F39C.Field.Core = 1; + D0F0xBC_x1F39C.Field.LowerLaneID = StartLane + Wrapper->StartPhyLane; + D0F0xBC_x1F39C.Field.UpperLaneID = EndLane + Wrapper->StartPhyLane; + IDS_HDT_CONSOLE ( + PCIE_MISC, + " LowerLaneID - %02d UpperLaneID - %02d Tx - %d Rx - %d Core - %d Exit\n", + D0F0xBC_x1F39C.Field.LowerLaneID, + D0F0xBC_x1F39C.Field.UpperLaneID, + D0F0xBC_x1F39C.Field.Tx, + D0F0xBC_x1F39C.Field.Rx, + D0F0xBC_x1F39C.Field.Core + ); + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Wrapper)->Address, + SMC_MSG_PHY_LN_OFF, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownUnusedLanesCallbackTN Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down unused lanes + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePowerGatePowerDownLanesCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C; + UINT32 LaneBitmap; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownLanesCallbackTN Enter\n"); + LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, Engine); + if (LaneBitmap != 0) { + GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie)); + D0F0xBC_x1F39C.Field.Tx = 1; + D0F0xBC_x1F39C.Field.Rx = 1; + D0F0xBC_x1F39C.Field.Core = 0; + D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + IDS_HDT_CONSOLE ( + PCIE_MISC, + " PCIe Lanes LowerLaneID - %02d UpperLaneID - %02d Tx - %d Rx - %d Core - %d Exit\n", + D0F0xBC_x1F39C.Field.LowerLaneID, + D0F0xBC_x1F39C.Field.UpperLaneID, + D0F0xBC_x1F39C.Field.Tx, + D0F0xBC_x1F39C.Field.Rx, + D0F0xBC_x1F39C.Field.Core + ); + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Engine)->Address, + SMC_MSG_PHY_LN_OFF, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, 0, Engine); + if (LaneBitmap != 0) { + GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie)); + D0F0xBC_x1F39C.Field.Tx = 1; + D0F0xBC_x1F39C.Field.Rx = 1; + D0F0xBC_x1F39C.Field.Core = 1; + D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + IDS_HDT_CONSOLE ( + PCIE_MISC, + " DDI Lanes LowerLaneID - %02d UpperLaneID - %02d Tx - %d Rx - %d Core - %d Exit\n", + D0F0xBC_x1F39C.Field.LowerLaneID, + D0F0xBC_x1F39C.Field.UpperLaneID, + D0F0xBC_x1F39C.Field.Tx, + D0F0xBC_x1F39C.Field.Rx, + D0F0xBC_x1F39C.Field.Core + ); + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Engine)->Address, + SMC_MSG_PHY_LN_OFF, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownLanesCallbackTN Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Power gate init + * + * Late PCIe initialization + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + */ + +AGESA_STATUS +PciePowerGateTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 PowerGatingFlags; + D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateTN Enter\n"); + PowerGatingFlags = GnbBuildOptions.CfgPciePowerGatingFlags; + // Report used lanes + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, + PciePowerGateReportActiveLanesCallbackTN, + NULL, + Pcie + ); + + IDS_OPTION_HOOK (IDS_GNB_PCIE_POWER_GATING, &PowerGatingFlags, GnbLibGetHeader (Pcie)); + + // Update flags + GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie)); + if ((PowerGatingFlags & PCIE_POWERGATING_SKIP_CORE) == 0) { + D0F0xBC_x1F39C.Field.SkipCore = 0; + } + if ((PowerGatingFlags & PCIE_POWERGATING_SKIP_PHY) == 0) { + D0F0xBC_x1F39C.Field.SkipPhy = 0; + } + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + // Power down unused lanes + PcieConfigRunProcForAllWrappers ( + DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, + PciePowerGatePowerDownUnusedLanesCallbackTN, + NULL, + Pcie + ); + //Power down hotplug lanes + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, + PciePowerGatePowerDownLanesCallbackTN, + NULL, + Pcie + ); + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateTN Exit\n"); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h new file mode 100644 index 0000000000..b8d2116a96 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe power gate initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEPOWERGATETN_H_ +#define _PCIEPOWERGATETN_H_ + +AGESA_STATUS +PciePowerGateTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c new file mode 100644 index 0000000000..faa2fa8f80 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c @@ -0,0 +1,258 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 65061 $ @e \$Date: 2012-02-06 23:48:39 -0600 (Mon, 06 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "PcieComplexDataTN.h" +#include "GnbRegistersTN.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + +STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { + { + WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS), + D0F0xE4_WRAP_8016_CalibAckLatency_MASK, + 0 + }, + { + PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), + D0F0xE4_PHY_2008_VdDetectEn_MASK, + 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET + }, + { + PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), + D0F0xE4_PHY_2008_VdDetectEn_MASK, + 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET + }, + { + PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS), + D0F0xE4_PHY_2008_VdDetectEn_MASK, + 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET + }, + { + PHY_SPACE (DDI_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), + D0F0xE4_PHY_2008_VdDetectEn_MASK, + 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET + }, + { + PHY_SPACE (DDI2_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), + D0F0xE4_PHY_2008_VdDetectEn_MASK, + 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET + } + }; + +CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN = { + &PcieInitEarlyTable[0], + sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) +}; + +STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { + { + D0F0xE4_CORE_0020_ADDRESS, + D0F0xE4_CORE_0020_CiRcOrderingDis_MASK | + D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK, + (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET) + }, + { + D0F0xE4_CORE_0010_ADDRESS, + D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK, + (0x4 << D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET) + }, + { + D0F0xE4_CORE_001C_ADDRESS, + D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK | + D0F0xE4_CORE_001C_TxArbSlvLimit_MASK | + D0F0xE4_CORE_001C_TxArbMstLimit_MASK, + (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) | + (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) | + (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET) + }, + { + D0F0xE4_CORE_0040_ADDRESS, + D0F0xE4_CORE_0040_PElecIdleMode_MASK, + (0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET) + }, + { + D0F0xE4_CORE_0002_ADDRESS, + D0F0xE4_CORE_0002_HwDebug_0__MASK, + (0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET) + }, + { + D0F0xE4_CORE_00C1_ADDRESS, + D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK | + D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK, + (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) | + (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET) + }, + { + D0F0xE4_CORE_00B0_ADDRESS, + D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK, + (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET) + } +}; + +CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN = { + &CoreInitTable[0], + sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) +}; + + +STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { + { + DxF0xE4_x02_ADDRESS, + DxF0xE4_x02_RegsLcAllowTxL1Control_MASK, + (0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET) + }, + { + DxF0xE4_x70_ADDRESS, + DxF0xE4_x70_RxRcbCplTimeoutMode_MASK, + (0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET) + }, + { + DxF0xE4_xA0_ADDRESS, + DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK | DxF0xE4_xA0_LcL0sInactivity_MASK, + (0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) | + (0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET) | + (0x6 << DxF0xE4_xA0_LcL0sInactivity_OFFSET) + }, + { + DxF0xE4_xA1_ADDRESS, + DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK, + (0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET) + }, + { + DxF0xE4_xA2_ADDRESS, + DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK, + (0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) | + (0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET) + }, + { + DxF0xE4_xA3_ADDRESS, + DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK, + (0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET) + }, + { + DxF0xE4_xB1_ADDRESS, + DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK, + (0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) | + (0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET) + } +}; + +CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN = { + &PortInitEarlyTable[0], + sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) +}; + + +STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = { + { + DxF0xE4_xA2_ADDRESS, + DxF0xE4_xA2_LcDynLanesPwrState_MASK, + (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET) + }, + { + DxF0xE4_xC0_ADDRESS, + DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK, + (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET) + } +}; + +CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN = { + &PortInitMidTable[0], + sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c new file mode 100644 index 0000000000..fb44d8328e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c @@ -0,0 +1,361 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "cpuLateInit.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbFamServices.h" +#include "GnbCommonLib.h" +#include "GnbIvrsLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +#define IVRS_TABLE_LENGTH 8 * 1024 + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GnbBuildIvmdList ( + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbIommuIvrsTableDump ( + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbIommuIvrsTable ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +IOMMU_IVRS_HEADER IvrsHeader = { + {'I', 'V', 'R', 'S'}, + sizeof (IOMMU_IVRS_HEADER), + 2, + 0, + {'A', 'M', 'D', ' ', ' ', 0}, + {'A', 'M', 'D', 'I', 'O', 'M', 'M', 'U'}, + 1, + {'A','M','D',' '}, + 0, + 0, + 0 +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Build IVRS table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +GnbIommuIvrsTable ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AMD_LATE_PARAMS *LateParamsPtr; + VOID *Ivrs; + BOOLEAN IvrsSupport; + GNB_HANDLE *GnbHandle; + + Status = AGESA_SUCCESS; + LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader; + IvrsSupport = FALSE; + Ivrs = LateParamsPtr->AcpiIvrs; + if (Ivrs == NULL) { + Ivrs = GnbAllocateHeapBuffer ( + AMD_ACPI_IVRS_BUFFER_HANDLE, + IVRS_TABLE_LENGTH, + StdHeader + ); + ASSERT (Ivrs != NULL); + if (Ivrs == NULL) { + return AGESA_ERROR; + } + LateParamsPtr->AcpiIvrs = Ivrs; + } + LibAmdMemFill (Ivrs, 0x0, IVRS_TABLE_LENGTH, StdHeader); + LibAmdMemCopy (Ivrs, &IvrsHeader, sizeof (IvrsHeader), StdHeader); + + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { + IDS_HDT_CONSOLE (GNB_TRACE, "Build IVRS for Socket %d Silicon %d\n", GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); + IvrsSupport = TRUE; + GnbFmCreateIvrsEntry (GnbHandle, IvrsIvhdBlock, Ivrs, StdHeader); + GnbBuildIvmdList (IvrsIvmdBlock, Ivrs, StdHeader); + if (GnbBuildOptions.IvrsRelativeAddrNamesSupport) { + GnbFmCreateIvrsEntry (GnbHandle, IvrsIvhdrBlock, Ivrs, StdHeader); + GnbBuildIvmdList (IvrsIvmdrBlock, Ivrs, StdHeader); + } + } + GnbHandle = GnbGetNextHandle (GnbHandle); + } + if (IvrsSupport == TRUE) { + ChecksumAcpiTable ((ACPI_TABLE_HEADER*) Ivrs, StdHeader); + GNB_DEBUG_CODE (GnbIommuIvrsTableDump (Ivrs, StdHeader)); + } else { + IDS_HDT_CONSOLE (GNB_TRACE, " IVRS table not generated\n"); + LateParamsPtr->AcpiIvrs = NULL; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build IVMD list + * + * + * @param[in] Type Entry type + * @param[in] Ivrs IVRS table pointer + * @param[in] StdHeader Standard configuration header + * + */ + +AGESA_STATUS +GnbBuildIvmdList ( + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IOMMU_EXCLUSION_RANGE_DESCRIPTOR *IvrsExclusionRangeList; + IVRS_IVMD_ENTRY *Ivmd; + UINT16 StartId; + UINT16 EndId; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBuildIvmdList Entry\n"); + IvrsExclusionRangeList = ((AMD_LATE_PARAMS*)StdHeader)->IvrsExclusionRangeList; + if (IvrsExclusionRangeList != NULL) { + // Process the entire IvrsExclusionRangeList here and create an IVMD for eache entry + IDS_HDT_CONSOLE (GNB_TRACE, "Process Exclusion Range List\n"); + while ((IvrsExclusionRangeList->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) { + if ((IvrsExclusionRangeList->Flags & DESCRIPTOR_IGNORE) == 0) { + // Address of IVMD entry + Ivmd = (IVRS_IVMD_ENTRY*) ((UINT8 *)Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength); + StartId = + (IvrsExclusionRangeList->RequestorIdStart.Bus << 8) + + (IvrsExclusionRangeList->RequestorIdStart.Device << 3) + + (IvrsExclusionRangeList->RequestorIdStart.Function); + EndId = + (IvrsExclusionRangeList->RequestorIdEnd.Bus << 8) + + (IvrsExclusionRangeList->RequestorIdEnd.Device << 3) + + (IvrsExclusionRangeList->RequestorIdEnd.Function); + GnbIvmdAddEntry ( + Type, + StartId, + EndId, + IvrsExclusionRangeList->RangeBaseAddress, + IvrsExclusionRangeList->RangeLength, + Ivmd, + StdHeader); + // Add entry size to existing table length + ((IOMMU_IVRS_HEADER *)Ivrs)->TableLength += sizeof (IVRS_IVMD_ENTRY); + } + // Point to next entry in IvrsExclusionRangeList + IvrsExclusionRangeList++; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBuildIvmdList Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump IVRS table + * + * + * @param[in] Ivrs Pointer to IVRS table + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +GnbIommuIvrsTableDump ( + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *Block; + UINT8 *Entry; + Block = (UINT8 *) Ivrs + sizeof (IOMMU_IVRS_HEADER); + IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Start -----------> \n"); + IDS_HDT_CONSOLE (GNB_TRACE, " IVInfo = 0x%08x\n", ((IOMMU_IVRS_HEADER *) Ivrs)-> IvInfo); + while (Block < ((UINT8 *) Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength)) { + if (*Block == IvrsIvhdBlock) { + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block Start -------->\n"); + IDS_HDT_CONSOLE (GNB_TRACE, " Flags = 0x%02x\n", ((IVRS_IVHD_ENTRY *) Block)->Flags); + IDS_HDT_CONSOLE (GNB_TRACE, " DeviceId = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->DeviceId); + IDS_HDT_CONSOLE (GNB_TRACE, " CapabilityOffset = 0x%02x\n", ((IVRS_IVHD_ENTRY *) Block)->CapabilityOffset); + IDS_HDT_CONSOLE (GNB_TRACE, " BaseAddress = 0x%08x%08x\n", (UINT32) (((IVRS_IVHD_ENTRY *) Block)->BaseAddress >> 32), (UINT32) ((IVRS_IVHD_ENTRY *) Block)->BaseAddress); + IDS_HDT_CONSOLE (GNB_TRACE, " PCI Segment = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->PciSegment); + IDS_HDT_CONSOLE (GNB_TRACE, " IommuInfo = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->IommuInfo); + IDS_HDT_CONSOLE (GNB_TRACE, " IommuEfr = 0x%08x\n", ((IVRS_IVHD_ENTRY *) Block)->IommuEfr); + Entry = Block + sizeof (IVRS_IVHD_ENTRY); + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block Device Entries Start -------->\n"); + while (Entry < (Block + ((IVRS_IVHD_ENTRY *) Block)->Length)) { + IDS_HDT_CONSOLE (GNB_TRACE, " "); + switch (*Entry) { + case IvhdEntrySelect: + case IvhdEntryEndRange: + GnbLibDebugDumpBuffer (Entry, 4, 1, 4); + Entry = Entry + 4; + break; + case IvhdEntryStartRange: + GnbLibDebugDumpBuffer (Entry, 8, 1, 8); + Entry = Entry + 8; + break; + case IvhdEntryAliasStartRange: + GnbLibDebugDumpBuffer (Entry, 12, 1, 12); + Entry = Entry + 12; + break; + case IvhdEntryAliasSelect: + case IvhdEntryExtendedSelect: + case IvhdEntrySpecialDevice: + GnbLibDebugDumpBuffer (Entry, 8, 1, 8); + Entry = Entry + 8; + break; + case IvhdEntryPadding: + Entry = Entry + 4; + break; + default: + IDS_HDT_CONSOLE (GNB_TRACE, " Unsupported entry type [%d]\n"); + ASSERT (FALSE); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block Device Entries End -------->\n"); + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block End ---------->\n"); + Block = Block + ((IVRS_IVHD_ENTRY *) Block)->Length; + } else if ( + (*Block == IvrsIvmdBlock) || + (*Block == IvrsIvmdBlockRange) || + (*Block == IvrsIvmdBlockSingle) || + (*Block == IvrsIvmdrBlock) || + (*Block == IvrsIvmdrBlockSingle)) { + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVMD Block Start -------->\n"); + IDS_HDT_CONSOLE (GNB_TRACE, " Flags = 0x%02x\n", ((IVRS_IVMD_ENTRY *) Block)->Flags); + IDS_HDT_CONSOLE (GNB_TRACE, " DeviceId = 0x%04x\n", ((IVRS_IVMD_ENTRY *) Block)->DeviceId); + switch (*Block) { + case IvrsIvmdBlock: + case IvrsIvmdrBlock: + IDS_HDT_CONSOLE (GNB_TRACE, " Applies to all devices\n"); + break; + case IvrsIvmdBlockSingle: + case IvrsIvmdrBlockSingle: + IDS_HDT_CONSOLE (GNB_TRACE, " Applies to a single device\n"); + break; + default: + IDS_HDT_CONSOLE (GNB_TRACE, " DeviceId End = 0x%04x\n", ((IVRS_IVMD_ENTRY *) Block)->AuxiliaryData); + } + IDS_HDT_CONSOLE (GNB_TRACE, " StartAddress = 0x%08x%08x\n", (UINT32) (((IVRS_IVMD_ENTRY *) Block)->BlockStart >> 32), (UINT32) ((IVRS_IVMD_ENTRY *) Block)->BlockStart); + IDS_HDT_CONSOLE (GNB_TRACE, " BockLength = 0x%08x%08x\n", (UINT32) (((IVRS_IVMD_ENTRY *) Block)->BlockLength >> 32), (UINT32) ((IVRS_IVMD_ENTRY *) Block)->BlockLength); + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVMD Block End ---------->\n"); + Block = Block + ((IVRS_IVMD_ENTRY *) Block)->Length; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Raw Data --------> \n"); + GnbLibDebugDumpBuffer (Ivrs, ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength, 1, 16); + IDS_HDT_CONSOLE (GNB_TRACE, "\n"); + IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table End -------------> \n"); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h new file mode 100644 index 0000000000..c48224f970 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBIOMMUIVRS_H_ +#define _GNBIOMMUIVRS_H_ + +AGESA_STATUS +GnbIommuIvrsTable ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c new file mode 100644 index 0000000000..b5eb7ed124 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c @@ -0,0 +1,168 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbFamServices.h" +#include "GnbRegistersTN.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Iommu Scratch Memory Range + * 1) code needs to be executed at Late Init + * 2) Allocate heap using heap type HEAP_RUNTIME_SYSTEM_MEM + * 3) Allocate enough memory to be able to get address aligned required by register + * 4) Assign same address to all Gnb in system + * + * + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +GnbIommuScratchMemoryRangeInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT32 AddressLow; + UINT32 AddressHigh; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuScratchMemoryRangeInterface Enter\n"); + + AllocHeapParams.RequestedBufferSize = 128; + AllocHeapParams.BufferHandle = AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE; + AllocHeapParams.Persist = HEAP_RUNTIME_SYSTEM_MEM; + Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + IDS_HDT_CONSOLE (GNB_TRACE, " Iommu Scratch Memory not allocated.\n"); + ASSERT (FALSE); + return AGESA_FATAL; + } + + AddressLow = (((UINT32) ((UINT64) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; + AddressHigh = ((UINT32) (((UINT64) AllocHeapParams.BufferPtr) >> 32)) & D0F0x98_x26_IOMMUUrAddr_39_32__MASK; + + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { + IDS_HDT_CONSOLE (GNB_TRACE, "Set Iommu Scratch Memory for Socket %d Silicon %d\n", GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); + GnbLibPciIndirectWrite ( + GnbHandle->Address.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x27_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + &AddressLow, + StdHeader); + + GnbLibPciIndirectWrite ( + GnbHandle->Address.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x26_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + &AddressHigh, + StdHeader); + } + GnbHandle = GnbGetNextHandle (GnbHandle); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuScratchMemoryRangeInterface Exit\n"); + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c new file mode 100644 index 0000000000..d18493eb09 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c @@ -0,0 +1,267 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 64895 $ @e \$Date: 2012-02-02 01:01:48 -0600 (Thu, 02 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "cpuLateInit.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbIommu.h" +#include "GnbFamServices.h" +#include "GnbCommonLib.h" +#include "GnbIommuIvrs.h" +#include "GnbIvrsLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVHDR entry for device range + * + * + * @param[in] StartRange Address of start range + * @param[in] EndRange Address of end range + * @param[in] DataSetting Data setting + * @param[in] Ivhd Pointer to IVHD entry + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbIvhdAddDeviceRangeEntry ( + IN PCI_ADDR StartRange, + IN PCI_ADDR EndRange, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IVHD_GENERIC_ENTRY *Entry; + Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length); + Entry->Type = IvhdEntryStartRange; + Entry->DeviceId = DEVICE_ID (StartRange); + Entry->DataSetting = DataSetting; + Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY); + Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length); + Entry->Type = IvhdEntryEndRange; + Entry->DeviceId = DEVICE_ID (EndRange); + Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVHDR entry for aliased range + * + * + * @param[in] StartRange Address of start range + * @param[in] EndRange Address of end range + * @param[in] Alias Address of alias requestor ID for range + * @param[in] DataSetting Data setting + * @param[in] Ivhd Pointer to IVHD entry + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbIvhdAddDeviceAliasRangeEntry ( + IN PCI_ADDR StartRange, + IN PCI_ADDR EndRange, + IN PCI_ADDR Alias, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IVHD_ALIAS_ENTRY *RangeEntry; + IVHD_GENERIC_ENTRY *Entry; + UINT16 Offset; + Offset = (Ivhd->Length + 0x7) & (~ 0x7); + RangeEntry = (IVHD_ALIAS_ENTRY *) ((UINT8 *) Ivhd + Offset); + RangeEntry->Type = IvhdEntryAliasStartRange; + RangeEntry->DeviceId = DEVICE_ID (StartRange); + RangeEntry->AliasDeviceId = DEVICE_ID (Alias); + RangeEntry->DataSetting = DataSetting; + Ivhd->Length = sizeof (IVHD_ALIAS_ENTRY) + Offset; + Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length); + Entry->Type = IvhdEntryEndRange; + Entry->DeviceId = DEVICE_ID (EndRange); + Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVHDR entry for special device + * + * + * @param[in] SpecialDevice Special device Type + * @param[in] Device Address of requestor ID for special device + * @param[in] Id Apic ID/ Hpet ID + * @param[in] DataSetting Data setting + * @param[in] Ivhd Pointer to IVHD entry + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbIvhdAddSpecialDeviceEntry ( + IN IVHD_SPECIAL_DEVICE SpecialDevice, + IN PCI_ADDR Device, + IN UINT8 Id, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IVHD_SPECIAL_ENTRY *SpecialEntry; + UINT16 Offset; + Offset = (Ivhd->Length + 0x7) & (~ 0x7); + SpecialEntry = (IVHD_SPECIAL_ENTRY *) ((UINT8 *) Ivhd + Offset); + SpecialEntry->Type = IvhdEntrySpecialDevice; + SpecialEntry->AliasDeviceId = DEVICE_ID (Device); + SpecialEntry->Variety = (UINT8) SpecialDevice; + SpecialEntry->Handle = Id; + SpecialEntry->DataSetting = DataSetting; + Ivhd->Length = sizeof (IVHD_SPECIAL_ENTRY) + Offset; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVMD entry + * + * + * @param[in] Type Root type for IVMD (IvrsIvmdBlock or IvrsIvmdrBlock) + * @param[in] StartDevice Device ID of start device range + * Use 0x0000 for ALL + * @param[in] EndDevice Device ID of end device range + * Use 0xFFFF for ALL + * Use == StartDevice for specific device + * @param[in] BlockAddress Address of memory block to be excluded + * @param[in] BlockLength Length of memory block go be excluded + * @param[in] Ivmd Pointer to IVMD entry + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbIvmdAddEntry ( + IN IVRS_BLOCK_TYPE Type, + IN UINT16 StartDevice, + IN UINT16 EndDevice, + IN UINT64 BlockAddress, + IN UINT64 BlockLength, + IN IVRS_IVMD_ENTRY *Ivmd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + Ivmd->Flags = IVMD_FLAG_EXCLUSION_RANGE; + Ivmd->Length = sizeof (IVRS_IVMD_ENTRY); + Ivmd->DeviceId = StartDevice; + Ivmd->AuxiliaryData = 0x0; + Ivmd->Reserved = 0x0000000000000000; + Ivmd->BlockStart = BlockAddress; + Ivmd->BlockLength = BlockLength; + if (Type == IvrsIvmdBlock) { + if (StartDevice == EndDevice) { + Ivmd->Type = IvrsIvmdBlockSingle; + } else if ((StartDevice == 0x0000) && (EndDevice == 0xFFFF)) { + Ivmd->Type = IvrsIvmdBlock; + } else { + Ivmd->Type = IvrsIvmdBlockRange; + Ivmd->AuxiliaryData = EndDevice; + } + } else { + if (StartDevice == EndDevice) { + Ivmd->Type = IvrsIvmdrBlockSingle; + } else { + Ivmd->Type = IvrsIvmdrBlock; + } + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h new file mode 100644 index 0000000000..5291d34f1b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h @@ -0,0 +1,117 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBIVRSLIB_H_ +#define _GNBIVRSLIB_H_ + + +VOID +GnbIvhdAddDeviceRangeEntry ( + IN PCI_ADDR StartRange, + IN PCI_ADDR EndRange, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbIvhdAddDeviceAliasRangeEntry ( + IN PCI_ADDR StartRange, + IN PCI_ADDR EndRange, + IN PCI_ADDR Alias, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbIvhdAddSpecialDeviceEntry ( + IN IVHD_SPECIAL_DEVICE SpecialDevice, + IN PCI_ADDR Device, + IN UINT8 Id, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbIvmdAddEntry ( + IN IVRS_BLOCK_TYPE Type, + IN UINT16 StartDevice, + IN UINT16 EndDevice, + IN UINT64 BlockAddress, + IN UINT64 BlockLength, + IN IVRS_IVMD_ENTRY *Ivmd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c new file mode 100644 index 0000000000..f160e8bcb1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c @@ -0,0 +1,203 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB UNB library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuServices.h" +#include "Gnb.h" +#include "GnbCommonLib.h" +#include "GnbFamServices.h" +#include "GnbPcieConfig.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBMSOCKETLIB_GNBMSOCKETLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Host bridge PCI Address + * + * + * + * @param[in] GnbHandle Socket ID + * @param[in] StdHeader Standard configuration header + * @retval PCI address of GNB for a given socket/silicon. + */ + +PCI_ADDR +GnbFmGetPciAddress ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR GnbPciAddress; + UINT8 NodeId; + UINT8 Register; + UINT32 Value; + GnbPciAddress.AddressValue = ILLEGAL_SBDFO; + NodeId = GnbGetNodeId (GnbHandle); + for (Register = 0xE0; Register <= 0xEC; Register = Register + 4) { + GnbLibPciRead (MAKE_SBDFO (0, 0, 24 + NodeId, 1, Register), AccessWidth32, &Value, StdHeader); + if (((Value >> 4) & 0x7) == NodeId) { + GnbPciAddress.AddressValue = MAKE_SBDFO (0, (Value >> 16) & 0xff, 0, 0, 0); + break; + } + } + ASSERT (GnbPciAddress.AddressValue != ILLEGAL_SBDFO); + return GnbPciAddress; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bus range decoded by GNB + * + * Final bus allocation can not be assumed until AmdInitMid + * + * @param[in] GnbHandle GNB handle + * @param[out] StartBusNumber Beggining of the Bus Range + * @param[out] EndBusNumber End of the Bus Range + * @param[in] StdHeader Standard configuration header + * @retval Satus + */ +AGESA_STATUS +GnbFmGetBusDecodeRange ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *StartBusNumber, + OUT UINT8 *EndBusNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 NodeId; + UINT8 Register; + UINT32 Value; + AGESA_STATUS Status; + Status = AGESA_ERROR; + NodeId = GnbGetNodeId (GnbHandle); + for (Register = 0xE0; Register <= 0xEC; Register = Register + 4) { + GnbLibPciRead (MAKE_SBDFO (0, 0, 24 + NodeId, 1, Register), AccessWidth32, &Value, StdHeader); + if (((Value >> 4) & 0x7) == NodeId) { + *StartBusNumber = (UINT8) ((Value >> 16) & 0xff); + *EndBusNumber = (UINT8) ((Value >> 24) & 0xff); + Status = AGESA_SUCCESS; + break; + } + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get link to which GNB connected to + * + * + * @param[in] GnbHandle GNB handle + * @param[out] LinkId Link to which GNB connected to + * @param[in] StdHeader Standard configuration header + * @retval Satus + */ + +AGESA_STATUS +GnbFmGetLinkId ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *LinkId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + ASSERT (GnbHandle->NodeId != 0xFF); + GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18 + GnbHandle->NodeId, 0, 0x1A0), AccessWidth32, &Value, StdHeader); + *LinkId = LibAmdBitScanForward (Value & 0xAAAA) / 2; + ASSERT (*LinkId < 8); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c new file mode 100644 index 0000000000..942d34d539 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c @@ -0,0 +1,432 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include "GnbCommonLib.h" +#include "GnbNbInitLibV1.h" +#include "GnbRegistersLN.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Init NB set top of memory + * + * + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +AGESA_STATUS +GnbSetTom ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + UINT64 MsrData; + UINT32 Value; + Status = AGESA_SUCCESS; + //Read memory size below 4G from MSR C001_001A + LibAmdMsrRead (TOP_MEM, &MsrData, StdHeader); + //Write to NB register 0x90 + Value = (UINT32)MsrData & 0xFF800000; //Keep bits 31:23 + GnbLibPciRMW ( + NbPciAddress.AddressValue | D0F0x90_ADDRESS, + AccessS3SaveWidth32, + 0x007FFFFF, + Value, + StdHeader + ); + if (Value == 0) { + Status = AGESA_WARNING; + } + + LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); + if ((MsrData & BIT21) != 0) { + //Read memory size above 4G from MSR C001_001D + LibAmdMsrRead (TOP_MEM2, &MsrData, StdHeader); + // Write memory size[39:32] to indirect register 1A[7:0] + Value = (UINT32) ((MsrData >> 32) & 0xFF); + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x1A_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + 0xFFFFFF00, + Value, + StdHeader + ); + + // Write memory size[31:23] to indirect register 19[31:23] and enable memory through bit 0 + Value = (UINT32)MsrData & 0xFF800000; //Keep bits 31:23 + Value |= BIT0; // Enable top of memory + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x19_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + 0x007FFFFF, + Value, + StdHeader + ); + } + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Avoid LPC DMA transaction deadlock + * + * + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +GnbLpcDmaDeadlockPrevention ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // For GPP Link core, enable special NP memory write protocol on the processor side PCIE controller + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0xE0_ADDRESS, + CORE_SPACE (1, D0F0xE4_CORE_0010_ADDRESS), + AccessWidth32, + 0xFFFFFFFF, + 1 << 9 , + StdHeader + ); + + //Enable special NP memory write protocol in ORB + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x06_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + 0xFFFFFFFF, + 1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET, + StdHeader + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * NB Dynamic Wake + * ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller + * that ORB is (or will soon) push data into the synchronizer FIFO (i.e. wake is high). + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +GnbOrbDynamicWake ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + ex495_STRUCT ex495 ; + + GnbLibPciIndirectRead ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + 0x2c | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessWidth32, + &ex495.Value, + StdHeader + ); + + // Enable Dynamic wake + // Wake Hysteresis timer value. Specifies the number of SMU pulses to count. + if (GnbBuildOptions.CfgOrbDynWakeEnable) { + ex495.Field.ex495_1 = 1; + } else { + ex495.Field.ex495_1 = 0; + } + ex495.Field.ex495_3 = 0x64; + + IDS_OPTION_HOOK (IDS_GNB_ORBDYNAMIC_WAKE, &ex495, StdHeader); + + GnbLibPciIndirectWrite ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + 0x2c | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + &ex495.Value, + StdHeader + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Lock NB registers + * + * + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +GnbLock ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbLibPciIndirectWriteField ( + NbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, + D0F0x64_x00_HwInitWrLock_OFFSET, + D0F0x64_x00_HwInitWrLock_WIDTH, + 0x1, + TRUE, + StdHeader + ); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * UnitID Clumping + * + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +GnbClumpUnitID ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 2, 0, 0), AccessWidth32, &Value, StdHeader); + if (Value != 0xFFFFFFFF) { + GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 3, 0, 0), AccessWidth32, &Value, StdHeader); + if (Value == 0xFFFFFFFF) { + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + 0x3a | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + 0xFFFFFFFF, + 1 << 3 /* D0F0x98_x3A_ClumpingEn_OFFSET*/, + StdHeader + ); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the index of highest SCLK VID + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID index + */ +UINT8 +GnbLocateHighestVidIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxVid; + UINT8 MaxVidIndex; + UINTN Index; + PP_FUSE_ARRAY *PpFuseArray; + + PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray == NULL) { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); + return 0; + } + + MaxVidIndex = 0; + MaxVid = 0xff; + for (Index = 0; Index < 4; Index++) { + if (PpFuseArray->SclkVid[Index] != 0 && PpFuseArray->SclkVid[Index] < MaxVid) { + MaxVid = PpFuseArray->SclkVid[Index]; + MaxVidIndex = (UINT8) Index; + } + } + ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0); + return MaxVidIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the index of lowest SCLK VID + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID index + */ +UINT8 +GnbLocateLowestVidIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MinVidIndex; + UINTN Index; + PP_FUSE_ARRAY *PpFuseArray; + + PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray == NULL) { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); + return 0; + } + + MinVidIndex = 0; + + for (Index = 0; Index < 4; Index++) { + if (PpFuseArray->SclkVid[Index] > PpFuseArray->SclkVid[MinVidIndex]) { + MinVidIndex = (UINT8) Index; + } + } + ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0); + return MinVidIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the highest SCLK VID (high voltage) + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID + */ +UINT8 +GnbLocateHighestVidCode ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxVidIndex; + PP_FUSE_ARRAY *PpFuseArray; + + PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + + MaxVidIndex = GnbLocateHighestVidIndex (StdHeader); + ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0); + return PpFuseArray->SclkVid[MaxVidIndex]; + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the lowest SCLK VID (low voltage) + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID + */ +UINT8 +GnbLocateLowestVidCode ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MinVidIndex; + PP_FUSE_ARRAY *PpFuseArray; + + PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + MinVidIndex = GnbLocateLowestVidIndex (StdHeader); + ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0); + return PpFuseArray->SclkVid[MinVidIndex]; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h new file mode 100644 index 0000000000..948ee4c404 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h @@ -0,0 +1,126 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBNBINITLIBV1_H_ +#define _GNBNBINITLIBV1_H_ + + +AGESA_STATUS +GnbSetTom ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLpcDmaDeadlockPrevention ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbOrbDynamicWake ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLock ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbClumpUnitID ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateHighestVidIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +UINT8 +GnbLocateLowestVidIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateHighestVidCode ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateLowestVidCode ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c new file mode 100644 index 0000000000..faf72986d6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c @@ -0,0 +1,620 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 64352 $ @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbRegistersTN.h" +#include "heapManager.h" +#include "GnbFamServices.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define SMC_RAM_START_ADDR 0x10000ul + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + GNB_TOPOLOGY_INFO *TopologyInfo; +} GNB_TOPOLOGY_INFO_DATA; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GnbSmuServiceRequestV4S3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID *Context + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Check a PCIE device to see if it supports phantom functions + * + * @param[in] Device Device pci address + * @param[in] StdHeader Standard configuration header + * @return TRUE Current device supports phantom functions + */ +STATIC BOOLEAN +GnbCheckPhantomFuncSupport ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + UINT32 Value; + Value = 0; + + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 4), AccessWidth32, &Value, StdHeader); + } + return ((Value & (BIT3 | BIT4)) != 0) ? TRUE : FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status + */ + +SCAN_STATUS +STATIC +GnbTopologyInfoScanCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + GNB_TOPOLOGY_INFO_DATA *GnbTopologyInfo; + PCIE_DEVICE_TYPE DeviceType; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " GnbIommuInfoScanCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + GnbTopologyInfo = (GNB_TOPOLOGY_INFO_DATA *)ScanData; + ScanStatus = SCAN_SUCCESS; + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + GnbLibPciScanSecondaryBus (Device, &GnbTopologyInfo->ScanData); + break; + case PcieDeviceUpstreamPort: + GnbLibPciScanSecondaryBus (Device, &GnbTopologyInfo->ScanData); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDevicePcieToPcix: + GnbTopologyInfo->TopologyInfo->PcieToPciexBridge = TRUE; + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + if (GnbCheckPhantomFuncSupport (Device, ScanData->StdHeader)) { + GnbTopologyInfo->TopologyInfo->PhantomFunction = TRUE; + } + ScanStatus = SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + default: + break; + } + return ScanStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get IOMMU topology info + * + * + * + * @param[in] StartPciAddress Start PCI address + * @param[in] EndPciAddress End PCI address + * @param[in] TopologyInfo Topology info structure + * @param[in] StdHeader Standard Configuration Header + */ + +AGESA_STATUS +GnbGetTopologyInfoV4 ( + IN PCI_ADDR StartPciAddress, + IN PCI_ADDR EndPciAddress, + OUT GNB_TOPOLOGY_INFO *TopologyInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GNB_TOPOLOGY_INFO_DATA GnbTopologyInfo; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbGetTopologyInfoV4 Enter\n"); + GnbTopologyInfo.ScanData.GnbScanCallback = GnbTopologyInfoScanCallback; + GnbTopologyInfo.ScanData.StdHeader = StdHeader; + GnbTopologyInfo.TopologyInfo = TopologyInfo; + GnbLibPciScan (StartPciAddress, EndPciAddress, &GnbTopologyInfo.ScanData); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbGetTopologyInfoV4 Exit\n"); + return AGESA_SUCCESS; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU service request + * + * + * @param[in] GnbPciAddress GNB PCI address + * @param[in] RequestId Request ID + * @param[in] AccessFlags See GNB_ACCESS_FLAGS_* definitions + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbSmuServiceRequestV4 ( + IN PCI_ADDR GnbPciAddress, + IN UINT8 RequestId, + IN UINT32 AccessFlags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_xE0003004_STRUCT D0F0xBC_xE0003004; + D0F0xBC_xE0003000_STRUCT D0F0xBC_xE0003000; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV4 Enter\n"); + IDS_HDT_CONSOLE (NB_MISC, " Service Request %d\n", RequestId); + + if ((AccessFlags & GNB_REG_ACC_FLAG_S3SAVE) != 0) { + SMU_MSG_CONTEXT SmuMsgContext; + SmuMsgContext.GnbPciAddress.AddressValue = GnbPciAddress.AddressValue; + SmuMsgContext.RequestId = RequestId; + S3_SAVE_DISPATCH (StdHeader, GnbSmuServiceRequestV4S3Script_ID, sizeof (SmuMsgContext), &SmuMsgContext); + } + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader); + } while (D0F0xBC_xE0003004.Field.IntDone == 0x0); + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003000_ADDRESS, AccessWidth32, &D0F0xBC_xE0003000.Value, StdHeader); + D0F0xBC_xE0003000.Field.IntToggle = ~D0F0xBC_xE0003000.Field.IntToggle; + D0F0xBC_xE0003000.Field.ServiceIndex = RequestId; + GnbLibPciIndirectWrite (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003000_ADDRESS, AccessWidth32, &D0F0xBC_xE0003000.Value, StdHeader); + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader); + } while (D0F0xBC_xE0003004.Field.IntAck == 0x0); + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader); + } while (D0F0xBC_xE0003004.Field.IntDone == 0x0); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV4 Exit\n"); +} +/*----------------------------------------------------------------------------------------*/ +/** + * SMU service request for S3 script + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context length + * @param[in] Context Pointer to Context + */ + +VOID +GnbSmuServiceRequestV4S3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID *Context + ) +{ + SMU_MSG_CONTEXT *SmuMsgContext; + SmuMsgContext = (SMU_MSG_CONTEXT *) Context; + GnbSmuServiceRequestV4 (SmuMsgContext->GnbPciAddress, SmuMsgContext->RequestId, 0, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU firmware download + * + * + * @param[in] GnbPciAddress GNB Pci Address + * @param[in] Firmware Pointer tp firmware + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +GnbSmuFirmwareLoadV4 ( + IN PCI_ADDR GnbPciAddress, + IN FIRMWARE_HEADER_V4 *Firmware, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + UINT32 Index; + D0F0xBC_xE00030A4_STRUCT D0F0xBC_xE00030A4; + D0F0xBC_xE0000004_STRUCT D0F0xBC_xE0000004; + D0F0xBC_xE0003088_STRUCT D0F0xBC_xE0003088; + ex1005_STRUCT ex1005 ; + D0F0xBC_x1F380_STRUCT D0F0xBC_x1F380; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV4 Enter\n"); + IDS_HDT_CONSOLE (NB_MISC, " Firmware version 0x%x\n", Firmware->Version); + // Step 2, 10, make sure Rom firmware sequance is done + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0000004_ADDRESS, AccessWidth32, &D0F0xBC_xE0000004.Value, StdHeader); + } while (D0F0xBC_xE0000004.Field.boot_seq_done == 0); + // Step 1, check if firmware running in protected mode + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE00030A4_ADDRESS, AccessWidth32, &D0F0xBC_xE00030A4.Value, StdHeader); + if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) { + // Step3, Clear firmware interrupt flags + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + D0F0xBC_x1F380_ADDRESS, + AccessWidth32, + 0x0, + 0x0, + StdHeader + ); + } + //Step 4, 11, Assert LM32 reset + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x80000000 , + AccessWidth32, + (UINT32) ~(0x1 ), + 1 << 0 , + StdHeader + ); + // Step5, 12, Load firmware + for (Index = 0; Index < (Firmware->FirmwareLength + Firmware->HeaderLength); Index++) { + GnbLibPciIndirectWrite (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, SMC_RAM_START_ADDR + (Index * 4), AccessWidth32, &((UINT32 *) Firmware)[Index], StdHeader); + } + if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) { + //Step 6, Write jmp to RAM firmware + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x0, + AccessWidth32, + 0x0, + 0xE0000000 + ((SMC_RAM_START_ADDR + Firmware->HeaderLength * 4) >> 2), + StdHeader + ); + } else { + //Step 13, Clear autentification done + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + D0F0xBC_xE0003088_ADDRESS, + AccessWidth32, + 0x0, + 0x0, + StdHeader + ); + } + // Step 7, 14 Enable LM32 clock + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x80000004 , + AccessWidth32, + (UINT32) ~(0x1 ), + 0 << 0 , + StdHeader + ); + + //Step 8, 15, Deassert LM32 reset + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x80000000 , + AccessWidth32, + (UINT32) ~(0x1 ), + 0 << 0 , + StdHeader + ); + + if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 1) { + IDS_HDT_CONSOLE (NB_MISC, " Protected mode: poll init autehtication vector\n"); + // Step 16, Wait for rom firmware init autehtication vector + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, 0x80010000 , AccessWidth32, &ex1005.Value, StdHeader); + } while (ex1005.Value != 0x400); + // Call Authentication service + GnbSmuServiceRequestV4 (GnbPciAddress, SMC_MSG_FIRMWARE_AUTH, 0, StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Protected mode: poll init autehtication done\n"); + // Wait for autehtication done + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003088_ADDRESS, AccessWidth32, &D0F0xBC_xE0003088.Value, StdHeader); + } while (D0F0xBC_xE0003088.Field.SmuAuthDone == 0x0); + //Step 17, Check Authentication results + if (D0F0xBC_xE0003088.Field.SmuAuthPass == 0) { + IDS_HDT_CONSOLE (NB_MISC, " ERROR!!!Autehtication fail!!!\n"); + ASSERT (FALSE); + return AGESA_FATAL; + } + // Step 18, Clear firmware interrupt enable flag + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + D0F0xBC_x1F380_ADDRESS, + AccessWidth32, + 0x0, + 0x0, + StdHeader + ); + //Step 19, Assert LM32 reset + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x80000000 , + AccessWidth32, + (UINT32) ~(0x1 ), + 1 << 0 , + StdHeader + ); + //Step 20, Deassert LM32 reset + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x80000000 , + AccessWidth32, + (UINT32) ~(0x1 ), + 0 << 0 , + StdHeader + ); + } +//Step 9, 21 Wait firmware to initialize + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_x1F380_ADDRESS, AccessWidth32, &D0F0xBC_x1F380.Value, StdHeader); + } while (D0F0xBC_x1F380.Field.InterruptsEnabled == 0); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV4 Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get IOMMU PCI address + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard configuration header + */ + +PCI_ADDR +GnbGetIommuPciAddressV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR GnbIommuPciAddress; + GnbIommuPciAddress = GnbGetHostPciAddress (GnbHandle); + GnbIommuPciAddress.Address.Function = 0x2; + return GnbIommuPciAddress; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * UnitID Clumping + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbClumpUnitIdV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + PCIe_ENGINE_CONFIG *EngineList; + UINT32 Value; + + Value = 0; + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_PCIE_ENGINE, &GnbHandle->Header); + while (EngineList != NULL) { + if (EngineList->Type.Port.NumberOfUnitId != 0) { + if (!PcieConfigIsActivePcieEngine (EngineList)) { + Value |= (((1 << EngineList->Type.Port.NumberOfUnitId) - 1) << EngineList->Type.Port.UnitId); + } else { + if (EngineList->Type.Port.NumberOfUnitId > 1) { + Value |= (((1 << (EngineList->Type.Port.NumberOfUnitId - 1)) - 1) << (EngineList->Type.Port.UnitId + 1)); + } + } + } + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB); + } + // Set GNB + GnbLibPciIndirectRMW ( + GnbHandle->Address.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x3A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + (UINT32) ~Value, + Value, + StdHeader + ); + //Set UNB + GnbLibPciRMW ( + MAKE_SBDFO (0, 0, GnbHandle->NodeId + 0x18, 0, D18F0x110_ADDRESS + GnbHandle->LinkId * 4), + AccessS3SaveWidth32, + (UINT32) ~Value, + Value, + StdHeader + ); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Config GNB to prevent LPC deadlock scenario + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLpcDmaDeadlockPreventionV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_ENGINE_CONFIG *EngineList; + + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &GnbHandle->Header); + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &GnbHandle->Header); + while (EngineList != NULL) { + if (PcieConfigIsPcieEngine (EngineList) && PcieConfigIsSbPcieEngine (EngineList)) { + PcieRegisterRMW ( + PcieConfigGetParentWrapper (EngineList), + CORE_SPACE (EngineList->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS), + D0F0xE4_CORE_0010_UmiNpMemWrite_MASK, + 1 << D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET, + TRUE, + Pcie + ); + //Enable special NP memory write protocol in ORB + GnbLibPciIndirectRMW ( + GnbHandle->Address.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x06_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + 0xFFFFFFFF, + 1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET, + StdHeader + ); + break; + } + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable IOMMU base address. (MMIO space ) + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +GnbEnableIommuMmioV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + UINT16 CapabilityOffset; + UINT64 BaseAddress; + UINT32 Value; + PCI_ADDR GnbIommuPciAddress; + + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Enter\n"); + + if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { + GnbIommuPciAddress = GnbGetIommuPciAddressV4 (GnbHandle, StdHeader); + CapabilityOffset = GnbLibFindPciCapability (GnbIommuPciAddress.AddressValue, IOMMU_CAP_ID, StdHeader); + + GnbLibPciRead (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessWidth32, &Value, StdHeader); + BaseAddress = (UINT64) Value << 32; + GnbLibPciRead (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessWidth32, &Value, StdHeader); + BaseAddress |= Value; + + if ((BaseAddress & 0xfffffffffffffffe) != 0x0) { + IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %x for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); + GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessS3SaveWidth32, 0xFFFFFFFF, 0x0, StdHeader); + GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessS3SaveWidth32, 0xFFFFFFFE, 0x1, StdHeader); + } else { + ASSERT (FALSE); + Status = AGESA_ERROR; + } + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Exit\n"); + return Status; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h new file mode 100644 index 0000000000..95d97df935 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h @@ -0,0 +1,149 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 64352 $ @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBNBINITLIBV4_H_ +#define _GNBNBINITLIBV4_H_ + +#pragma pack (push, 1) + +/// Firmware header +typedef struct { + UINT32 Version; ///< Version + UINT32 HeaderLength; ///< Header length + UINT32 FirmwareLength; ///< Firmware length + UINT32 EntryPoint; ///< Entry point + UINT32 MessageDigest[5]; ///< Message digest + UINT32 Reserved_A[3]; ///< Reserved + UINT32 CurrentSystemState; ///< Current system state + UINT32 DpmCacHistory; ///< DpmCac History + UINT32 DpmResidencyCounters; ///< DPM recidency counters + UINT32 Reserved_B[16]; ///< Reserved + UINT32 Reserved_C[16]; ///< Reserved + UINT32 Reserved_D[16]; ///< Reserved + UINT32 HeaderEnd; ///< Header end signature +} FIRMWARE_HEADER_V4; + +/// SMU service request contect +typedef struct { + PCI_ADDR GnbPciAddress; ///< PCIe address of GNB + UINT8 RequestId; ///< Request/Msg ID +} SMU_MSG_CONTEXT; + +#pragma pack (pop) + +AGESA_STATUS +GnbGetTopologyInfoV4 ( + IN PCI_ADDR StartPciAddress, + IN PCI_ADDR EndPciAddress, + OUT GNB_TOPOLOGY_INFO *TopologyInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbSmuServiceRequestV4 ( + IN PCI_ADDR GnbPciAddress, + IN UINT8 RequestId, + IN UINT32 AccessFlags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbSmuFirmwareLoadV4 ( + IN PCI_ADDR GnbPciAddress, + IN FIRMWARE_HEADER_V4 *Firmware, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +PCI_ADDR +GnbGetIommuPciAddressV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbClumpUnitIdV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLpcDmaDeadlockPreventionV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbEnableIommuMmioV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c new file mode 100644 index 0000000000..1b3742da7c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c @@ -0,0 +1,578 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "cpuLateInit.h" +#include "cpuRegisters.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbNbInitLibV1.h" +#include "GnbRegistersLN.h" +#include "OptionGnb.h" +#include "PcieAlib.h" +#include "GnbFuseTable.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern F_ALIB_GET *AlibGetBaseTable; +extern F_ALIB_UPDATE *AlibDispatchTable[]; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieAlibUpdatePcieMmioInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieAlibUpdateVoltageInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieAlibUpdatePcieInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +PcieAlibSetPortMaxSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +STATIC +PcieAlibSetPortOverrideSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +STATIC +PcieAlibSetPortInfoCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieAlibBuildAcpiTable ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **AlibSsdtPtr + ); + +VOID +STATIC +PcieAlibSetSclkVid ( + IN OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Create ACPI ALIB SSDT table + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PcieAlibFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_LATE_PARAMS *LateParamsPtr; + LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader; + return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build ALIB ACPI table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @param[in,out] AlibSsdtPtr Pointer to pointer to ALIB SSDT table + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +PcieAlibBuildAcpiTable ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **AlibSsdtPtr + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + UINTN Index; + VOID *AlibSsdtBuffer; + VOID *AlibSsdtTable; + UINTN AlibSsdtlength; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Enter\n"); + AgesaStatus = AGESA_SUCCESS; + AlibSsdtTable = AlibGetBaseTable (StdHeader); + AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtTable)->TableLength; + if (*AlibSsdtPtr == NULL) { + AlibSsdtBuffer = GnbAllocateHeapBuffer ( + AMD_ACPI_ALIB_BUFFER_HANDLE, + AlibSsdtlength, + StdHeader + ); + ASSERT (AlibSsdtBuffer != NULL); + if (AlibSsdtBuffer == NULL) { + return AGESA_ERROR; + } + *AlibSsdtPtr = AlibSsdtBuffer; + } else { + AlibSsdtBuffer = *AlibSsdtPtr; + } + // Copy template to buffer + LibAmdMemCopy (AlibSsdtBuffer, AlibSsdtTable, AlibSsdtlength, StdHeader); + // Disaptch fucntion form table + Index = 0; + while (AlibDispatchTable[Index] != NULL) { + Status = AlibDispatchTable[Index] (AlibSsdtBuffer, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + Index++; + } + if (AgesaStatus != AGESA_SUCCESS) { + //Shrink table length to size of the header + ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER); + } + ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Update MMIO info + * + * + * + * + * @param[in] AlibSsdtBuffer Ponter to SSDT table + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +PcieAlibUpdatePcieMmioInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 AmlObjName; + UINT32 AlibSsdtlength; + VOID *AmlObjPtr; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieMmioInfo Enter\n"); + Status = AGESA_SUCCESS; + AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength; + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '1'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + UINT64 LocalMsrRegister; + LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); + if ((LocalMsrRegister & BIT0) != 0 && (LocalMsrRegister & 0xFFFFFFFF00000000) == 0) { + *(UINT32*)((UINT8*) AmlObjPtr + 5) = (UINT32)(LocalMsrRegister & 0xFFFFF00000); + } else { + Status = AGESA_FATAL; + } + } else { + Status = AGESA_FATAL; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieMmioInfo Exit\n"); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Update MMIO info + * + * + * + * + * @param[in] AlibSsdtBuffer Ponter to SSDT table + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +PcieAlibUpdateVoltageInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 AmlObjName; + UINT32 AlibSsdtlength; + VOID *AmlObjPtr; + UINT8 BootUpVidIndex; + UINT8 Gen1VidIndex; + PP_FUSE_ARRAY *PpFuseArray; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageInfo Enter\n"); + Status = AGESA_SUCCESS; + AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength; + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray != NULL) { + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '3'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*) AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid; + } else { + Status = AGESA_FATAL; + } + } else { + Status = AGESA_FATAL; + } + + Gen1VidIndex = GnbLocateLowestVidIndex (StdHeader); + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '4'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*) AmlObjPtr + 5) = Gen1VidIndex; + } else { + Status = AGESA_FATAL; + } + + BootUpVidIndex = GnbLocateHighestVidIndex (StdHeader); + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '5'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*) AmlObjPtr + 5) = BootUpVidIndex; + } else { + Status = AGESA_FATAL; + } + + AmlObjName = STRING_TO_UINT32 ('A', 'D', '1', '0'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieAlibSetSclkVid ((UINT8*) ((UINT8*)AmlObjPtr + 7), StdHeader); + } else { + Status = AGESA_FATAL; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageInfo Exit\n"); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Update PCIe info + * + * + * + * + * @param[in] AlibSsdtBuffer Ponter to SSDT table + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +PcieAlibUpdatePcieInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_PLATFORM_CONFIG *Pcie; + UINT32 AmlObjName; + UINT32 AlibSsdtlength; + VOID *AmlObjPtr; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieInfo Enter\n"); + Status = AGESA_SUCCESS; + AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength; + if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '2'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*) AmlObjPtr + 5) = Pcie->PsppPolicy; + } else { + Status = AGESA_FATAL; + } + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '6'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAlibSetPortMaxSpeedCallback, + (UINT8*)((UINT8*) AmlObjPtr + 7), + Pcie + ); + } else { + Status = AGESA_FATAL; + } + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '8'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAlibSetPortOverrideSpeedCallback, + (UINT8*)((UINT8*) AmlObjPtr + 7), + Pcie + ); + } else { + Status = AGESA_FATAL; + } + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '7'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAlibSetPortInfoCallback, + (UINT8*)((UINT8*) AmlObjPtr + 4), + Pcie + ); + } else { + Status = AGESA_FATAL; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieInfo Exit\n"); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init max port speed capability + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAlibSetPortMaxSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *PsppMaxPortSpeedPackage; + PsppMaxPortSpeedPackage = (UINT8*) Buffer; + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init max port speed capability + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAlibSetPortOverrideSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *PsppOverridePortSpeedPackage; + PsppOverridePortSpeedPackage = (UINT8*) Buffer; + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = Engine->Type.Port.PortData.MiscControls.LinkSafeMode; + } + if (Engine->Type.Port.PortData.LinkHotplug == HotplugBasic && !PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = PcieGen1; + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init port info + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAlibSetPortInfoCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + ALIB_PORT_INFO_PACKAGE *PortInfoPackage; + UINT8 PortIndex; + PortInfoPackage = (ALIB_PORT_INFO_PACKAGE*) Buffer; + PortIndex = (UINT8) Engine->Type.Port.Address.Address.Device - 2; + PortInfoPackage->PortInfo[PortIndex].StartPhyLane = (UINT8) Engine->EngineData.StartLane; + PortInfoPackage->PortInfo[PortIndex].EndPhyLane = (UINT8) Engine->EngineData.EndLane; + PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane; + PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane; + PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId; + PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieConfigGetParentWrapper (Engine)->WrapId); + PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug; + PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); + PortInfoPackage->PortInfo[PortIndex].ClkPmSupport = Engine->Type.Port.PortData.MiscControls.ClkPmSupport; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init port info + * + * + * + * + * @param[in, out] Buffer Asl buffer + * @param[in] StdHeader Standard configuration header + * + */ + +VOID +STATIC +PcieAlibSetSclkVid ( + IN OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *SclkVid; + PP_FUSE_ARRAY *PpFuseArray; + UINT8 Index; + + SclkVid = (UINT8*) Buffer; + PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray == NULL) { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); + return; + } + + for (Index = 0; Index < 4; Index++) { + SclkVid[Index * 2 + 1] = PpFuseArray->SclkVid[Index]; + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h new file mode 100644 index 0000000000..63a06e1ab2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h @@ -0,0 +1,109 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEALIB_H_ +#define _PCIEALIB_H_ + +#pragma pack (push, 1) +///Port info asl buffer +typedef struct { + UINT8 BufferOp; ///< Opcode + UINT8 PkgLength; ///< Package length + UINT8 BufferSize; ///< Buffer size + UINT8 ByteList; ///< Byte lisy + UINT8 StartPhyLane; ///< Port Start PHY lane + UINT8 EndPhyLane; ///< Port End PHY lane + UINT8 StartCoreLane; ///< Port Start Core lane + UINT8 EndCoreLane; ///< Port End Core lane + UINT8 PortId; ///< Port ID + UINT16 WrapperId; ///< Wrapper ID + UINT8 LinkHotplug; ///< Link hotplug type + UINT8 MaxSpeedCap; ///< Max port speed capability + UINT8 ClkPmSupport; ///< ClkPmSupport +} ALIB_PORT_INFO_BUFFER; +///Ports info asl package +typedef struct { + UINT8 PackageOp; ///< Opcode + UINT8 PkgLength; ///< Package length + UINT8 NumElements; ///< number of elements + UINT8 PackageElementList; ///< package element list + ALIB_PORT_INFO_BUFFER PortInfo[7]; ///< Array of port info buffers +} ALIB_PORT_INFO_PACKAGE; + +#pragma pack (pop) + +AGESA_STATUS +PcieAlibFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl new file mode 100644 index 0000000000..5c53c6b870 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl @@ -0,0 +1,136 @@ +/** + * @file + * + * ALIB PSPP config + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEALIBCONFIG_H_ +#define _PCIEALIBCONFIG_H_ + +//#define PCIE_PHY_LANE_POWER_GATE_SUPPORT +// #define PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK + +#define DEF_OFFSET_START_CORE_LANE 2 +#define DEF_OFFSET_END_CORE_LANE 3 +#define DEF_OFFSET_START_PHY_LANE 0 +#define DEF_OFFSET_END_PHY_LANE 1 +#define DEF_OFFSET_PORT_ID 4 +#define DEF_OFFSET_WRAPPER_ID 5 +#define DEF_OFFSET_LINK_HOTPLUG 7 +#define DEF_OFFSET_GEN2_CAP 8 +#define DEF_OFFSET_CLK_PM_SUPPORT 9 + +#define DEF_BASIC_HOTPLUG 1 + +#define DEF_PSPP_POLICY_START 1 +#define DEF_PSPP_POLICY_STOP 0 +#define DEF_PSPP_POLICY_PERFORMANCE 1 +#define DEF_PSPP_POLICY_BALANCEHIGH 2 +#define DEF_PSPP_POLICY_BALANCELOW 3 +#define DEF_PSPP_POLICY_POWERSAVING 4 +#define DEF_PSPP_STATE_AC 0 +#define DEF_PSPP_STATE_DC 1 + +#define DEF_TRAINING_STATE_COMPLETE 0 +#define DEF_TRAINING_STATE_DETECT_PRESENCE 1 +#define DEF_TRAINING_STATE_PRESENCE_DETECTED 2 +#define DEF_TRAINING_GEN2_WORKAROUND 3 +#define DEF_TRAINING_STATE_NOT_PRESENT 4 +#define DEF_TRAINING_DEVICE_PRESENT 5 +#define DEF_TRAINING_STATE_RELEASE_TRAINING 6 +#define DEF_TRAINING_STATE_REQUEST_RESET 7 +#define DEF_TRAINING_STATE_EXIT 8 + +#define DEF_LINK_SPEED_GEN1 1 +#define DEF_LINK_SPEED_GEN2 2 + +#define DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT 0 +#define DEF_HOTPLUG_STATUS_DEVICE_PRESENT 1 + +#define DEF_PORT_NOT_ALLOCATED 0 +#define DEF_PORT_ALLOCATED 1 + +#define DEF_PCIE_LANE_POWERON 1 +#define DEF_PCIE_LANE_POWEROFF 0 +#define DEF_PCIE_LANE_POWEROFFUNUSED 2 + +#define DEF_SCARTCH_PSPP_START_OFFSET 0 +#define DEF_SCARTCH_PSPP_POLICY_OFFSET 1 +#define DEF_SCARTCH_PSPP_ACDC_OFFSET 5 +#define DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET 6 +#define DEF_SCARTCH_PSPP_REQ_OFFSET 16 + +#define DEF_LINKWIDTH_ACTIVE 0 +#define DEF_LINKWIDTH_MAX_PHY 1 + +#define DEF_SB_PORT_INDEX 6 + +#define TRUE 1 +#define FALSE 0 + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl new file mode 100644 index 0000000000..bc1f70db88 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl @@ -0,0 +1,111 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + + /*----------------------------------------------------------------------------------------*/ + /** + * Master control method + * + * Arg0 - Function ID + * Arg1 - Function specific data buffer + */ + Method (ALIB, 2, NotSerialized) { + If (Lequal (Arg0, 0x1)) { + return (procPsppReportAcDsState (Arg1)) + } + If (LEqual (Arg0, 0x2)) { + return (procPsppPerformanceRequest (Arg1)) + } + If (LEqual (Arg0, 0x3)) { + return (procPsppControl (Arg1)) + } + If (LEqual (Arg0, 0x4)) { + return (procPcieSetBusWidth (Arg1)) + } + If (LEqual (Arg0, 0x5)) { + return (procAlibInit ()) + } + If (LEqual (Arg0, 0x6)) { + return (procPciePortHotplug (Arg1)) + } + return (0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Alib Init + * + * + */ + Method (procAlibInit, 0, Serialized) { + + return (0) + } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl new file mode 100644 index 0000000000..e8820cf502 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl @@ -0,0 +1,73 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + Name (varStringBuffer, Buffer (256) {}) + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl new file mode 100644 index 0000000000..951193a57b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl @@ -0,0 +1,787 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 65976 $ @e \$Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + External(\_SB.ALIC, MethodObj) + External(P80H) + + Name (varStartPhyLane, 0) + Name (varEndPhyLane, 0) + Name (varStartCoreLane, 0) + Name (varEndCoreLane, 0) + Name (varWrapperId, 0) + Name (varPortId, 0) + Name (varMaxPhyLinkWidth, 0) + + Name (varNormalizeLinkWidthBuffer, Buffer () {1, 2, 4, 4, 8, 8, 8, 8, 16, 16, 16, 16, 16, 16, 16, 16}) + /*----------------------------------------------------------------------------------------*/ + /** + * Set PCIe Bus Width + * + * Arg0 - Data Buffer + */ + Method (procPcieSetBusWidth, 1, NotSerialized) { + Store ("procPcieSetBusWidth Enter", Debug) + + Name (varClientBus, 0) + Name (varArgBusWidth, 0) + Store (0, varPortIndex) + Store (Buffer (10) {}, Local7) + + //ClientId: WORD + //Bits 2-0: Function number. + //Bits 7-3: Device number. + //Bits 15-8: Bus number. + Store (DerefOf (Index (Arg0, 0x3)), varClientBus) + Store (DerefOf (Index (Arg0, 0x4)), varArgBusWidth) + Store (Concatenate (" Client Bus : ", ToHexString (varClientBus), varStringBuffer), Debug) + Store (Concatenate (" Arg Bus Width : ", ToHexString (varArgBusWidth), varStringBuffer), Debug) + + Store (3, Index (Local7, 0x0)) // Return Buffer Length + Store (0, Index (Local7, 0x1)) // Return Buffer Length + Store (varArgBusWidth, Index (Local7, 0x2)) // Return BusWidth + // disable interface + return (Local7) + + //deternime correct lane bitmap (check for reversal) gate/ungate unused lanes + + // determine port index base on "Client ID" + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { + Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) + And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number + And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number + if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { + break + } + } + Increment (varPortIndex) + } + if (LGreater (varPortIndex, varMaxPortIndexNumber)) { + Store ("procPcieSetBusWidth Exit -- over max port index", Debug) + return (Local7) + } + + Store (Concatenate (" Pcie Set BusWidth for port index : ", ToHexString (varPortIndex), varStringBuffer), Debug) + + // Normalize link width (Num Lanes) to correct value x1, x2.x4,x8,x16, + // make sure that number of lanes requested to be powered on less or equal mx port link width + if (LLessEqual (procPcieGetLinkWidth (varPortIndex, DEF_LINKWIDTH_MAX_PHY), varArgBusWidth)) { + // Active link equal max link width, nothing needs to be done + Store ("procPcieSetBusWidth Exit -- over max lanes supported", Debug) + return (Local7) + } + Store (DeRefOf (Index (varNormalizeLinkWidthBuffer, varArgBusWidth)), Local1) + + + // call procPcieLaneControl to power on all lanes (Arg0 - port index , Arg1 - 1, Arg2 = 0) + procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWERON, 0) + + // call procPcieLaneControl power off unused lanes (Arg0 - port index, Arg1 - 1, Arg2 = Link width) + procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWEROFFUNUSED, Local1) + +#ifdef PHY_SPEED_REPORT_SUPPORT + procReportPhySpeedCap () +#endif + Store (Local1, Index (Local7, 0x2)) // Return BusWidth + + Store ("procPcieSetBusWidth Exit", Debug) + return (Local7) + } + + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe port hotplug + * + * Arg0 - Data Buffer + * Retval - Return buffer + */ + Method (procPciePortHotplug, 1, Serialized) { + Store ("PciePortHotplug Enter", Debug) + Store (DerefOf (Index (Arg0, 4)), varHotplugStateLocal0) + Store (DerefOf (Index (Arg0, 2)), varPortBdfLocal1) + + Subtract (ShiftRight (varPortBdfLocal1, 3), 2, varPortIndexLocal4) + if (LEqual(varHotplugStateLocal0, 1)) { + // Enable port + Store (DEF_TRAINING_STATE_RELEASE_TRAINING, Local2) + } else { + // Disable port + Store (DEF_TRAINING_STATE_NOT_PRESENT, Local2) + } + + //Disable ASPM + Store (procPciDwordRead (varPortBdfLocal1, 0x68), Local3) + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), 0x00) + + Store (procPciePortTraining (varPortIndexLocal4, Local2), varHotplugStateLocal0) + + //Restore ASPM + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), And (Local3, 0x3)) + +#ifdef PHY_SPEED_REPORT_SUPPORT + procReportPhySpeedCap () +#endif + + Store (Buffer (10) {}, Local7) + CreateWordField (Local7, 0x0, varReturnBufferLength) + CreateByteField (Local7, 0x2, varReturnStatus) + CreateByteField (Local7, 0x3, varReturnDeviceStatus) + Store (0x4, varReturnBufferLength) + Store (0x0, varReturnStatus) + Store (varHotplugStateLocal0, varReturnDeviceStatus) + Store ("PciePortHotplug Exit", Debug) + return (Local7) + } + + Name (varSpeedRequest, Buffer (10) {0,0,0,0,0,0,0,0,0,0}) + + /*----------------------------------------------------------------------------------------*/ + /** + * Train PCIe port + * + * + * Arg0 - Port Index + * Arg1 - Initial state + */ + Method (procPciePortTraining, 2, Serialized) { + Store ("PciePortTraining Enter", Debug) + Store (DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT, varResultLocal4) + Store (procPcieGetPortInfo (Arg0), Local7) + // Check if port supports basic hotplug + Store (DerefOf (Index (Local7, DEF_OFFSET_LINK_HOTPLUG)), varTempLocal1) + if (LNotEqual (varTempLocal1, DEF_BASIC_HOTPLUG)) { + Store (" No action.[Hotplug type]", Debug) + Store ("procPciePortTraining Exit", Debug) + return (varResultLocal4) + } + Store (Arg1, varStateLocal2) + while (LNotEqual (varStateLocal2, DEF_TRAINING_STATE_EXIT)) { + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_RELEASE_TRAINING)) { + Store (" State: Release training", Debug) + // Remove link speed override + Store (0, Index (varOverrideLinkSpeed, Arg0)) + // Enable link width upconfigure + procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x0000) + if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + // Request Max link speed for hotplug by going to AC state + Store (0, varPsppAcDcOverride) + procApplyPsppState () + } else { + procPcieSetLinkSpeed (Arg0, DeRefOf (Index (varMaxLinkSpeed, Arg0))) + } + // Power on/enable port lanes + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWERON, 0) + // Release training + procPcieTrainingControl (Arg0, 0) + // Move to next state to check presence detection + Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) + // Initialize retry count + Store(0, varCountLocal3) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_DETECT_PRESENCE)) { + Store (" State: Detect presence", Debug) + And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, varTempLocal1) + if (LGreater (varTempLocal1, 0x4)) { + // device connection detected move to next state + Store (DEF_TRAINING_STATE_PRESENCE_DETECTED, varStateLocal2) + // reset retry counter + Store(0, varCountLocal3) + continue + } + if (LLess (varCountLocal3, 80)) { + Sleep (1) + Increment (varCountLocal3) + } else { + // detection time expired move to device not present state + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) + } + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_PRESENCE_DETECTED)) { + Store (" State: Device detected", Debug) + Store (procPciePortIndirectRegisterRead (Arg0, 0xa5), varTempLocal1) + And (varTempLocal1, 0x3f, varTempLocal1) + if (LAnd (LGreaterEqual (varTempLocal1, 0x10), LLessEqual (varTempLocal1, 0x13))) { + Store (DEF_TRAINING_DEVICE_PRESENT, varStateLocal2) + continue + } + if (LLess (varCountLocal3, 80)) { + Sleep (1) + Increment (varCountLocal3) + continue + } + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) + if (LEqual (DeRefOf (Index (varOverrideLinkSpeed, Arg0)), DEF_LINK_SPEED_GEN1)) { + // GEN2 workaround already applied but device not trained successfully move device not present state + continue + } + + if (LEqual (procPcieCheckForGen2Workaround (Arg0), TRUE)) { + Store (" Request Gen2 workaround", Debug) + procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x2000) + Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) + procPcieSetLinkSpeed (Arg0, DEF_LINK_SPEED_GEN1) + Store (DEF_TRAINING_STATE_REQUEST_RESET, varStateLocal2) + } + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_NOT_PRESENT)) { + Store (" State: Device not present", Debug) + procPcieTrainingControl (Arg0, 1) + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFF, 0) +#ifdef PCIE_MAX_PAYLOAD_SUPPORT + procPcieClearMaxPayload (Arg0) +#endif + + // Find device on secondary bus + Store (ShiftLeft (Add( Arg0, 2), 3), varTempBdfLocal0) + Store (procPciDwordRead (varTempBdfLocal0, 0x18), varTempLocal1) + And (ShiftRight (varTempLocal1, 8), 0xFF, varTempLocal1) + Store (Concatenate (" Remove device from Bus : ", ToHexString (varTempLocal1), varStringBuffer), Debug) + ShiftLeft (varTempLocal1, 8, varTempBdfLocal0) + Store (procPciDwordRead (varTempBdfLocal0, 0x0), varTempLocal0) + if (LEqual (varTempLocal0, 0xFFFFFFFF)) { + Store (" Device has been un-pluged!! ", Debug) + } + // Exclude device from PSPP managment since it is not present + Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) + Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_REQUEST_RESET)) { + Store (" State: Request Reset", Debug) + if (CondRefOf (\_SB.ALIC, Local6)) { + Store (" Call ALIC method", Debug) + //varTempLocal1 contain port BDF + Store(ShiftLeft (Add (Arg0, 2), 3), varTempLocal1) + \_SB.ALIC (varTempLocal1, 0) + Sleep (2) + \_SB.ALIC (varTempLocal1, 1) + Store (0, varCountLocal3) + Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) + continue + } + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) + } + if (LEqual (varStateLocal2, DEF_TRAINING_DEVICE_PRESENT)) { + Store (" State: Device present", Debug) + Store (DEF_HOTPLUG_STATUS_DEVICE_PRESENT, varResultLocal4) + Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) +#ifdef PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFFUNUSED, 0) +#endif +#ifdef PCIE_MAX_PAYLOAD_SUPPORT + procPcieSetMaxPayload (Arg0) +#endif +#ifdef PCIE_CLKPM_SUPPORT + procPcieClkPmConfigure (Arg0) +#endif + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_COMPLETE)) { + if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + Store (1, varPsppAcDcOverride) + procApplyPsppState () + } + Store (DEF_TRAINING_STATE_EXIT, varStateLocal2) + } + } + Store ("PciePortTraining Exit", Debug) + return (varResultLocal4) + } + + + /*----------------------------------------------------------------------------------------*/ + /** + * Lane control + * + * Arg0 - Port Index + * Arg1 - 0 - Power off all lanes / 1 - Power on all Lanes / 2 Power off unused lanes + * Arg2 - link width + */ + + Method (procPcieLaneControl, 3, Serialized) { + Store ("PcieLaneControl Enter", Debug) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) + Store (procPcieGetPortInfo (Arg0), Local7) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) +#endif + Store (DerefOf (Index (Local7, DEF_OFFSET_START_CORE_LANE)), varStartCoreLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_CORE_LANE)), varEndCoreLane) + + Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_MAX_PHY), varMaxPhyLinkWidth) + + if (LEqual (Arg1, DEF_PCIE_LANE_POWEROFF)) { + procPcieLaneEnableControl (Arg0, varStartCoreLane, Add (varStartCoreLane, Subtract(varMaxPhyLinkWidth, 1)), 1) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1) +#endif + } + if (LEqual (Arg1, DEF_PCIE_LANE_POWERON)) { +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0) +#endif + procPcieLaneEnableControl (Arg0, varStartCoreLane, Add (varStartCoreLane, Subtract(varMaxPhyLinkWidth, 1)), 0) + } + if (LNotEqual (Arg1, DEF_PCIE_LANE_POWEROFFUNUSED)) { + return (0) + } + + // Local2 should have link width (active lanes) + // Local3 should have first non active lanes + // Local4 should have last non active lanes + + if (LEqual(Arg2, 0)) { + Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_ACTIVE), varActiveLinkWidthLocal2) + } else { + Store ( Arg2 , varActiveLinkWidthLocal2) + } + // Let say Link width is x1 than local2 = 1, Local3 = 1 Local4 = 15 for non reversed case + // while for reversed case should be Local2 = 1 Local3 = 0 and Local4 = 14 + + if (LLessEqual (varMaxPhyLinkWidth, varActiveLinkWidthLocal2)) { + // Active link equal max link width, nothing needs to be done + return (0) + } + + Store (procPcieIsPortReversed (Arg0), varIsReversedLocal1) + //There is unused lanes after device plugged + if (LEqual(varIsReversedLocal1, FALSE)) { + Store (" Port Not Reversed", Debug) + // Link not reversed + Add (varStartCoreLane, varActiveLinkWidthLocal2, Local3) + Store (varEndCoreLane, Local4) + } else { + // Link reversed + Store (" Port Reversed", Debug) + Subtract (varEndCoreLane, varActiveLinkWidthLocal2, Local4) + Store (varStartCoreLane, Local3) + } + procPcieLaneEnableControl (Arg0, Local3, Local4, 1) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + if (LGreater (varStartPhyLane, varEndPhyLane)) { + Store (varEndPhyLane, Local3) + Store (varStartPhyLane, Local4) + } else { + Store (varEndPhyLane, Local4) + Store (varStartPhyLane, Local3) + } + if (LEqual(varIsReversedLocal1, FALSE)) { + // Not reversed + Add (Local3, varActiveLinkWidthLocal2, Local3) + } else { + // Link reversed + Subtract (Local4, varActiveLinkWidthLocal2, Local4) + } + procPcieLanePowerControl (Local3, Local4, 1) +#endif + return (0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Check if GEN2 workaround applicable + * + * Arg0 - Port Index + * Retval - TRUE / FALSE + */ + + Method (procPcieCheckForGen2Workaround, 1, NotSerialized) { + Store (Buffer (16) {}, Local1) + Store (0x0, Local0) + while (LLessEqual (Local0, 0x3)) { + Store (procPciePortIndirectRegisterRead (Arg0, Add (Local0, 0xA5)), Local2) + Store (Local2, Index (Local1, Multiply (Local0, 4))) + Store (ShiftRight (Local2, 8), Index (Local1, Add (Multiply (Local0, 4), 1))) + Store (ShiftRight (Local2, 16), Index (Local1, Add (Multiply (Local0, 4), 2))) + Store (ShiftRight (Local2, 24), Index (Local1, Add (Multiply (Local0, 4), 3))) + Increment (Local0) + } + Store (0, Local0) + while (LLess (Local0, 15)) { + if (LAnd (LEqual (DeRefOf (Index (Local1, Local0)), 0x2a), LEqual (DeRefOf (Index (Local1, Add (Local0, 1))), 0x9))) { + return (TRUE) + } + Increment (Local0) + } + return (FALSE) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Is port reversed + * + * Arg0 - Port Index + * Retval - 0 - Not reversed / !=0 - Reversed + */ + Method (procPcieIsPortReversed , 1, Serialized) { + Store (procPcieGetPortInfo (Arg0), Local7) + + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) + Store (0, Local0) + if (LGreater (varStartPhyLane, varEndPhyLane)) { + Store (1, Local0) + } + And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1) + return (And (Xor (Local0, Local1), 0x1)) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Training Control + * + * Arg0 - Port Index + * Arg1 - Hold Training (1) / Release Training (0) + */ + Method (procPcieTrainingControl , 2, NotSerialized) { + Store ("PcieTrainingControl Enter", Debug) + Store (procPcieGetPortInfo (Arg0), Local7) + Store (DerefOf (Index (Local7, DEF_OFFSET_PORT_ID)), varPortId) + Store ( + Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), + varWrapperId + ) + procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1); + Store ("PcieTrainingControl Exit", Debug) + } + + +Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16}) + /*----------------------------------------------------------------------------------------*/ + /** + * Get actual negotiated/PHY or core link width + * + * Arg0 - Port Index + * Arg1 - 0/1 Negotiated/Phy + * Retval - Link Width + */ + Method (procPcieGetLinkWidth, 2, NotSerialized) { + Store ("PcieGetLinkWidth Enter", Debug) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) + + if (LEqual (Arg1, DEF_LINKWIDTH_ACTIVE)){ + //Get negotiated length + And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0) + Store (DeRefOf (Index (varLinkWidthBuffer, Local0)), Local1) + Store (Concatenate (" Active Link Width :", ToHexString (Local1), varStringBuffer), Debug) + } else { + //Get phy length + Store (procPcieGetPortInfo (Arg0), Local7) + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) + if (LGreater (varStartPhyLane, varEndPhyLane)) { + Subtract (varStartPhyLane, varEndPhyLane, Local1) + } else { + Subtract (varEndPhyLane, varStartPhyLane, Local1) + } + Increment (Local1) + Store (Concatenate (" PHY Link Width :", ToHexString (Local1), varStringBuffer), Debug) + } + Store ("PcieGetLinkWidth Exit", Debug) + return (Local1) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe lane mux lane enable control (hotplug support) + * + * Arg0 - Port Index + * Arg1 - Start Lane + * Arg2 - End Lane + * Arg3 - Enable(0) / Disable(1) + */ + Method (procPcieLaneEnableControl, 4, Serialized) { + Store ("PcieLaneEnableControl Enter", Debug) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) + Store (Concatenate (" Arg2 : ", ToHexString (Arg2), varStringBuffer), Debug) + Store (Concatenate (" Arg3 : ", ToHexString (Arg3), varStringBuffer), Debug) + Store (procPcieGetPortInfo (Arg0), Local7) + Store (Arg1, varStartCoreLane) + Store (Arg2, varEndCoreLane) + Store ( + Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), + varWrapperId + ) + if (LGreater (varStartCoreLane, varEndCoreLane)) { + Subtract (varStartCoreLane, varEndCoreLane, Local1) + Store (varEndCoreLane, Local2) + } else { + Subtract (varEndCoreLane, varStartCoreLane, Local1) + Store (varStartCoreLane, Local2) + } + ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, varLaneBitmapOrMaskLocal3) + Store (Not (varLaneBitmapOrMaskLocal3), varLaneBitmapAndMaskLocal4) + Store (Concatenate (" Lane Bitmap : ", ToHexString (varLaneBitmapOrMaskLocal3), varStringBuffer), Debug) + if (Lequal (Arg3, 1)) { + Store (0, varLaneBitmapOrMaskLocal3) + } + procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), varLaneBitmapAndMaskLocal4, varLaneBitmapOrMaskLocal3); + Stall (10) + Store ("PcieLaneEnableControl Exit", Debug) + } + +#ifdef PCIE_MAX_PAYLOAD_SUPPORT + + /*----------------------------------------------------------------------------------------*/ + /** + * Max_Payload_Size Blacklist + * + * Entry 1 = Vendor & Device ID + * Entry 2 = Max_Payload_Size for this device + */ + Name (varPayloadBlacklist, Package () { + Package() {0x10831969, 0} + }) + + /*----------------------------------------------------------------------------------------*/ + /** + * Set Max_Payload_Size + * + * Arg0 - Port Index + */ + Method (procPcieSetMaxPayload, 1, Serialized) { + + // Local variable usage + // varTempLocal0 - Temporary storage + // varBdfLocal1 - Address of port config space + // varCapLocal2 - Offset of port PCIe Capabilities + // varMaxPayloadLocal3 - Largest common value of Max_Payload_Size capability + // varMaxFunctionLocal4 - Max function number + // varFunctionLocal5 - Current function number + // varDeviceIDLocal6 - Root port BDF and Vendor and device ID for blacklist workaround + // varIndexLocal7 - Package index for blacklist workaround + + Store ("PcieSetMaxPayload Enter", Debug) + + // Get Port BDF from Port Index + Store (ShiftLeft (Add( Arg0, 2), 3), varDeviceIDLocal6) + Store (procFindPciCapability (varDeviceIDLocal6, 0x10), varCapLocal2) + if (LNotEqual (varCapLocal2, 0)) { + + // Find device on secondary bus + Store (procPciDwordRead (varDeviceIDLocal6, 0x18), varTempLocal0) + And (ShiftRight (varTempLocal0, 8), 0xFF, varTempLocal0) + + Store (Concatenate (" EP on SecondaryBus : ", ToHexString (varTempLocal0), varStringBuffer), Debug) + + ShiftLeft (varTempLocal0, 8, varBdfLocal1) + + Store (procPciDwordRead (varBdfLocal1, 0xC), varTempLocal0) + Store (And (ShiftRight (varTempLocal0, 16), 0xFF), varTempLocal0) + if (LNotEqual (And (varTempLocal0, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal4) + } else { + Store (0x0, varMaxFunctionLocal4) + } + // Start with illegal value so we will know if a device is foudn + Store (0x08, varMaxPayloadLocal3) + // Search all functions and find smallest Max_Payload_Size + Store (0x0, varFunctionLocal5) + while (LLessEqual (varFunctionLocal5, varMaxFunctionLocal4)) { + Store (procFindPciCapability (Add (varBdfLocal1, varFunctionLocal5), 0x10), varCapLocal2) + if (LNotEqual (varCapLocal2, 0)) { + And (procPciDwordRead (Add (varBdfLocal1, varFunctionLocal5), Add (varCapLocal2, 0x04)), 0x07, varTempLocal0) + // Scan blacklist package for workaround + Store(procPciDwordRead (Add (varBdfLocal1, varFunctionLocal5), 0), varDeviceIDLocal6) + Store (0, varIndexLocal7) + while (LLess (varIndexLocal7, SizeOf (varPayloadBlacklist))) { + if (LEqual (DeRefOf (Index (DeRefOf (Index (varPayloadBlacklist, varIndexLocal7)), 0)), varDeviceIDLocal6)) { + Store (DeRefOf (Index (DeRefOf (Index (varPayloadBlacklist, varIndexLocal7)), 1)), varTempLocal0) + } + Increment (varIndexLocal7) + } + if (LLess (varTempLocal0, varMaxPayloadLocal3)) { + Store (varTempLocal0, varMaxPayloadLocal3) + } + } + Increment(varFunctionLocal5) + } + + // We will only set Max_Payload_Size if PCIe capabilties were found on the downstream side + if (LNotEqual (varMaxPayloadLocal3, 0x08)) { + // Read root port Max_Payload_Size and compare with device supported value + Store (ShiftLeft (Add( Arg0, 2), 3), varDeviceIDLocal6) + Store (procFindPciCapability (varDeviceIDLocal6, 0x10), varCapLocal2) + And (procPciDwordRead (varDeviceIDLocal6, Add (varCapLocal2, 0x04)), 0x07, varTempLocal0) + if (LLess (varTempLocal0, varMaxPayloadLocal3)) { + Store (varTempLocal0, varMaxPayloadLocal3) + } + // Search all functions and set smallest Max_Payload_Size to all functions + // Relocate Max_Payload_Size data to bits 7-5 + Store (Concatenate (" Setting Max_Payload_Size : ", ToHexString (varMaxPayloadLocal3), varStringBuffer), Debug) + ShiftLeft (varMaxPayloadLocal3, 5, varMaxPayloadLocal3) + // Set the root port Max_Payload_Size + procPciDwordRMW (varDeviceIDLocal6, Add (varCapLocal2, 0x08), Not (0x000000E0), varMaxPayloadLocal3) + //Set the Max_Payload_Size in each function that has PCIe Capabilities + Store (0x0, varFunctionLocal5) + while (LLessEqual (varFunctionLocal5, varMaxFunctionLocal4)) { + Store (procFindPciCapability (Add (varBdfLocal1, varFunctionLocal5), 0x10), varCapLocal2) + if (LNotEqual (varCapLocal2, 0)) { + procPciDwordRMW (varBdfLocal1, Add (varCapLocal2, 0x08), Not (0x000000E0), varMaxPayloadLocal3) + } + Increment(varFunctionLocal5) + } + } + } + Store ("PcieSetMaxPayload Exit", Debug) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Clear Max_Payload_Size + * + * Arg0 - Port Index + */ + Method (procPcieClearMaxPayload, 1, Serialized) { + + // Local variable usage + // varPortBdfLocal0 - Address of root port config space + // varPortCapLocal1 - Offset of root port PCIe Capabilities + + Store ("PcieClearMaxPayload Enter", Debug) + + // Get Port BDF from Port Index + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal0) + Store (procFindPciCapability (varPortBdfLocal0, 0x10), varPortCapLocal1) + if (LNotEqual (varPortCapLocal1, 0)) { + // Set the root port Max_Payload_Size to default = 0x0 + procPciDwordRMW (varPortBdfLocal0, Add (varPortCapLocal1, 0x08), Not (0x000000E0), 0x0) + + } + Store ("PcieClearMaxPayload Exit", Debug) + } +#endif + +#ifdef PCIE_CLKPM_SUPPORT + Method (procPcieClkPmConfigure, 1, Serialized) { + Store ("PcieClkPmConfigure Enter", Debug) + Store (procPcieGetPortInfo (Arg0), Local7) + Store (DerefOf (Index (Local7, DEF_OFFSET_CLK_PM_SUPPORT)), varTempLocal0) + if (LEqual (varTempLocal0, 0)) { + Store ("PcieClkPmConfigure Exit", Debug) + return (0) + } + // Get Port PCI address + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal0) + // Get device BDf on secondary bus + And (varTempLocal0, 0xFF00, varEndpointBdfLocal2) + + Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal0) + Store (And (ShiftRight (varTempLocal0, 16), 0xFF), varTempLocal0) + if (LNotEqual (And (varTempLocal0, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal3) + } else { + Store (0x0, varMaxFunctionLocal3) + } + Store (0, varFunctionLocal4) + Store (0, varIsClkPmSupportedLocal5) + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal3)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Or (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieCapabilityOffsetLocal6) + if (LEqual (varPcieCapabilityOffsetLocal6, 0)) { + Increment (varFunctionLocal4) + continue + } + // Found PCI capability + if (LNotEqual (And (procPciDwordRead (Or (varEndpointBdfLocal2, varFunctionLocal4), Add (varPcieCapabilityOffsetLocal6, 0xC)), ShiftLeft (1,18)), 0)) { + Store (1, varIsClkPmSupportedLocal5) + } else { + Store (0, varIsClkPmSupportedLocal5) + break + } + Increment (varFunctionLocal4) + } + if (LEqual (varIsClkPmSupportedLocal5, 0)) { + Store ("PcieClkPmConfigure Exit", Debug) + return (0) + } + Store (0, varFunctionLocal4) + + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal3)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Or (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieCapabilityOffsetLocal6) + if (LEqual (varPcieCapabilityOffsetLocal6, 0)) { + Increment (varFunctionLocal4) + continue + } + // Enable CLK PM Capability + procPciDwordRMW (Or (varEndpointBdfLocal2, varFunctionLocal4), Add (varPcieCapabilityOffsetLocal6, 0x10), 0xffffffff, ShiftLeft (1, 8)) + Increment (varFunctionLocal4) + } + Store ("PcieClkPmConfigure Exit", Debug) + } +#endif + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl new file mode 100644 index 0000000000..abe0cdd459 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl @@ -0,0 +1,88 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe MMIO Base address + * + */ + + Name ( + AD01, + 0xE0000000 + ) + + Alias ( + AD01, + varPcieBase + ) + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl new file mode 100644 index 0000000000..378c0392ef --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl @@ -0,0 +1,289 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCI config register through MMIO + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Register offset + */ + Method (procPciDwordRead, 2, Serialized) { + Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) + Add (Arg1, Local0, Local0) + OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) + Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { + Offset (0x0), + varPciReg32, 32, + } + return (varPciReg32) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCI config register through MMIO + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Register offset + * Arg2 - Value + */ + Method (procPciDwordWrite, 3, Serialized) { + Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) + Add (Arg1, Local0, Local0) + OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) + Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { + Offset (0x0), + varPciReg32, 32, + } + Store (Arg2, varPciReg32) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCI config register through MMIO + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Register offset + * Arg2 - AND mask + * Arg3 - OR mask + */ + Method (procPciDwordRMW, 4, Serialized) { + Store (procPciDwordRead (Arg0, Arg1), Local0) + Or (And (Local0, Arg2), Arg3, Local0) + procPciDwordWrite (Arg0, Arg1, Local0) + } + + Mutex(varPciePortAccessMutex, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Port Index + * Arg1 - Register offset + * + */ + Method (procPciePortIndirectRegisterRead, 2, NotSerialized) { + Acquire(varPciePortAccessMutex, 0xFFFF) + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + procPciDwordWrite (Local0, 0xe0, Arg1) + Store (procPciDwordRead (Local0, 0xe4), Local0) + Release (varPciePortAccessMutex) + return (Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCIe port indirect register + * + * Arg0 - Port Index + * Arg1 - Register offset + * Arg2 - Value + */ + Method (procPciePortIndirectRegisterWrite, 3, NotSerialized) { + Acquire(varPciePortAccessMutex, 0xFFFF) + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + procPciDwordWrite (Local0, 0xe0, Arg1) + procPciDwordWrite (Local0, 0xe4, Arg2) + Release (varPciePortAccessMutex) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Port Index + * Arg1 - Register offset + * Arg2 - AND Mask + * Arg3 - OR Mask + * + */ + Method (procPciePortIndirectRegisterRMW, 4, NotSerialized) { + Store (procPciePortIndirectRegisterRead (Arg0, Arg1), Local0) + Or (And (Local0, Arg2), Arg3, Local0) + procPciePortIndirectRegisterWrite (Arg0, Arg1, Local0) + } + Mutex(varHostAccessMutex, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - BDF + * Arg1 - Register offset + * Arg2 - Register address + * + */ + Method (procIndirectRegisterRead, 3, NotSerialized) { + Acquire(varHostAccessMutex, 0xFFFF) + procPciDwordWrite (Arg0, Arg1, Arg2) + Store (procPciDwordRead (Arg0, Add (Arg1, 4)), Local0) + Release(varHostAccessMutex) + return (Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCIe port indirect register + * + * Arg0 - BDF + * Arg1 - Register offset + * Arg2 - Register address + * Arg3 - Value + */ + Method (procIndirectRegisterWrite, 4, NotSerialized) { + Acquire(varHostAccessMutex, 0xFFFF) + procPciDwordWrite (Arg0, Arg1, Arg2) + procPciDwordWrite (Arg0, Add (Arg1, 4), Arg3) + Release(varHostAccessMutex) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read Modify Write indirect registers + * + * Arg0 - BDF + * Arg1 - Register Offset + * Arg2 - Register Address + * Arg3 - AND Mask + * Arg4 - OR Mask + * + */ + Method (procIndirectRegisterRMW, 5, NotSerialized) { + Store (procIndirectRegisterRead (Arg0, Arg1, Arg2), Local0) + Or (And (Local0, Arg3), Arg4, Local0) + procIndirectRegisterWrite (Arg0, Arg1, Arg2, Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Find Pci Capability + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Capability id + */ + Method (procFindPciCapability, 2, NotSerialized) { + Store (0x34, Local1) + if (LEqual (procPciDwordRead (Arg0, 0x0), 0xFFFFFFFF)) { + // Device not present + return (0) + } + Store (1, Local0) + while (LEqual (Local0, 1)) { + Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1) + if (LEqual (Local1, 0)) { + break + } + if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) { + Store (0, Local0) + } else { + Increment (Local1) + } + } + return (Local1) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * + * + * Arg0 - Aspm + * Arg1 - 0: Read, 1: Write + */ + Method (procPcieSbAspmControl, 2, Serialized) { + // Create an opregion for PM IO Registers + OperationRegion (PMIO, SystemIO, 0xCD6, 0x2) + Field (PMIO, ByteAcc, NoLock, Preserve) + { + PMRI, 8, + PMRD, 8 + } + IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) + { + Offset(0xE0), // IO Base address of A-Link Express/ A-Link Bridge register + ABAR, 32, + } + OperationRegion (ACFG, SystemIO, ABAR, 0x8) + Field (ACFG, DWordAcc, Nolock, Preserve) //AB_INDX/AB_DATA + { + ABIX, 32, + ABDA, 32 + } + + Store (0, Local0) + if (LEqual (Arg1, 0)) { + Store (0x80000068, ABIX) + Store (ABDA, Local0) + return (Local0) + } else { + Store (0x80000068, ABIX) + Store (ABDA, Local0) + Or (And (Local0, 0xfffffffc), Arg0, Local0) + Store (Local0, ABDA) + } + } + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl new file mode 100644 index 0000000000..228c839b3a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl @@ -0,0 +1,109 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe port info + * + */ + + Name ( + AD07, + Package () { + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev2 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev3 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev4 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev5 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev6 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev7 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev8 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev9 + } + ) + + Alias ( + AD07, + varPortInfo + ) + + + /*----------------------------------------------------------------------------------------*/ + /** + * + * + * Arg0 - Port ID + * Retval - buffer that represent port data set + */ + Method (procPcieGetPortInfo, 1, NotSerialized) { + return (DeRefOf (Index (varPortInfo, Arg0))) + } + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl new file mode 100644 index 0000000000..bedd41cddd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl @@ -0,0 +1,825 @@ +/** +* @file +* +* ALIB PSPP ASL library +* +* +* +* @xrefitem bom "File Content Label" "Release Content" +* @e project: AGESA +* @e sub-project: GNB +* @e \$Revision: 65976 $ @e \$Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $ +* +*/ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe Performance Policy + * + * varPsppPolicy - 0 Disabled + * 1 Performance + * 2 Balance Hight + * 3 Balance Low + * 4 Power Saving + */ + Name ( + AD02, + 0x0 + ) + + Alias ( + AD02, + varPsppPolicy + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * GEN2 VID + * + */ + + Name ( + AD03, + 0x0 + ) + + Alias ( + AD03, + varGen2Vid + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * GEN1 VID + * + */ + Name ( + AD04, + 0x0 + ) + + Alias ( + AD04, + varGen1Vid + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * Boot VID + * + */ + + Name ( + AD05, + 0x0 + ) + + Alias ( + AD05, + varBootVid + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * Max Port link speed + * + */ + Name (AD06, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + Alias (AD06, varMaxLinkSpeed) + + + /*----------------------------------------------------------------------------------------*/ + /** + * Max link speed that was changed during runtime (hotplug for instance) + * + */ + + Name (AD08, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + Alias (AD08, varOverrideLinkSpeed) + + /*----------------------------------------------------------------------------------------*/ + /** + * Policy service status + * + * varPsppPolicyService - 0 (Stopped) + * 1 (Started) + */ + + Name (varPsppPolicyService, 0x0 ) + + /*----------------------------------------------------------------------------------------*/ + /** + * AC DC state + * + * varPsppAcDcState - 0 (AC) + * 1 (DC) + */ + + Name (varPsppAcDcState, 0x0) + Name (varPsppAcDcOverride, 0x1) + + /*----------------------------------------------------------------------------------------*/ + /** + * Client ID array + * + */ + + Name (varPsppClientIdArray, + Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} + ) + + Name (varDefaultPsppClientIdArray, + Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} + ) + /*----------------------------------------------------------------------------------------*/ + /** + * LInk speed requested by device driver + * + */ + + Name (varRequestedLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + /*----------------------------------------------------------------------------------------*/ + /** + * Current link speed + * + */ + Name (AD09, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) + Alias (AD09, varCurrentLinkSpeed) + /*----------------------------------------------------------------------------------------*/ + /** + * Template link speed + * + */ + Name ( + varGen1LinkSpeedTemplate, + Package () { + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1 + }) + + /*----------------------------------------------------------------------------------------*/ + /** + * Template link speed + * + */ + Name (varLowVoltageRequest, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }) + + /*----------------------------------------------------------------------------------------*/ + /** + * Global varuable + * + */ + Name (varPortIndex, 0) + + /*----------------------------------------------------------------------------------------*/ + /** + * Sclk VID that was changed during runtime + * + */ + + Name (AD10, Package () {0x00, 0x00, 0x00, 0x00}) + + Alias (AD10, varSclkVid) + + /*----------------------------------------------------------------------------------------*/ + /** + * Report AC/DC state + * + * Arg0 - Data Buffer + */ + Method (procPsppReportAcDsState, 1, Serialized) { + Store ("PsppReportAcDsState Enter", Debug) + + Store (DeRefOf (Index (Arg0, 0x2)), varArgAcDcStateLocal1) + Store (Concatenate (" AC/DC state: ", ToHexString (varArgAcDcStateLocal1), varStringBuffer), Debug) + + Store (procPsppGetAcDcState(), varCurrentAcDcStateLocal0) + Store (varArgAcDcStateLocal1, varPsppAcDcState) + + Or (ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local2) + Or (ShiftLeft (varPsppAcDcState, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (varPsppAcDcOverride, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local3) + procIndirectRegisterRMW (0x0, 0x60, 0xF4, Not (Local2), And (Local2, Local3)) + + + if (LEqual (varArgAcDcStateLocal1, varCurrentAcDcStateLocal0)) { + Store (" No action. [AC/DC state not changed]", Debug) + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + + // Disable both APM (boost) and PDM flow on DC event enable it on AC. + procApmPdmActivate(varPsppAcDcState) + + // Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service. + if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) +#ifdef ALTVDDNB_SUPPORT + procNbAltVddNb (DEF_LINK_SPEED_GEN1) +#endif + } + if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + Store (" No action. [Policy type]", Debug) + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { + Store (" No action. [Policy not started]", Debug) + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + procApplyPsppState () + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe Performance Request + * + * Arg0 - Data Buffer + */ + Method (procPsppPerformanceRequest, 1, NotSerialized) { + Store (procPsppProcessPerformanceRequest (Arg0), Local7) + Store (DeRefOf (Index (Local7, 2)), varReturnStatusLocal0) + if (LNotEqual (varReturnStatusLocal0, 2)) { + return (Local7) + } + procApplyPsppState () + return (Local7) + } + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe Performance Request + * + * Arg0 - Data Buffer + */ + Method (procPsppProcessPerformanceRequest, 1, NotSerialized) { + Store ("PsppProcessPerformanceRequest Enter", Debug) + Name (varClientBus, 0) + Store (0, varPortIndex) + Store (Buffer (10) {}, Local7) + CreateWordField (Local7, 0x0, varReturnBufferLength) + Store (3, varReturnBufferLength) + CreateByteField (Local7, 0x2, varReturnStatus) + Store (1, varReturnStatus) + + if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + Store (" No action. [Policy type]", Debug) + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { + Store (" No action. [Policy not started]", Debug) + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + CreateWordField (Arg0, 0x2, varClientId) + CreateWordField (Arg0, 0x4, varValidFlag) + CreateWordField (Arg0, 0x6, varFlag) + CreateByteField (Arg0, 0x8, varRequestType) + CreateByteField (Arg0, 0x9, varRequestData) + + Store (Concatenate (" Client ID : ", ToHexString (varClientId), varStringBuffer), Debug) + Store (Concatenate (" Valid Flags : ", ToHexString (varValidFlag), varStringBuffer), Debug) + Store (Concatenate (" Flags : ", ToHexString (varFlag), varStringBuffer), Debug) + Store (Concatenate (" Request Type: ", ToHexString (varRequestType), varStringBuffer), Debug) + Store (Concatenate (" Request Data: ", ToHexString (varRequestData), varStringBuffer), Debug) + + + And (ShiftRight (varClientId, 8), 0xff, varClientBus) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { + Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) + And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number + And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number + if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { + break + } + } + Increment (varPortIndex) + } + if (LGreater (varPortIndex, varMaxPortIndexNumber)) { + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + + Store (Concatenate (" Performance request for port index : ", ToHexString (varPortIndex), Local6), Debug) + + if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) { + Store (varClientId, Index (varPsppClientIdArray, varPortIndex)) + } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) { + // We already have registered client + Store (" No action. [Unsupported request]", Debug) + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + Store (0, Index (varLowVoltageRequest, varPortIndex)) + if (LEqual (varRequestData, 0)) { + Store (0x0000, Index (varPsppClientIdArray, varPortIndex)) + } + if (LEqual (varRequestData, 1)) { + Store (1, Index (varLowVoltageRequest, varPortIndex)) + } + if (LEqual (varRequestData, 2)) { + Store (DEF_LINK_SPEED_GEN1, Index (varRequestedLinkSpeed, varPortIndex)) + } + if (LEqual (varRequestData, 3)) { + Store (DEF_LINK_SPEED_GEN2, Index (varRequestedLinkSpeed, varPortIndex)) + } + if (LEqual (And (varValidFlag, varFlag), 0x1)) { + Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)), Index (varRequestedLinkSpeed, varPortIndex)) + } + Store (2, varReturnStatus) + Store ("PsppProcessPerformanceRequest Exit", Debug) + return (Local7) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PSPP Start/Stop Management Request + * + * Arg0 - Data Buffer + */ + + Method (procChecPortAllocated, 1, Serialized) { + if (LEqual (DeRefOf (Index (varMaxLinkSpeed, Arg0)), 0)) { + return (DEF_PORT_NOT_ALLOCATED) + } + return (DEF_PORT_ALLOCATED) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PSPP Start/Stop Management Request + * + * Arg0 - Data Buffer + */ + Method (procPsppControl, 1, Serialized) { + Store ("PsppControl Enter", Debug) + Store (Buffer (256) {}, Local7) + Store (3, Index (Local7, 0x0)) // Return Buffer Length + Store (0, Index (Local7, 0x1)) // Return Buffer Length + Store (0, Index (Local7, 0x2)) // Return Status + + Store (DerefOf (Index (Arg0, 0x2)), varPsppPolicyService) + + Store (procIndirectRegisterRead (0x0, 0x60, 0xF4), varPsppScratchLocal0) + + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_START)) { + if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_START)) { + // Policy already started + Store (" No action. [Policy already started]", Debug) + Store ("PsppControl Exit", Debug) + return (Local7) + } + Or (varPsppScratchLocal0, DEF_PSPP_POLICY_START, varPsppScratchLocal0) + } + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { + if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_STOP)) { + // Policy already stopped + Store (" No action. [Policy already stopped]", Debug) + Store ("PsppControl Exit", Debug) + return (Local7) + } + And (varPsppScratchLocal0, Not (DEF_PSPP_POLICY_START), varPsppScratchLocal0) + } + Or (varPsppScratchLocal0, Shiftleft (varPsppPolicy, DEF_SCARTCH_PSPP_POLICY_OFFSET), varPsppScratchLocal0) + procIndirectRegisterWrite (0x0, 0x60, 0xF4, varPsppScratchLocal0) + + procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray)) + + // Reevaluate APM/PDM state here on S3 resume while staying on DC. + procApmPdmActivate(varPsppAcDcState) + + // Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service. + if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) +#ifdef ALTVDDNB_SUPPORT + procNbAltVddNb (DEF_LINK_SPEED_GEN1) +#endif + } + //Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage + if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + // Load default speed capability state + if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) { + procCopyPackage (RefOf (varMaxLinkSpeed), RefOf (varCurrentLinkSpeed)) + Store (0, varPortIndex) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LNotEqual (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), 0)) { + Store (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), Index (varCurrentLinkSpeed, varPortIndex)) + } + Increment (varPortIndex) + } + } else { + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varCurrentLinkSpeed)) +#ifdef SBLINK_BALANCE_LOW_GEN2_SUPPORT + Store (DeRefOf (Index (varMaxLinkSpeed, DEF_SB_PORT_INDEX)),Index (varCurrentLinkSpeed, DEF_SB_PORT_INDEX)) + //Store (DEF_LINK_SPEED_GEN2, Index (varCurrentLinkSpeed, DEF_SB_PORT_INDEX)) +#endif + + } + procApplyPsppState () + } + Store ("PsppControl Exit", Debug) + return (Local7) + } + + Name (varNewLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + /*----------------------------------------------------------------------------------------*/ + /** + * Evaluate PCIe speed on all links according to PSPP state and client requests + * + * + * + */ + Method (procApplyPsppState, 0, Serialized) { + Store ("ApplyPsppState Enter", Debug) + Store (0, varPortIndex) + + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_ALLOCATED)) { + Store (procGetPortRequestedCapability (varPortIndex), Index (varNewLinkSpeed, varPortIndex)) + } + Increment (varPortIndex) + } + if (LNotEqual(Match (varLowVoltageRequest, MEQ, 0x01, MTR, 0, 0), ONES)) { + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) + } + if (LNotEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { + // Set GEN2 voltage + Store ("Set GEN2 VID", Debug) +#ifdef ALTVDDNB_SUPPORT + procNbAltVddNb (DEF_LINK_SPEED_GEN2) +#endif + procPcieSetVoltage (DEF_LINK_SPEED_GEN2, 1) +// procPcieAdjustPll (DEF_LINK_SPEED_GEN2) + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN2) + } + Store (0, varPortIndex) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_NOT_ALLOCATED)) { + Increment (varPortIndex) + continue + } + Store (DerefOf (Index (varCurrentLinkSpeed, varPortIndex)), varCurrentLinkSpeedLocal0) + Store (DerefOf (Index (varNewLinkSpeed, varPortIndex)), varNewLinkSpeedLocal2) + if (LEqual (varCurrentLinkSpeedLocal0, varNewLinkSpeedLocal2)) { + Increment (varPortIndex) + continue + } + Store (varNewLinkSpeedLocal2, Index (varCurrentLinkSpeed, varPortIndex)) + procSetPortCapabilityAndSpeed (varPortIndex, varNewLinkSpeedLocal2) + Increment (varPortIndex) + } + if (LEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { + // Set GEN1 voltage + Store ("Set GEN1 VID", Debug) + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) +// procPcieAdjustPll (DEF_LINK_SPEED_GEN1) + procPcieSetVoltage (DEF_LINK_SPEED_GEN1, 0) +#ifdef ALTVDDNB_SUPPORT + procNbAltVddNb (DEF_LINK_SPEED_GEN1) +#endif + } +#ifdef PHY_SPEED_REPORT_SUPPORT + procReportPhySpeedCap () +#endif + Store ("ApplyPsppState Exit", Debug) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCI config register + * + * Arg0 - Port Index + * + */ + Method (procGetPortRequestedCapability, 1) { + Store (DEF_LINK_SPEED_GEN2, varCurrentSpeedLocal0) + Store (procPsppGetAcDcState(), varAcDcStateLocal1) + if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { + if (LOr (LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { + // Default policy cap to GEN1 + Store (DEF_LINK_SPEED_GEN1, varCurrentSpeedLocal0) + } +#ifdef SBLINK_BALANCE_LOW_GEN2_SUPPORT + if (LAnd (LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_AC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { + if (LEqual (Arg0, DEF_SB_PORT_INDEX)) { + Store (DEF_LINK_SPEED_GEN2, varCurrentSpeedLocal0) + } + } +#endif + if (LNotEqual (DerefOf (Index (varOverrideLinkSpeed, Arg0)), 0)) { + Store (DerefOf (Index (varOverrideLinkSpeed, Arg0)), varCurrentSpeedLocal0) + } + } else { + Store (DerefOf (Index (varRequestedLinkSpeed, Arg0)), varCurrentSpeedLocal0) + } + Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)),varMaxLinkSpeedLocal2) + if (LLess (varMaxLinkSpeedLocal2, varCurrentSpeedLocal0)) { + Store (varMaxLinkSpeedLocal2, varCurrentSpeedLocal0) + } + + + return (varCurrentSpeedLocal0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Set capability and speed + * + * Arg0 - Port Index + * Arg1 - Link speed + */ + Method (procSetPortCapabilityAndSpeed, 2, NotSerialized) { + Store ("SetPortCapabilityAndSpeed Enter", Debug) + Store (Concatenate (" Port Index : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Speed : ", ToHexString (Arg1), varStringBuffer), Debug) + + //UnHide UMI port + if (LEqual (Arg0, 6)) { + procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40); + } + + procPcieSetLinkSpeed (Arg0, Arg1) + + // Programming for LcInitSpdChgWithCsrEn + if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { + // Registered port, LcInitSpdChgWithCsrEn = 0. + procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0) + } else { + procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000) + } + + // Determine port PCI address and check port present + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + And (procPciePortIndirectRegisterRead (Arg0, 0xA5), 0x3f, varPortPresentLocal3) + procPciePortIndirectRegisterWrite (Arg0, 0x1, varPortPresentLocal3) + if (LGreaterEqual (varPortPresentLocal3, 0x10)) { + procDisableAndSaveAspm (Arg0) + Store (1, Local2) + while (Local2) { + //retrain port + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000000), 0x20) + Sleep (30) + while (And (procPciDwordRead (varPortBdfLocal1, 0x68), 0x08000000)) { + Sleep (10) + } + Store (0, Local2) + if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { + //Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentLinkSpeedLocal4) + if (LNotEqual (procPciePortGetCurrentLinkSpeed (Arg0), DEF_LINK_SPEED_GEN1)) { + Store (1, Local2) + } + } + } + procRestoreAspm (Arg0) + } else { + Store (" Device not present. Set capability and speed only", Debug) + } + //Hide UMI port + if (LEqual (Arg0, 6)) { + procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00); + } + Store ("SetPortCapabilityAndSpeed Exit", Debug) + } + + Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) + Name (varPcieLinkControlOffset, 0) + Name (varPcieLinkControlData, 0) + Name (varPcieRcControlData, 0) + + /*----------------------------------------------------------------------------------------*/ + /** + * Disable and save ASPM state + * + * Arg0 - Port Index + */ + Method (procDisableAndSaveAspm, 1, Serialized) { + Store (0, varPcieLinkControlOffset) + Store (0, varPcieLinkControlData) + + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + if (LEqual (Arg0, 6)) { + Store (" Disable SB ASPM", Debug) + Store (procPcieSbAspmControl (0, 0), Index (varPcieLinkControlArray, 0)) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) + procPcieSbAspmControl (0, 1) + return (0) + } + + Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) + + Store (Concatenate (" Disable EP ASPM on Secondary Bus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) + Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) + + Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + if (LNotEqual (And (varTempLocal3, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal0) + } else { + Store (0x0, varMaxFunctionLocal0) + } + Store (0, varFunctionLocal4) + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) + if (LEqual (varPcieLinkControlOffset, 0)) { + Increment (varFunctionLocal4) + continue + } + Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) + + Store (Concatenate (" Function number of Secondary Bus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) + Store (Concatenate (" PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) + // Save ASPM on EP + Store (procPciDwordRead (Add (varEndpointBdfLocal2, varFunctionLocal4) , varPcieLinkControlOffset), varPcieLinkControlData) + Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, varFunctionLocal4)) + + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (varPcieLinkControlData), varStringBuffer), Debug) + + procPciDwordRMW (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, Not (0x00000003), 0x00) + Store ("Disable ASPM on EP Complete!!", Debug) + Increment (varFunctionLocal4) + } + //Disable ASPM on RC + Store (procPciDwordRead (varPortBdfLocal1, 0x68), varPcieRcControlData) + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), 0x00) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Restore ASPM + * + * Arg0 - Port Index + */ + Method (procRestoreAspm, 1, Serialized) { + + Store (0, varPcieLinkControlOffset) + Store (0, varPcieLinkControlData) + + + // Restore SB ASPM + if (LEqual (Arg0, 6)) { + Store (" Restore SB ASPM", Debug) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) + procPcieSbAspmControl (DerefOf(Index (varPcieLinkControlArray, 0)), 1) + return (0) + } + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + // Restore EP ASPM + Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) + // Restore ASPM on RC + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), And (varPcieRcControlData, 0x3)) + + Store (Concatenate (" Disable EP ASPM on SecondaryBus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) + Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) + + Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + if (LNotEqual (And (varTempLocal3, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal0) + } else { + Store (0x0, varMaxFunctionLocal0) + } + Store (0, varFunctionLocal4) + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) + if (LEqual (varPcieLinkControlOffset, 0)) { + Increment (varFunctionLocal4) + continue + } + Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) + + Store (Concatenate (" Restore Function number of SecondaryBus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) + Store (Concatenate (" Restore PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))), varStringBuffer), Debug) + + procPciDwordWrite (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))) + Increment (varFunctionLocal4) + } + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Request VID + * + * Arg0 - Port Index + * Arg1 - PCIe speed + */ + + Method (procPcieSetLinkSpeed, 2) { + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { + procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x21) + procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x0) + } else { + procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x20000001) + procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x2) + } + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Ref Source Pckage + * Arg1 - Ref to Destination Package + * + */ + Method (procCopyPackage, 2, NotSerialized) { + + Store (SizeOf (Arg0), Local1) + Store (0, Local0) + While (LLess (Local0, Local1)) { + Store (DerefOf(Index(DerefOf (Arg0), Local0)), Index(DerefOf (Arg1), Local0)) + Increment (Local0) + } + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Ref Source Pckage + * Arg1 - Ref to Destination Package + * + */ + Method (procPsppGetAcDcState, 0 , NotSerialized) { + Return (And (varPsppAcDcState, varPsppAcDcOverride)) + } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c new file mode 100644 index 0000000000..a88b5d9e7a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c @@ -0,0 +1,445 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link ASPM + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "OptionGnb.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "PcieAspmBlackList.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + PCIE_ASPM_TYPE Aspm; + PCI_ADDR DownstreamPort; +} PCIE_ASPM_DATA; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieAspmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +SCAN_STATUS +PcieAspmCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +VOID +PcieAspmEnableOnLink ( + IN PCI_ADDR Downstream, + IN PCI_ADDR Upstream, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +PCIE_ASPM_TYPE +PcieAspmGetPmCapability ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable PCIE Advance state power management + * + * + * + * @param[in] DownstreamPort PCI Address of the downstream port + * @param[in] Aspm ASPM type + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +VOID +PcieLinkAspmEnable ( + IN PCI_ADDR DownstreamPort, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIE_ASPM_DATA PcieAspmData; + PcieAspmData.Aspm = Aspm; + PcieAspmData.ScanData.StdHeader = StdHeader; + PcieAspmData.ScanData.GnbScanCallback = PcieAspmCallback; + GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieAspmData.ScanData); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +SCAN_STATUS +PcieAspmCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + PCIE_ASPM_DATA *PcieAspmData; + PCIE_DEVICE_TYPE DeviceType; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + PcieAspmData = (PCIE_ASPM_DATA *) ScanData; + ScanStatus = SCAN_SUCCESS; + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + PcieAspmData->DownstreamPort = Device; + //PcieExitLatencyData->LinkCount++; + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); + //PcieExitLatencyData->LinkCount--; + break; + case PcieDeviceUpstreamPort: + PcieAspmEnableOnLink ( + PcieAspmData->DownstreamPort, + Device, + PcieAspmData->Aspm, + ScanData->StdHeader + ); + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + PcieAspmEnableOnLink ( + PcieAspmData->DownstreamPort, + Device, + PcieAspmData->Aspm, + ScanData->StdHeader + ); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + default: + break; + } + return ScanStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set ASMP State on PCIe device function + * + * + * + * @param[in] Function PCI address of function. + * @param[in] Aspm Aspm capability to enable + * @param[in] StdHeader Standard configuration header + * + */ + /*----------------------------------------------------------------------------------------*/ +VOID +PcieAspmEnableOnFunction ( + IN PCI_ADDR Function, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRMW ( + Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) , + AccessS3SaveWidth8, + (UINT32)~(BIT0 | BIT1), + Aspm, + StdHeader + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set ASMP State on all function of PCI device + * + * + * + * @param[in] Device PCI address of device. + * @param[in] Aspm Aspm capability to enable + * @param[in] StdHeader Standard configuration header + * + */ + /*----------------------------------------------------------------------------------------*/ +STATIC VOID +PcieAspmEnableOnDevice ( + IN PCI_ADDR Device, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxFunc; + UINT8 CurrentFunc; + MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; + for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { + Device.Address.Function = CurrentFunc; + if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { + PcieAspmEnableOnFunction (Device, Aspm, StdHeader); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable ASPM on link + * + * + * + * @param[in] Downstream PCI Address of downstrteam port + * @param[in] Upstream PCI Address of upstream port + * @param[in] Aspm Aspm capability to enable + * @param[in] StdHeader Standard configuration header + */ + +VOID +PcieAspmEnableOnLink ( + IN PCI_ADDR Downstream, + IN PCI_ADDR Upstream, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_LINK_ASPM LinkAsmp; + PCIE_ASPM_TYPE DownstreamCap; + PCIE_ASPM_TYPE UpstreamCap; + LinkAsmp.DownstreamPort = Downstream; + DownstreamCap = PcieAspmGetPmCapability (Downstream, StdHeader); + LinkAsmp.UpstreamPort = Upstream; + UpstreamCap = PcieAspmGetPmCapability (Upstream, StdHeader); + LinkAsmp.DownstreamAspm = DownstreamCap & UpstreamCap & Aspm & AspmL1; + LinkAsmp.UpstreamAspm = LinkAsmp.DownstreamAspm; + LinkAsmp.RequestedAspm = Aspm; + if ((UpstreamCap & Aspm & AspmL0s) != 0) { + LinkAsmp.UpstreamAspm |= AspmL0s; + } + if ((DownstreamCap & Aspm & AspmL0s) != 0) { + LinkAsmp.DownstreamAspm |= AspmL0s; + } + if (GnbBuildOptions.PcieAspmBlackListEnable == 1) { + PcieAspmBlackListFeature (&LinkAsmp, StdHeader); + } + //AgesaPcieLinkAspm (&LinkAsmp, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n", + (LinkAsmp.UpstreamAspm) , + LinkAsmp.UpstreamPort.Address.Bus, + LinkAsmp.UpstreamPort.Address.Device, + LinkAsmp.UpstreamPort.Address.Function + ); + IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n", + (LinkAsmp.DownstreamAspm) , + LinkAsmp.DownstreamPort.Address.Bus, + LinkAsmp.DownstreamPort.Address.Device, + LinkAsmp.DownstreamPort.Address.Function + ); + // Disable ASPM Upstream component + PcieAspmEnableOnDevice (Upstream, AspmDisabled, StdHeader); + // Enable ASPM Donstream component + PcieAspmEnableOnFunction (Downstream, LinkAsmp.DownstreamAspm, StdHeader); + // Enable ASPM Upstream component + PcieAspmEnableOnDevice (Upstream, LinkAsmp.UpstreamAspm, StdHeader); +} + + + +/**----------------------------------------------------------------------------------------*/ +/** + * Port/Endpoint ASMP capability + * + * + * + * @param[in] Device PCI address of downstream port + * @param[in] StdHeader Standard configuration header + * + * @retval PCIE_ASPM_TYPE + */ + /*----------------------------------------------------------------------------------------*/ +PCIE_ASPM_TYPE +PcieAspmGetPmCapability ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + UINT32 Value; + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr == 0) { + return 0; + } + GnbLibPciRead ( + Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), + AccessWidth32, + &Value, + StdHeader + ); + return (Value >> 10) & 3; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAspmPortInitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled && + !PcieConfigIsSbPcieEngine (Engine) && + PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PcieLinkAspmEnable ( + Engine->Type.Port.Address, + Engine->Type.Port.PortData.LinkAspm, + GnbLibGetHeader (Pcie) + ); + } +} + + +/**----------------------------------------------------------------------------------------*/ +/** + * Interface to enable Clock Power Managment + * + * + * + * @param[in] StdHeader Standard configuration header + * + * @retval AGESA_STATUS + */ + /*----------------------------------------------------------------------------------------*/ +AGESA_STATUS +PcieAspmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAspmInterface Enter\n"); + AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie); + if (AgesaStatus == AGESA_SUCCESS) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAspmPortInitCallback, + NULL, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAspmInterface Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h new file mode 100644 index 0000000000..16bf03ec4a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h @@ -0,0 +1,90 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link ASPM + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEASPM_H_ +#define _PCIEASPM_H_ + +VOID +PcieLinkAspmEnable ( + IN PCI_ADDR DownstreamPort, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieAspmEnableOnFunction ( + IN PCI_ADDR Function, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c new file mode 100644 index 0000000000..d268915b5a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c @@ -0,0 +1,353 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe Clock Power Managment + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "PcieClkPm.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable Clock Power Managment on function of the device + * + * + * + * @param[in] Function PCI address of function. + * @param[in] StdHeader Standard configuration header + * + */ + /*----------------------------------------------------------------------------------------*/ +STATIC VOID +PcieClkPmEnableOnFunction ( + IN PCI_ADDR Function, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRMW ( + Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER), + AccessS3SaveWidth32, + (UINT32)~(BIT8), + BIT8, + StdHeader + ); + } +} + + +/**----------------------------------------------------------------------------------------*/ +/** + * check capability of intire device including its functions + * + * + * + * @param[in] Device PCI address of downstream port + * @param[in] StdHeader Standard configuration header + * + * @retval TRUE - Device support Clock Power Managment + */ + /*----------------------------------------------------------------------------------------*/ +STATIC BOOLEAN +PcieClkPmCheckDeviceCapability ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + UINT8 MaxFunc; + UINT8 CurrentFunc; + UINT8 PcieCapPtr; + UINT32 Value; + + MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; + + for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { + Device.Address.Function = CurrentFunc; + if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr == 0) { + return FALSE; + } + GnbLibPciRead ( + Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), + AccessWidth32, + &Value, + StdHeader + ); + if ((Value & BIT18) == 0) { + return FALSE; + } + } + } + return TRUE; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Clock power managment on device + * + * + * + * @param[in] Device PCI address of device. + * @param[in] StdHeader Standard configuration header + * + */ + /*----------------------------------------------------------------------------------------*/ +STATIC VOID +PcieClkPmEnableOnDevice ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxFunc; + UINT8 CurrentFunc; + if (PcieClkPmCheckDeviceCapability (Device, StdHeader)) { + MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; + for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { + Device.Address.Function = CurrentFunc; + if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { + IDS_HDT_CONSOLE (GNB_TRACE, " Enable Clock Power Managment for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + PcieClkPmEnableOnFunction (Device, StdHeader); + } + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +STATIC SCAN_STATUS +PcieClkPmCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + PCIE_DEVICE_TYPE DeviceType; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " PcieClkPmCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + ScanStatus = SCAN_SUCCESS; + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, ScanData); + break; + case PcieDeviceUpstreamPort: + PcieClkPmEnableOnDevice (Device, ScanData->StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, ScanData); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + PcieClkPmEnableOnDevice (Device, ScanData->StdHeader); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + default: + break; + } + return ScanStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Confiugure Clock Power Managment + * + * + * + * + * @param[in] DownstreamPort Downstream port PCI address + * @param[in] StdHeader Standard configuration header + * + */ + +VOID +STATIC +PcieClkPmPortInitConfigure ( + IN PCI_ADDR DownstreamPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GNB_PCI_SCAN_DATA ScanData; + ScanData.StdHeader = StdHeader; + ScanData.GnbScanCallback = PcieClkPmCallback; + GnbLibPciScan (DownstreamPort, DownstreamPort, &ScanData); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieClkPmPortInitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (Engine->Type.Port.PortData.MiscControls.ClkPmSupport == 0x1 && + !PcieConfigIsSbPcieEngine (Engine) && + PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PcieClkPmPortInitConfigure ( + Engine->Type.Port.Address, + GnbLibGetHeader (Pcie) + ); + } +} + +/**----------------------------------------------------------------------------------------*/ +/** + * Interface to enable Clock Power Managment + * + * + * + * @param[in] StdHeader Standard configuration header + * + * @retval AGESA_STATUS + */ + /*----------------------------------------------------------------------------------------*/ +AGESA_STATUS +PcieClkPmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieClkPmInterface Enter\n"); + AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie); + if (AgesaStatus == AGESA_SUCCESS) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieClkPmPortInitCallback, + NULL, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieClkPmInterface Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h new file mode 100644 index 0000000000..3d14ac8abc --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link ASPM + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIECLKPM_H_ +#define _PCIECLKPM_H_ + +AGESA_STATUS +PcieClkPmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c new file mode 100644 index 0000000000..4b354caba4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c @@ -0,0 +1,162 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate/manes GNB/PCIe configuration + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get GNB handle + * + * + * @param[in] StdHeader Standard configuration header + */ +GNB_HANDLE * +GnbGetHandle ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_PLATFORM_CONFIG *Pcie; + GNB_HANDLE *GnbHandle; + AGESA_STATUS Status; + GnbHandle = NULL; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + GnbHandle = (GNB_HANDLE *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header); + } + return GnbHandle; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get GNB socket ID + * + * + * @param[in] GnbHandle Gnb handle + */ +UINT8 +GnbGetSocketId ( + IN GNB_HANDLE *GnbHandle + ) +{ + return PcieConfigGetParentComplex (GnbHandle)->SocketId; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Get PCI_ADDR of GNB + * + * + * @param[in] Handle Pointer to GNB_HANDLE + * @retval PCI_ADDR PCI_ADDR of device + */ + +PCI_ADDR +GnbGetHostPciAddress ( + IN GNB_HANDLE *Handle + ) +{ + ASSERT (Handle != NULL); + return Handle->Address; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h new file mode 100644 index 0000000000..affaa8c0ab --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h @@ -0,0 +1,101 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBHANDLELIB_H_ +#define _GNBHANDLELIB_H_ + + +GNB_HANDLE * +GnbGetHandle ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbGetSocketId ( + IN GNB_HANDLE *GnbHandle + ); + +PCI_ADDR +GnbGetHostPciAddress ( + IN GNB_HANDLE *Handle + ); + + +#define GnbGetNextHandle(Descriptor) (GNB_HANDLE *) PcieConfigGetNextTopologyDescriptor (Descriptor, DESCRIPTOR_TERMINATE_TOPOLOGY) + +#define GnbGetSiliconId(Handle) (Handle != NULL ? (Handle)->SiliconId : 0) +#define GnbGetNodeId(Handle) (Handle != NULL ? (Handle)->NodeId : 0) + +#define GnbIsGnbConnectedToSb(Handle) (Handle != NULL ? ((Handle)->Address.AddressValue == 0x0) : FALSE) + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h new file mode 100644 index 0000000000..9074aba624 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe configuration + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBPCIECONFIG_H_ +#define _GNBPCIECONFIG_H_ + +#include "GnbPcie.h" +#include "PcieConfigData.h" +#include "PcieConfigLib.h" +#include "GnbHandleLib.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c new file mode 100644 index 0000000000..febae7f986 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c @@ -0,0 +1,561 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "OptionGnb.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbFamServices.h" +#include "cpuServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "PcieMapTopology.h" +#include "PcieInputParser.h" +#include "PcieConfigLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +#define PcieConfigAttachChild(P, C) (P)->Child = (UINT16) ((UINT8 *) C - (UINT8 *) P); +#define PcieConfigAttachParent(P, C) (C)->Parent = (UINT16) ((UINT8 *) C - (UINT8 *) P); + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +PcieConfigAttachComplexes ( + IN OUT PCIe_COMPLEX_CONFIG *Base, + IN OUT PCIe_COMPLEX_CONFIG *New + ); + +AGESA_STATUS +PcieUpdateConfigurationData ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +PCIe_COMPLEX_DESCRIPTOR * +PcieConfigProcessUserConfig ( + IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieConfigurationInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieConfigurationMap ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Create internal PCIe configuration topology + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_SUCCESS Configuration data successfully allocated. + * @retval AGESA_FATAL Configuration data allocation failed. + */ + +AGESA_STATUS +PcieConfigurationInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_SILICON_CONFIG *Silicon; + UINT8 SocketId; + UINTN CurrentComplexesDataLength; + UINTN ComplexesDataLength; + UINT8 ComplexIndex; + VOID *Buffer; + ComplexesDataLength = 0; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Enter\n"); + for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) { + if (IsProcessorPresent (SocketId, StdHeader)) { + Status = PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + ComplexesDataLength += CurrentComplexesDataLength; + } + } + ComplexIndex = 0; + Pcie = GnbAllocateHeapBufferAndClear (AMD_PCIE_COMPLEX_DATA_HANDLE, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader); + ASSERT (Pcie != NULL); + if (Pcie != NULL) { + PcieConfigAttachChild (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header); + PcieConfigSetDescriptorFlags (Pcie, DESCRIPTOR_PLATFORM | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_TOPOLOGY); + Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG); + for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) { + if (IsProcessorPresent (SocketId, StdHeader)) { + Pcie->ComplexList[ComplexIndex].SocketId = SocketId; + //Attache Comples to Silicon which will be created by PcieFmBuildComplexConfiguration + PcieConfigAttachChild (&Pcie->ComplexList[ComplexIndex].Header, &((PCIe_SILICON_CONFIG *) Buffer)->Header); + //Attach Comples to Pcie + PcieConfigAttachParent (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header); + PcieConfigSetDescriptorFlags (&Pcie->ComplexList[ComplexIndex], DESCRIPTOR_COMPLEX | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY); + PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); + Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[ComplexIndex]); + while (Silicon != NULL) { + PcieConfigAttachParent (&Pcie->ComplexList[ComplexIndex].Header, &Silicon->Header); + GetNodeId (SocketId, Silicon->SiliconId, &Silicon->NodeId, StdHeader); + GnbFmGetLinkId ((GNB_HANDLE*) Silicon, &Silicon->LinkId, StdHeader); + Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY); + } + + if (ComplexIndex > 0) { + PcieConfigAttachComplexes (&Pcie->ComplexList[ComplexIndex - 1], &Pcie->ComplexList[ComplexIndex]); + } + PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); + Buffer = (VOID *) ((UINT8 *) Buffer + CurrentComplexesDataLength); + ComplexIndex++; + } + } + } else { + Status = AGESA_FATAL; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create internal PCIe configuration topology + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_SUCCESS Configuration data successfully allocated. + * @retval AGESA_FATAL Configuration data allocation failed. + */ + +AGESA_STATUS +PcieConfigurationMap ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_EARLY_PARAMS *EarlyParamsPtr; + PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor; + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + UINTN Index; + UINTN NumberOfComplexes; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationMap Enter\n"); + AgesaStatus = AGESA_SUCCESS; + EarlyParamsPtr = (AMD_EARLY_PARAMS *) StdHeader; + PcieComplexList = PcieConfigProcessUserConfig (EarlyParamsPtr->GnbConfig.PcieComplexList, StdHeader); + GNB_DEBUG_CODE ( + if (PcieComplexList != NULL) { + PcieUserConfigConfigDump (PcieComplexList); + } + ); + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header); + NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); + while (Complex != NULL) { + for (Index = 0; Index < NumberOfComplexes; Index++) { + ComplexDescriptor = PcieInputParserGetComplexDescriptor (PcieComplexList, Index); + if (ComplexDescriptor->SocketId == Complex->SocketId) { + Status = PcieMapTopologyOnComplex (ComplexDescriptor, Complex, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + } + Complex = PcieLibGetNextDescriptor (Complex); + } + } + Pcie->LinkReceiverDetectionPooling = GnbBuildOptions.CfgGnbLinkReceiverDetectionPooling; + Pcie->LinkL0Pooling = GnbBuildOptions.CfgGnbLinkL0Pooling; + Pcie->LinkGpioResetAssertionTime = GnbBuildOptions.CfgGnbLinkGpioResetAssertionTime; + Pcie->LinkResetToTrainingTime = GnbBuildOptions.CfgGnbLinkResetToTrainingTime; + Pcie->GfxCardWorkaround = GfxWorkaroundEnable; + Pcie->TrainingExitState = LinkStateTrainingCompleted; + Pcie->TrainingAlgorithm = GnbBuildOptions.CfgGnbTrainingAlgorithm; + if ((UserOptions.CfgAmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { + Pcie->GfxCardWorkaround = GfxWorkaroundDisable; + } + Pcie->PsppPolicy = EarlyParamsPtr->GnbConfig.PsppPolicy; + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG, Pcie, StdHeader); + GNB_DEBUG_CODE ( + PcieConfigDebugDump (Pcie); + ); + HeapDeallocateBuffer (AMD_GNB_TEMP_DATA_HANDLE, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate global PCIe configuration data + * + * + * + * @param[in] PcieComplexList User PCIe topology configuration + * @param[out] StdHeader Standard configuration header + * @retval Updated topology configuration + */ +PCIe_COMPLEX_DESCRIPTOR * +PcieConfigProcessUserConfig ( + IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Node0SocketId; + UINT32 Node0SiliconId; + UINTN NumberOfComplexes; + UINTN NumberOfPorts; + UINTN Index; + UINT16 DescriptorLoLane; + UINT16 DescriptorHiLane; + PCIe_COMPLEX_DESCRIPTOR *ResultComplexConfig; + PCIe_COMPLEX_DESCRIPTOR *SbComplexDescriptor; + PCIe_PORT_DESCRIPTOR *SbPortDescriptor; + PCIe_PORT_DESCRIPTOR DefaultSbPortDescriptor; + PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; + AGESA_STATUS Status; + SbPortDescriptor = NULL; + GetSocketModuleOfNode (0, &Node0SocketId, &Node0SiliconId, StdHeader); + Status = PcieFmGetSbConfigInfo ((UINT8) Node0SocketId, &DefaultSbPortDescriptor, StdHeader); + if (Status == AGESA_UNSUPPORTED) { + return PcieComplexList; + } + if (PcieComplexList == NULL) { + // No complex descriptor for any silicon was provided + // 1. Create complex descriptor + // 2. Create SB port descriptor + // 3. Attach SB descriptor to complex descriptor created in step #1 + ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( + AMD_GNB_TEMP_DATA_HANDLE, + sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + SbComplexDescriptor = ResultComplexConfig; + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR)); + LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); + SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + // Attach post array to complex descriptor + SbComplexDescriptor->PciePortList = SbPortDescriptor; + SbComplexDescriptor->SocketId = Node0SocketId; + SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + } else { + NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); + SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket (PcieComplexList, Node0SocketId); + if (SbComplexDescriptor == NULL) { + // No complex descriptor for silicon that have SB attached. + // 1. Create complex descriptor. Will be first one in the list + // 2. Create SB port descriptor + // 3. Attach SB descriptor to complex descriptor created in step #1 + ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( + AMD_GNB_TEMP_DATA_HANDLE, + (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + SbComplexDescriptor = ResultComplexConfig; + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR)); + LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); + SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + // Attach post array to complex descriptor + SbComplexDescriptor->PciePortList = SbPortDescriptor; + SbComplexDescriptor->SocketId = Node0SocketId; + SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + LibAmdMemCopy ( + (UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR), + PcieComplexList, + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), + StdHeader + ); + + } else { + // Complex descriptor that represent silicon that have SB attached exist + // 1. Determine if complex have descriptor for SB + // 2. Create new descriptor for SB if needed + NumberOfPorts = PcieInputParserGetLengthOfPcieEnginesList (SbComplexDescriptor); + ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBuffer ( + AMD_GNB_TEMP_DATA_HANDLE, + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + (NumberOfPorts + 1) * sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + // Copy complex descriptor array + LibAmdMemCopy ( + ResultComplexConfig, + PcieComplexList, + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), + StdHeader + ); + if (NumberOfPorts != 0) { + // Copy port descriptor array associated with complex with SB attached + LibAmdMemCopy ( + (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), + SbComplexDescriptor->PciePortList, + NumberOfPorts * sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + // Update SB complex pointer on in memory list + SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket ((PCIe_COMPLEX_DESCRIPTOR *) ResultComplexConfig, Node0SocketId); + // Attach port descriptor array to complex + SbComplexDescriptor->PciePortList = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR)); + for (Index = 0; Index < NumberOfPorts; ++Index) { + EngineDescriptor = PcieInputParserGetEngineDescriptor (SbComplexDescriptor, Index); + if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { + DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + if (DescriptorLoLane >= DefaultSbPortDescriptor.EngineData.StartLane && DescriptorLoLane <= DefaultSbPortDescriptor.EngineData.EndLane) { + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) EngineDescriptor; + } + } + } + } + if (SbPortDescriptor == NULL) { + // No descriptor that represent SB where found, create new one, will be first one in list + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); + // Copy default config info + LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); + // Reattach descriptor list to complex + SbComplexDescriptor->PciePortList = SbPortDescriptor; + } else { + // Move SB descriptor to be first one in array + LibAmdMemCopy ( + (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), + SbPortDescriptor, + sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + // Disable original SB descriptor + SbPortDescriptor->EngineData.EngineType = PcieUnusedEngine; + //Update pointer to new SB descriptor + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); + //It is no longer a descriptor that terminates list + SbPortDescriptor->Flags &= (~ DESCRIPTOR_TERMINATE_LIST); + // Reattach descriptor list to complex + SbComplexDescriptor->PciePortList = SbPortDescriptor; + } + } + } + // Mark descriptor as SB link + SbPortDescriptor->Port.MiscControls.SbLink = 0x1; + return ResultComplexConfig; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate global PCIe configuration data + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[out] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Configuration data successfully located + * @retval AGESA_FATAL Configuration can not be located. + */ +AGESA_STATUS +PcieLocateConfigurationData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT PCIe_PLATFORM_CONFIG **Pcie + ) +{ + *Pcie = GnbLocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, StdHeader); + if (*Pcie == NULL) { + IDS_ERROR_TRAP; + return AGESA_FATAL; + } + (*Pcie)->StdHeader = /* (PVOID) */ (UINT32)StdHeader; + PcieUpdateConfigurationData (*Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attache descriptors + * + * + * @param[in] Type Descriptor type + * @param[in,out] Base Base descriptor + * @param[in,out] New New descriptor + */ +VOID +STATIC +PcieConfigAttachDescriptors ( + IN UINT32 Type, + IN OUT PCIe_DESCRIPTOR_HEADER *Base, + IN OUT PCIe_DESCRIPTOR_HEADER *New + ) +{ + PCIe_DESCRIPTOR_HEADER *Left; + PCIe_DESCRIPTOR_HEADER *Right; + + Left = PcieConfigGetPeer (DESCRIPTOR_TERMINATE_GNB, PcieConfigGetChild (Type, Base)); + ASSERT (Left != NULL); + Right = PcieConfigGetChild (Type, New); + Left->Peer = (UINT16) ((UINT8 *) Right - (UINT8 *) Left); + PcieConfigResetDescriptorFlags (Left, DESCRIPTOR_TERMINATE_TOPOLOGY); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach configurations of two GNB to each other. + * + * Function will link all data structure to linked lists + * + * @param[in,out] Base Base complex descriptor + * @param[in,out] New New complex descriptor + */ +VOID +STATIC +PcieConfigAttachComplexes ( + IN OUT PCIe_COMPLEX_CONFIG *Base, + IN OUT PCIe_COMPLEX_CONFIG *New + ) +{ + // Connect Complex + Base->Header.Peer = (UINT16) ((UINT8 *) New - (UINT8 *) Base); + PcieConfigResetDescriptorFlags (Base, DESCRIPTOR_TERMINATE_TOPOLOGY); + // Connect Silicon + PcieConfigAttachDescriptors (DESCRIPTOR_SILICON, &Base->Header, &New->Header); + // Connect Wrappers + PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, &Base->Header, &New->Header); + // Connect Engines + PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, &Base->Header, &New->Header); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Update configuration data + * + * Puprouse of this structure to update config data that base on programming of + * other silicon compoments. For instance PCI address of GNB and PCIe ports + * can change by AGESA or external agent + * + * + * @param[in,out] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Configuration data successfully update + * @retval AGESA_FATAL Failt to update configuration + */ +AGESA_STATUS +PcieUpdateConfigurationData ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SILICON_CONFIG *Silicon; + PCIe_ENGINE_CONFIG *Engine; + PCI_ADDR NewAddress; + // Update silicon configuration + Silicon = PcieConfigGetChildSilicon (Pcie); + while (Silicon != NULL) { + NewAddress = GnbFmGetPciAddress ((GNB_HANDLE *) PcieConfigGetParentComplex (Silicon), GnbLibGetHeader (Pcie)); + if (Silicon->Address.AddressValue != NewAddress.AddressValue) { + Silicon->Address.AddressValue = NewAddress.AddressValue; + Engine = PcieConfigGetChildEngine (Silicon); + while (Engine != NULL) { + if (PcieConfigIsPcieEngine (Engine)) { + Engine->Type.Port.Address.Address.Bus = Silicon->Address.Address.Bus; + } + Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_GNB); + } + } + Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY); + } + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h new file mode 100644 index 0000000000..063d408245 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h @@ -0,0 +1,84 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIECONFIGDATA_H_ +#define _PCIECONFIGDATA_H_ + + +AGESA_STATUS +PcieLocateConfigurationData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT PCIe_PLATFORM_CONFIG **Pcie + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c new file mode 100644 index 0000000000..0083e80ad9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -0,0 +1,827 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 65589 $ @e \$Date: 2012-02-19 20:32:29 -0600 (Sun, 19 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "PcieMapTopology.h" +#include "PcieInputParser.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * get Master Lane of PCIe port engine + * + * + * + * @param[in] Engine Pointer to engine descriptor + * @retval Master Engine Lane Number + */ +UINT8 +PcieConfigGetPcieEngineMasterLane ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT8 MasterLane; + PCIe_WRAPPER_CONFIG *Wrapper; + ASSERT (PcieConfigIsPcieEngine (Engine)); + + Wrapper = PcieConfigGetParentWrapper (Engine); + if (Engine->EngineData.StartLane <= Engine->EngineData.EndLane) { + MasterLane = (UINT8) (Engine->EngineData.StartLane - Wrapper->StartPhyLane); + } else { + MasterLane = (UINT8) (Engine->EngineData.EndLane - Wrapper->StartPhyLane); + } + return MasterLane; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of core lanes + * + * + * + * @param[in] Engine Pointer to engine descriptor + * @retval Number of core lane + */ +UINT8 +PcieConfigGetNumberOfCoreLane ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + if (Engine->Type.Port.StartCoreLane >= UNUSED_LANE_ID || Engine->Type.Port.EndCoreLane >= UNUSED_LANE_ID) { + return 0; + } + return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Disable engine + * + * + * + * @param[in] Engine Pointer to engine config descriptor + */ +VOID +PcieConfigDisableEngine ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + if (PcieConfigIsSbPcieEngine (Engine)) { + return; + } + PcieConfigResetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Disable all engines on wrapper + * + * + * + * @param[in] EngineTypeMask Engine type bitmap. + * @param[in] Wrapper Pointer to wrapper config descriptor + */ +VOID +PcieConfigDisableAllEngines ( + IN UINTN EngineTypeMask, + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if ((EngineList->EngineData.EngineType & EngineTypeMask) != 0) { + PcieConfigDisableEngine (EngineList); + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get engine PHY lanes bitmap + * + * + * + * @param[in] Engine Pointer to engine config descriptor + */ +UINT32 +PcieConfigGetEnginePhyLaneBitMap ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT32 LaneBitMap; + LaneBitMap = 0; + if (PcieLibIsEngineAllocated (Engine)) { + LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane); + } + return LaneBitMap; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of phy lanes + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @retval Number of Phy lane + */ +UINT8 +PcieConfigGetNumberOfPhyLane ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) { + return 0; + } + if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) { + return (UINT8) (Engine->EngineData.StartLane - Engine->EngineData.EndLane + 1); + } else { + return (UINT8) (Engine->EngineData.EndLane - Engine->EngineData.StartLane + 1); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get port configuration signature for given wrapper and core + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] CoreId Core ID + * @retval Configuration Signature + */ +UINT64 +PcieConfigGetConfigurationSignature ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId + ) +{ + UINT64 ConfigurationSignature; + PCIe_ENGINE_CONFIG *EngineList; + ConfigurationSignature = 0; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieConfigIsPcieEngine (EngineList) && EngineList->Type.Port.CoreId == CoreId) { + ConfigurationSignature = (ConfigurationSignature << 8) | PcieConfigGetNumberOfCoreLane (EngineList); + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + return ConfigurationSignature; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check Port Status + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] PortStatus Check if status asserted for port + * @retval TRUE if status asserted + */ +BOOLEAN +PcieConfigCheckPortStatus ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT32 PortStatus + ) +{ + return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set/Reset port status + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] SetStatus SetStatus + * @param[in] ResetStatus ResetStatus + * + */ +UINT16 +PcieConfigUpdatePortStatus ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_ENGINE_INIT_STATUS SetStatus, + IN PCIe_ENGINE_INIT_STATUS ResetStatus + ) +{ + Engine->InitStatus |= SetStatus; + Engine->InitStatus &= (~ResetStatus); + return Engine->InitStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute callback on all descriptor of specific type + * + * + * @param[in] InDescriptorFlags Include descriptor flags + * @param[in] OutDescriptorFlags Exlude descriptor flags + * @param[in] TerminationFlags Termination flags + * @param[in] Callback Pointer to callback function + * @param[in, out] Buffer Pointer to buffer to pass information to callback + * @param[in] Pcie Pointer to global PCIe configuration + */ + +AGESA_STATUS +PcieConfigRunProcForAllDescriptors ( + IN UINT32 InDescriptorFlags, + IN UINT32 OutDescriptorFlags, + IN UINT32 TerminationFlags, + IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_DESCRIPTOR_HEADER *Descriptor; + + AgesaStatus = AGESA_SUCCESS; + Descriptor = PcieConfigGetChild (InDescriptorFlags & DESCRIPTOR_ALL_TYPES, &Pcie->Header); + while (Descriptor != NULL) { + if ((InDescriptorFlags & Descriptor->DescriptorFlags) != 0 && (OutDescriptorFlags && Descriptor->DescriptorFlags) == 0) { + Status = Callback (Descriptor, Buffer, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + Descriptor = (PCIe_DESCRIPTOR_HEADER *) PcieConfigGetNextTopologyDescriptor (Descriptor, TerminationFlags); + } + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute callback on all wrappers in topology + * + * + * @param[in] DescriptorFlags Wrapper Flags + * @param[in] Callback Pointer to callback function + * @param[in, out] Buffer Pointer to buffer to pass information to callback + * @param[in] Pcie Pointer to global PCIe configuration + */ + +AGESA_STATUS +PcieConfigRunProcForAllWrappers ( + IN UINT32 DescriptorFlags, + IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_WRAPPER_CONFIG *Wrapper; + + AgesaStatus = AGESA_SUCCESS; + Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header); + while (Wrapper != NULL) { + if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { + if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Header.DescriptorFlags) != 0) { + Status = Callback (Wrapper, Buffer, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + } + Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetNextTopologyDescriptor (Wrapper, DESCRIPTOR_TERMINATE_TOPOLOGY); + } + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute callback on all engine in topology + * + * + * @param[in] DescriptorFlags Engine flags. + * @param[in] Callback Pointer to callback function + * @param[in, out] Buffer Pointer to buffer to pass information to callback + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieConfigRunProcForAllEngines ( + IN UINT32 DescriptorFlags, + IN PCIe_RUN_ON_ENGINE_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + + PCIe_ENGINE_CONFIG *Engine; + Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &Pcie->Header); + while (Engine != NULL) { + if (!(PcieLibIsVirtualDesciptor (Engine) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { + if (!((DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0 && !PcieLibIsEngineAllocated (Engine))) { + if ((Engine->Header.DescriptorFlags & DESCRIPTOR_ALL_ENGINES & DescriptorFlags) != 0) { + Callback (Engine, Buffer, Pcie); + } + } + } + Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_TOPOLOGY); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get parent descriptor of specific type + * + * + * @param[in] Type Descriptor type + * @param[in] Descriptor Pointer to buffer to pass information to callback + */ +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetParent ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ) +{ + while ((Descriptor->DescriptorFlags & Type) == 0) { + if (Descriptor->Parent != 0) { + Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor - Descriptor->Parent); + } else { + return NULL; + } + } + return Descriptor; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get child descriptor of specific type + * + * + * @param[in] Type Descriptor type + * @param[in] Descriptor Pointer to buffer to pass information to callback + */ +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetChild ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ) +{ + while ((Descriptor->DescriptorFlags & Type) == 0) { + if (Descriptor->Child != 0) { + Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Child); + } else { + return NULL; + } + } + return Descriptor; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get peer descriptor of specific type + * + * + * @param[in] Type Descriptor type + * @param[in] Descriptor Pointer to buffer to pass information to callback + */ +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetPeer ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ) +{ + ASSERT (Descriptor != NULL); + while ((Descriptor->DescriptorFlags & Type) == 0) { + if (Descriptor->Peer != 0) { + Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Peer); + } else { + return NULL; + } + } + return Descriptor; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check is engine is active or potentially active + * + * + * + * @param[in] Engine Pointer to engine descriptor + * @retval TRUE - engine active + * @retval FALSE - engine not active + */ +BOOLEAN +PcieConfigIsActivePcieEngine ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + BOOLEAN Result; + ASSERT (PcieConfigIsPcieEngine (Engine)); + Result = FALSE; + if (PcieConfigIsEngineAllocated (Engine)) { + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || + (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled && Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) { + Result = TRUE; + } + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate SB engine on wrapper + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @retval SB engine pointer or NULL + */ +PCIe_ENGINE_CONFIG * +PcieConfigLocateSbEngine ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieConfigIsSbPcieEngine (EngineList)) { + return EngineList; + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + return NULL; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump engine configuration + * + * + * @param[in] EngineList Engine Configuration + */ +VOID +PcieConfigEngineDebugDump ( + IN PCIe_ENGINE_CONFIG *EngineList + ) +{ + IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", EngineList->Header.DescriptorFlags); + IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n Start Phy Lane - %d\n End Phy Lane - %d\n", + ((EngineList->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : "DDI Link"), + EngineList->EngineData.StartLane, + EngineList->EngineData.EndLane + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Scrath - %d\n", EngineList->Scratch); + IDS_HDT_CONSOLE (PCIE_MISC, " Init Status - 0x%08x\n", EngineList->InitStatus); + if (PcieLibIsPcieEngine (EngineList)) { + IDS_HDT_CONSOLE (PCIE_MISC, " PCIe port configuration:\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " Port Training - %s\n", + (EngineList->Type.Port.PortData.PortPresent == PortDisabled) ? "Disable" : "Enabled" + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Start Core Lane - %d\n", EngineList->Type.Port.StartCoreLane); + IDS_HDT_CONSOLE (PCIE_MISC, " End Core Lane - %d\n", EngineList->Type.Port.EndCoreLane); + IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Dev Number - %d\n",EngineList->Type.Port.PortData.DeviceNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Func Number - %d\n",EngineList->Type.Port.PortData.FunctionNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " PCI Address - %d:%d:%d\n", + EngineList->Type.Port.Address.Address.Bus, + EngineList->Type.Port.Address.Address.Device, + EngineList->Type.Port.Address.Address.Function + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control - 0x%02x\n", EngineList->Type.Port.PortData.MiscControls); + IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n", + (EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) ? "Disabled" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugBasic) ? "Basic" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugServer) ? "Server" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugEnhanced) ? "Enhanced" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard) ? "Inboard" : "Unknown")))) + ); + ASSERT (EngineList->Type.Port.PortData.LinkHotplug < MaxHotplug); + IDS_HDT_CONSOLE (PCIE_MISC, " ASPM - %s\n", + (EngineList->Type.Port.PortData.LinkAspm == AspmDisabled) ? "Disabled" : ( + (EngineList->Type.Port.PortData.LinkAspm == AspmL0s) ? "L0s" : ( + (EngineList->Type.Port.PortData.LinkAspm == AspmL1) ? "L1" : ( + (EngineList->Type.Port.PortData.LinkAspm == AspmL0sL1) ? "L0s & L1" : "Unknown"))) + ); + ASSERT (EngineList->Type.Port.PortData.LinkAspm < MaxAspm); + IDS_HDT_CONSOLE (PCIE_MISC, " Speed - %d\n", + EngineList->Type.Port.PortData.LinkSpeedCapability + ); + } else { + IDS_HDT_CONSOLE (PCIE_MISC, " DDI configuration:\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " Connector - %s\n", + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) ? "DP" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) ? "eDP" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDVI) ? "Single Link DVI" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) ? "Dual Link DVI" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) ? "HDMI" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToVga) ? "Travis DP-to-VGA" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToLvds) ? "Travis DP-to-LVDS" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds) ? "LVDS" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeNutmegDpToVga) ? "Hudson-2 Nutmeg DP-to-VGA" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) ? "Single Link DVI-I" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeCrt) ? "CRT" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) ? "eDP To Lvds" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToRealtecLvds) ? "Realtec eDP To Lvds" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect) ? "Autodetect" : "Unknown"))))))))))))) + ); + ASSERT (EngineList->Type.Ddi.DdiData.ConnectorType < MaxConnectorType); + IDS_HDT_CONSOLE (PCIE_MISC, " Aux - Aux%d\n", EngineList->Type.Ddi.DdiData.AuxIndex + 1); + ASSERT (EngineList->Type.Ddi.DdiData.AuxIndex < MaxAux); + IDS_HDT_CONSOLE (PCIE_MISC, " Hdp - Hdp%d\n", EngineList->Type.Ddi.DdiData.HdpIndex + 1); + ASSERT (EngineList->Type.Ddi.DdiData.HdpIndex < MaxHdp); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump wrapper configuration + * + * + * @param[in] WrapperList Wrapper Configuration + */ +VOID +PcieConfigWrapperDebugDump ( + IN PCIe_WRAPPER_CONFIG *WrapperList + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config -------->\n", + PcieFmDebugGetWrapperNameString (WrapperList) + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Start PHY lane - %02d\n", WrapperList->StartPhyLane); + IDS_HDT_CONSOLE (PCIE_MISC, " End PHY lane - %02d\n", WrapperList->EndPhyLane); + IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", WrapperList->Header.DescriptorFlags); + IDS_HDT_CONSOLE (PCIE_MISC, " PowerOffUnusedLanes - %x\n PowerOffUnusedPlls - %x\n ClkGating - %x\n" + " LclkGating - %x\n TxclkGatingPllPowerDown - %x\n PllOffInL1 - %x\n", + WrapperList->Features.PowerOffUnusedLanes, + WrapperList->Features.PowerOffUnusedPlls, + WrapperList->Features.ClkGating, + WrapperList->Features.LclkGating, + WrapperList->Features.TxclkGatingPllPowerDown, + WrapperList->Features.PllOffInL1 + ); + IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config End----->\n", + PcieFmDebugGetWrapperNameString (WrapperList) + ); + EngineList = PcieConfigGetChildEngine (WrapperList); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + PcieConfigEngineDebugDump (EngineList); + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump configuration to debug out + * + * + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieConfigDebugDump ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SILICON_CONFIG *SiliconList; + PCIe_WRAPPER_CONFIG *WrapperList; + PCIe_COMPLEX_CONFIG *ComplexList; + ComplexList = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header); + IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config Start------------>\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " PSPP Policy - %s\n", + (Pcie->PsppPolicy == PsppPowerSaving) ? "Power Saving" : + (Pcie->PsppPolicy == PsppBalanceHigh) ? "Balance-High" : ( + (Pcie->PsppPolicy == PsppBalanceLow) ? "Balance-Low" : ( + (Pcie->PsppPolicy == PsppPerformance) ? "Performance" : ( + (Pcie->PsppPolicy == PsppDisabled) ? "Disabled" : "Unknown"))) + ); + IDS_HDT_CONSOLE (PCIE_MISC, " GFX Workaround - %s\n", + (Pcie->GfxCardWorkaround == 0) ? "Disabled" : "Enabled" + ); + IDS_HDT_CONSOLE (PCIE_MISC, " LinkL0Pooling - %dus\n", + Pcie->LinkL0Pooling + ); + IDS_HDT_CONSOLE (PCIE_MISC, " LinkGpioResetAssertionTime - %dus\n", + Pcie->LinkGpioResetAssertionTime + ); + IDS_HDT_CONSOLE (PCIE_MISC, " LinkReceiverDetectionPooling - %dus\n", + Pcie->LinkReceiverDetectionPooling + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Training Algorythm - %s\n", + (Pcie->TrainingAlgorithm == PcieTrainingStandard) ? "PcieTrainingStandard" : ( + (Pcie->TrainingAlgorithm == PcieTrainingDistributed) ? "PcieTrainingDistributed" : "Unknown") + ); + while (ComplexList != NULL) { + IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config Start ---------->\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", ComplexList->Header.DescriptorFlags); + IDS_HDT_CONSOLE (PCIE_MISC, " Socket ID - %d\n", ComplexList->SocketId); + SiliconList = PcieConfigGetChildSilicon (ComplexList); + while (SiliconList != NULL) { + IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config Start -------->\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", SiliconList->Header.DescriptorFlags); + IDS_HDT_CONSOLE (PCIE_MISC, " Silicon ID - %d\n", SiliconList->SiliconId); + IDS_HDT_CONSOLE (PCIE_MISC, " Node ID - %d\n", SiliconList->NodeId); + IDS_HDT_CONSOLE (PCIE_MISC, " Host PCI Address - %d:%d:%d\n", + SiliconList->Address.Address.Bus, + SiliconList->Address.Address.Device, + SiliconList->Address.Address.Function + ); + WrapperList = PcieConfigGetChildWrapper (SiliconList); + while (WrapperList != NULL) { + PcieConfigWrapperDebugDump (WrapperList); + WrapperList = PcieLibGetNextDescriptor (WrapperList); + } + IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config End ---------->\n"); + SiliconList = PcieLibGetNextDescriptor (SiliconList); + } + IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config End ------------>\n"); + ComplexList = PcieLibGetNextDescriptor (ComplexList); + } + IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config End-------------->\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump input configuration to user engine descriptor + * + * + * @param[in] EngineDescriptor Pointer to engine descriptor + */ +VOID +PcieUserDescriptorConfigDump ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor + ) +{ + + IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n", + (EngineDescriptor->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : ( + (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) ? "DDI Link" : ( + (EngineDescriptor->EngineData.EngineType == PcieUnusedEngine) ? "Unused" : "Invalid")) + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Start Phy Lane - %d\n End Phy Lane - %d\n", + EngineDescriptor->EngineData.StartLane, + EngineDescriptor->EngineData.EndLane + ); + if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { + IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n SB link - %d\n MiscControls - 0x%02x\n" , + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.FunctionNumber, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkSpeedCapability, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls + ); + } + if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { + IDS_HDT_CONSOLE (PCIE_MISC, " ConnectorType - %d\n AuxIndex - %d\n HdpIndex - %d\n" , + ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.ConnectorType, + ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.AuxIndex, + ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.HdpIndex + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump input configuration to debug out + * + * + * @param[in] ComplexDescriptor Pointer to user defined complex descriptor + */ +VOID +PcieUserConfigConfigDump ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor + ) +{ + PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; + PCIe_COMPLEX_DESCRIPTOR *CurrentComplexDescriptor; + UINTN ComplexIndex; + UINTN Index; + UINTN NumberOfEngines; + UINTN NumberOfComplexes; + + IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config Start------------->\n"); + + NumberOfComplexes = PcieInputParserGetNumberOfComplexes (ComplexDescriptor); + for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) { + CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex); + NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor); + IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n", + ComplexDescriptor->SocketId, + NumberOfEngines + ); + + for (Index = 0; Index < NumberOfEngines; Index++) { + EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index); + PcieUserDescriptorConfigDump (EngineDescriptor); + } + } + IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n"); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h new file mode 100644 index 0000000000..4a732dce78 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h @@ -0,0 +1,248 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIECONFIGLIB_H_ +#define _PCIECONFIGLIB_H_ + +typedef VOID (*PCIe_RUN_ON_ENGINE_CALLBACK) ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +typedef AGESA_STATUS (*PCIe_RUN_ON_WRAPPER_CALLBACK) ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +typedef AGESA_STATUS (*PCIe_RUN_ON_DESCRIPTOR_CALLBACK) ( + IN PCIe_DESCRIPTOR_HEADER *Descriptor, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT8 +PcieConfigGetPcieEngineMasterLane ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT8 +PcieConfigGetNumberOfCoreLane ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +VOID +PcieConfigDisableAllEngines ( + IN UINTN EngineTypeMask, + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +VOID +PcieConfigDisableEngine ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT32 +PcieConfigGetEnginePhyLaneBitMap ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT8 +PcieConfigGetNumberOfPhyLane ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT64 +PcieConfigGetConfigurationSignature ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId + ); + +BOOLEAN +PcieConfigCheckPortStatus ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT32 PortStatus + ); + +UINT16 +PcieConfigUpdatePortStatus ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_ENGINE_INIT_STATUS SetStatus, + IN PCIe_ENGINE_INIT_STATUS ResetStatus + ); + +VOID +PcieConfigRunProcForAllEngines ( + IN UINT32 DescriptorFlags, + IN PCIe_RUN_ON_ENGINE_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieConfigRunProcForAllWrappers ( + IN UINT32 DescriptorFlags, + IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieConfigRunProcForAllDescriptors ( + IN UINT32 InDescriptorFlags, + IN UINT32 OutDescriptorFlags, + IN UINT32 TerminationFlags, + IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetParent ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ); + +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetChild ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ); + +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetPeer ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ); + +BOOLEAN +PcieConfigIsActivePcieEngine ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +PCIe_ENGINE_CONFIG * +PcieConfigLocateSbEngine ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +VOID +PcieConfigDebugDump ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieConfigWrapperDebugDump ( + IN PCIe_WRAPPER_CONFIG *WrapperList + ); + +VOID +PcieConfigEngineDebugDump ( + IN PCIe_ENGINE_CONFIG *EngineList + ); + +VOID +PcieUserConfigConfigDump ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor + ); + +VOID +PcieUserDescriptorConfigDump ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor + ); + +#define PcieConfigGetParentWrapper(Descriptor) ((PCIe_WRAPPER_CONFIG *) PcieConfigGetParent (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header))) +#define PcieConfigGetParentSilicon(Descriptor) ((PCIe_SILICON_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &((Descriptor)->Header))) +#define PcieConfigGetParentComplex(Descriptor) ((PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &((Descriptor)->Header))) +#define PcieConfigGetPlatform(Descriptor) ((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header))) +#define PcieConfigGetChildWrapper(Descriptor) ((PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header))) +#define PcieConfigGetChildEngine(Descriptor) ((PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &((Descriptor)->Header))) +#define PcieConfigGetChildSilicon(Descriptor) ((PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &((Descriptor)->Header))) +#define PcieConfigGetNextDescriptor(Descriptor) ((((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (++Descriptor))) +#define PcieConfigIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : FALSE) +#define PcieConfigIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : FALSE) +#define PcieConfigIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : FALSE) +#define PcieConfigIsSbPcieEngine(Engine) (Engine != NULL ? ((BOOLEAN) (Engine->Type.Port.PortData.MiscControls.SbLink)) : FALSE) +#define PcieConfigIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : FALSE) +#define PcieConfigIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : FALSE) +#define PcieConfigIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : FALSE) +#define PcieConfigSetDescriptorFlags(Descriptor, SetDescriptorFlags) if (Descriptor != NULL) (Descriptor)->Header.DescriptorFlags |= SetDescriptorFlags +#define PcieConfigResetDescriptorFlags(Descriptor, ResetDescriptorFlags) if (Descriptor != NULL) ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags &= (~(ResetDescriptorFlags)) +#define PcieInputParsetGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL) +#define PcieConfigGetNextTopologyDescriptor(Descriptor, Termination) (Descriptor != NULL ? (((((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags & Termination) != 0) ? NULL : ((UINT8 *) Descriptor + ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->Peer)) : NULL) +#define GnbGetNextHandle(Descriptor) (GNB_HANDLE *) PcieConfigGetNextTopologyDescriptor (Descriptor, DESCRIPTOR_TERMINATE_TOPOLOGY) +#define PcieConfigGetNextDataDescriptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0 ? NULL : ++Descriptor) + +#define PcieConfigGetStdHeader(Descriptor) ((AMD_CONFIG_PARAMS *)((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header)))->StdHeader) + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c new file mode 100644 index 0000000000..b4b6106772 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c @@ -0,0 +1,275 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Procedure to parse PCIe input configuration data + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "PcieInputParser.h" +#include "PcieConfigLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of complexes in platform topology configuration + * + * + * + * @param[in] ComplexList First complex configuration in complex configuration array + * @retval Number of Complexes + * + */ +UINTN +PcieInputParserGetNumberOfComplexes ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList + ) +{ + UINTN Result; + Result = 0; + while (ComplexList != NULL) { + Result++; + ComplexList = PcieInputParsetGetNextDescriptor (ComplexList); + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of PCIe engines in given complex + * + * + * + * @param[in] Complex Complex configuration + * @retval Number of Engines + */ +UINTN +PcieInputParserGetLengthOfPcieEnginesList ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ) +{ + UINTN Result; + PCIe_PORT_DESCRIPTOR *PciePortList; + Result = 0; + PciePortList = Complex->PciePortList; + while (PciePortList != NULL) { + Result++; + PciePortList = PcieInputParsetGetNextDescriptor (PciePortList); + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of DDI engines in given complex + * + * + * + * @param[in] Complex Complex configuration + * @retval Number of Engines + */ +STATIC UINTN +PcieInputParserGetLengthOfDdiEnginesList ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ) +{ + UINTN Result; + PCIe_DDI_DESCRIPTOR *DdiLinkList; + Result = 0; + DdiLinkList = Complex->DdiLinkList; + while (DdiLinkList != NULL) { + Result++; + DdiLinkList = PcieInputParsetGetNextDescriptor (DdiLinkList); + } + return Result; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of engines in given complex + * + * + * + * @param[in] Complex Complex configuration header + * @retval Number of Engines + */ +UINTN +PcieInputParserGetNumberOfEngines ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ) +{ + UINTN Result; + + Result = PcieInputParserGetLengthOfDdiEnginesList (Complex) + + PcieInputParserGetLengthOfPcieEnginesList (Complex); + return Result; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Complex descriptor by index from given Platform configuration + * + * + * + * @param[in] ComplexList Platform topology configuration + * @param[in] Index Complex descriptor Index + * @retval Pointer to Complex Descriptor + */ +PCIe_COMPLEX_DESCRIPTOR* +PcieInputParserGetComplexDescriptor ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, + IN UINTN Index + ) +{ + ASSERT (Index < (PcieInputParserGetNumberOfComplexes (ComplexList))); + return &ComplexList[Index]; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Complex descriptor by index from given Platform configuration + * + * + * + * @param[in] ComplexList Platform topology configuration + * @param[in] SocketId Socket Id + * @retval Pointer to Complex Descriptor + */ +PCIe_COMPLEX_DESCRIPTOR* +PcieInputParserGetComplexDescriptorOfSocket ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, + IN UINT32 SocketId + ) +{ + PCIe_COMPLEX_DESCRIPTOR *Result; + Result = NULL; + while (ComplexList != NULL) { + if (ComplexList->SocketId == SocketId) { + Result = ComplexList; + break; + } + ComplexList = PcieInputParsetGetNextDescriptor (ComplexList); + } + return Result; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Engine descriptor from given complex by index + * + * + * + * @param[in] Complex Complex descriptor + * @param[in] Index Engine descriptor index + * @retval Pointer to Engine Descriptor + */ +PCIe_ENGINE_DESCRIPTOR* +PcieInputParserGetEngineDescriptor ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex, + IN UINTN Index + ) +{ + UINTN PcieListlength; + ASSERT (Index < (PcieInputParserGetNumberOfEngines (Complex))); + PcieListlength = PcieInputParserGetLengthOfPcieEnginesList (Complex); + if (Index < PcieListlength) { + return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->PciePortList)[Index]); + } else { + return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h new file mode 100644 index 0000000000..630f9ae187 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h @@ -0,0 +1,110 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Procedure to parse PCIe input configuration data + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEINPUTPARSER_H_ +#define _PCIEINPUTPARSER_H_ + + +UINTN +PcieInputParserGetNumberOfComplexes ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList + ); + +UINTN +PcieInputParserGetNumberOfEngines ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ); + + +PCIe_COMPLEX_DESCRIPTOR* +PcieInputParserGetComplexDescriptor ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, + IN UINTN Index + ); + +PCIe_ENGINE_DESCRIPTOR* +PcieInputParserGetEngineDescriptor ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex, + IN UINTN Index + ); + +PCIe_COMPLEX_DESCRIPTOR* +PcieInputParserGetComplexDescriptorOfSocket ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, + IN UINT32 SocketId + ); + +UINTN +PcieInputParserGetLengthOfPcieEnginesList ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ); +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c new file mode 100644 index 0000000000..f1fc4b8ac5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c @@ -0,0 +1,672 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Procedure to map user define topology to processor configuration + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GeneralServices.h" +#include "PcieInputParser.h" +#include "PcieMapTopology.h" +#include "GnbPcieConfig.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +AGESA_STATUS +STATIC +PcieMapPortsPciAddresses ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieMapTopologyOnWrapper ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN OUT PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieMapInitializeEngineData ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN OUT PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +BOOLEAN +PcieCheckPortPciDeviceMapping ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +BOOLEAN +PcieIsDescriptorLinkWidthValid ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor + ); + +BOOLEAN +PcieCheckLanesMatch ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +BOOLEAN +PcieCheckDescriptorMapsToWrapper ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +VOID +PcieAllocateEngine ( + IN UINT8 DescriptorIndex, + IN PCIe_ENGINE_CONFIG *Engine + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] ComplexDescriptor Pointer to used define complex descriptor + * @param[in] Complex Pointer to complex descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +PcieMapTopologyOnComplex ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN PCIe_COMPLEX_CONFIG *Complex, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SILICON_CONFIG *Silicon; + PCIe_WRAPPER_CONFIG *Wrapper; + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n"); + Silicon = PcieConfigGetChildSilicon (Complex); + while (Silicon != NULL) { + Wrapper = PcieConfigGetChildWrapper (Silicon); + while (Wrapper != NULL) { + Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_ERROR) { + PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); + IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n", + PcieFmDebugGetWrapperNameString (Wrapper) + ); + ASSERT (FALSE); + } + Wrapper = PcieLibGetNextDescriptor (Wrapper); + } + Status = PcieMapPortsPciAddresses (Silicon, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + Silicon = PcieLibGetNextDescriptor (Silicon); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] EngineType Engine type + * @param[in] ComplexDescriptor Pointer to used define complex descriptor + * @param[in] Wrapper Pointer to wrapper config descriptor + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ +STATIC AGESA_STATUS +PcieEnginesToWrapper ( + IN PCIE_ENGINE_TYPE EngineType, + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + AGESA_STATUS Status; + PCIe_ENGINE_CONFIG *EngineList; + PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; + UINT8 ConfigurationId; + UINT8 Allocations; + UINTN Index; + UINTN NumberOfDescriptors; + + ConfigurationId = 0; + Allocations = 0; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Enter\n"); + NumberOfDescriptors = PcieInputParserGetNumberOfEngines (ComplexDescriptor); + do { + Status = PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId++); + if (Status == AGESA_SUCCESS) { + Allocations = 0; + for (Index = 0; Index < NumberOfDescriptors; Index++) { + EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index); + if (EngineDescriptor->EngineData.EngineType == EngineType) { + // Step 1, belongs to wrapper check. + if (PcieCheckDescriptorMapsToWrapper (EngineDescriptor, Wrapper)) { + ++Allocations; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (!PcieLibIsEngineAllocated (EngineList)) { + // Step 2.user descriptor less or equal to link width of engine + if (PcieCheckLanesMatch (EngineDescriptor, EngineList)) { + // Step 3, Check if link width is correct.x1, x2, x4, x8, x16. + if (!PcieIsDescriptorLinkWidthValid (EngineDescriptor)) { + PcieConfigDisableEngine (EngineList); + return AGESA_ERROR; + } + if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { + // Step 4, Family specifc, port device number match engine device + if (PcieCheckPortPciDeviceMapping ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) { + //Step 5, Family specifc, lanes can be muxed. + if (PcieFmCheckPortPcieLaneCanBeMuxed ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) { + PcieAllocateEngine ((UINT8) Index, EngineList); + --Allocations; + break; + } + } + } else { + PcieAllocateEngine ((UINT8) Index, EngineList); + --Allocations; + break; + } + } + } //end if PcieLibIsEngineAllocated + EngineList = PcieLibGetNextDescriptor (EngineList); + } + } //end if PcieCheckDescriptorMapsToWrapper + } // end if EngineType + } //end for + } + } while (Status == AGESA_SUCCESS && Allocations != 0); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Exit [%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) + * + * + * @param[in] EngineDescriptor Pointer to used define engine descriptor + * @param[in] Wrapper Pointer to PCIe_WRAPPER_CONFIG + * @retval TRUE Belongs to wrapper + * @retval FALSE Not belongs to wrapper + */ +BOOLEAN +PcieCheckDescriptorMapsToWrapper ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + BOOLEAN Result; + UINT16 DescriptorHiLane; + UINT16 DescriptorLoLane; + UINT16 DescriptorNumberOfLanes; + + DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; + Result = FALSE; + + if (Wrapper->StartPhyLane <= DescriptorLoLane && DescriptorHiLane <= Wrapper->EndPhyLane) { + // Lanes of descriptor belongs to wrapper + Result = TRUE; + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Engine to be allocated. + * + * + * @param[in] DescriptorIndex UINT8 index + * @param[in] Engine Pointer to engine config + */ +VOID +PcieAllocateEngine ( + IN UINT8 DescriptorIndex, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + PcieConfigSetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED); + Engine->Scratch = DescriptorIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * PCIE port + * + * + * 1 Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) + * 2 Check if link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG) + * 3 Check if link width is correct. Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8 + * 4 Check if user port device number (PCIe_PORT_DESCRIPTOR) match engine port device number (PCIe_ENGINE_CONFIG) + * 5 Check if lane can be muxed + * + * + * DDI Link + * + * 1 Check if lane from user port descriptor (PCIe_DDI_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) + * 2 Check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG) + * + * + * + * @param[in] ComplexDescriptor Pointer to used define complex descriptor + * @param[in,out] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ +AGESA_STATUS +PcieMapTopologyOnWrapper ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN OUT PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_ENGINE_CONFIG *EngineList; + UINT32 WrapperPhyLaneBitMap; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Enter\n"); + AgesaStatus = AGESA_SUCCESS; + if (PcieLibIsPcieWrapper (Wrapper)) { + Status = PcieEnginesToWrapper (PciePortEngine, ComplexDescriptor, Wrapper); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_ERROR) { + // If we can not map topology on wrapper we can not enable any engines. + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION, + Wrapper->WrapId, + Wrapper->StartPhyLane, + Wrapper->EndPhyLane, + 0, + GnbLibGetHeader (Pcie) + ); + PcieConfigDisableAllEngines (PciePortEngine, Wrapper); + } + } + if (PcieLibIsDdiWrapper (Wrapper)) { + Status = PcieEnginesToWrapper (PcieDdiEngine, ComplexDescriptor, Wrapper); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_ERROR) { + // If we can not map topology on wrapper we can not enable any engines. + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION, + Wrapper->WrapId, + Wrapper->StartPhyLane, + Wrapper->EndPhyLane, + 0, + GnbLibGetHeader (Pcie) + ); + PcieConfigDisableAllEngines (PcieDdiEngine, Wrapper); + } + } + // Copy engine data + PcieMapInitializeEngineData (ComplexDescriptor, Wrapper, Pcie); + + EngineList = PcieConfigGetChildEngine (Wrapper); + // Verify if we oversubscribe lanes and PHY link width + WrapperPhyLaneBitMap = 0; + while (EngineList != NULL) { + UINT32 EnginePhyLaneBitMap; + if (PcieLibIsEngineAllocated (EngineList)) { + EnginePhyLaneBitMap = PcieConfigGetEnginePhyLaneBitMap (EngineList); + if ((WrapperPhyLaneBitMap & EnginePhyLaneBitMap) != 0) { + IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Lanes double subscribe lanes [Engine Lanes %d..%d]\n", + EngineList->EngineData.StartLane, + EngineList->EngineData.EndLane + ); + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_LANES_CONFIGURATION, + EngineList->EngineData.StartLane, + EngineList->EngineData.EndLane, + 0, + 0, + GnbLibGetHeader (Pcie) + ); + PcieConfigDisableEngine (EngineList); + Status = AGESA_ERROR; + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } else { + WrapperPhyLaneBitMap |= EnginePhyLaneBitMap; + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Exit [%d]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize engine data + * + * + * + * @param[in] ComplexDescriptor Pointer to user defined complex descriptor + * @param[in,out] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieMapInitializeEngineData ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN OUT PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; + + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + if (EngineList->Scratch != 0xFF) { + EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, EngineList->Scratch); + LibAmdMemCopy (&EngineList->EngineData, &EngineDescriptor->EngineData, sizeof (EngineDescriptor->EngineData), GnbLibGetHeader (Pcie)); + if (PcieLibIsDdiEngine (EngineList)) { + LibAmdMemCopy (&EngineList->Type.Ddi, &((PCIe_DDI_DESCRIPTOR*) EngineDescriptor)->Ddi, sizeof (PCIe_DDI_DATA), GnbLibGetHeader (Pcie)); + EngineList->Type.Ddi.DisplayPriorityIndex = (UINT8) EngineList->Scratch; + } else if (PcieLibIsPcieEngine (EngineList)) { + LibAmdMemCopy (&EngineList->Type.Port, &((PCIe_PORT_DESCRIPTOR*) EngineDescriptor)->Port, sizeof (PCIe_PORT_DATA), GnbLibGetHeader (Pcie)); + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Allocate PCI addresses for all PCIe engines on silicon + * + * + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieCheckPortPciDeviceMapping ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + BOOLEAN Result; + + if ((PortDescriptor->Port.DeviceNumber == Engine->Type.Port.NativeDevNumber && + PortDescriptor->Port.FunctionNumber == Engine->Type.Port.NativeFunNumber) || + (PortDescriptor->Port.DeviceNumber == 0 && PortDescriptor->Port.FunctionNumber == 0)) { + Result = TRUE; + } else { + Result = PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine); + } + + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Allocate PCI addresses for all PCIe engines on silicon + * + * + * + * @param[in] Silicon Pointer to silicon configurration + * @param[in] Pcie Pointer PCIe configuration + * @retval AGESA_ERROR Fail to allocate PCI device address + * @retval AGESA_SUCCESS Successfully allocate PCI address for all PCIe ports + */ + +AGESA_STATUS +STATIC +PcieMapPortsPciAddresses ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + PCIe_WRAPPER_CONFIG *WrapperList; + PCIe_ENGINE_CONFIG *EngineList; + AgesaStatus = AGESA_SUCCESS; + WrapperList = PcieConfigGetChildWrapper (Silicon); + while (WrapperList != NULL) { + EngineList = PcieConfigGetChildEngine (WrapperList); + while (EngineList != NULL) { + if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { + Status = PcieFmMapPortPciAddress (EngineList); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO ( + 0, + Silicon->Address.Address.Bus, + EngineList->Type.Port.PortData.DeviceNumber, + EngineList->Type.Port.PortData.FunctionNumber, + 0 + ); + } else { + EngineList->Type.Port.PortData.PortPresent = OFF; + IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to allocate PCI address for PCIe port\n" + ); + //Report error + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION, + EngineList->Type.Port.PortData.DeviceNumber, + 0, + 0, + 0, + GnbLibGetHeader (Pcie) + ); + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + WrapperList = PcieLibGetNextDescriptor (WrapperList); + } + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * If link width from user descriptor less or equal to link width of engine + * + * + * @param[in] EngineDescriptor Pointer to used define engine descriptor + * @param[in] Engine Pointer to engine config + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieCheckLanesMatch ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + BOOLEAN Result; + UINT16 DescriptorHiLane; + UINT16 DescriptorLoLane; + UINT16 DescriptorNumberOfLanes; + + DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; + Result = FALSE; + + if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { + // + // If link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG) + // + if (DescriptorNumberOfLanes <= PcieConfigGetNumberOfCoreLane (Engine)) { + Result = TRUE; + } + } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { + // + //For Ddi, check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG) + // + if ((Engine->EngineData.StartLane == DescriptorLoLane) && (Engine->EngineData.EndLane == DescriptorHiLane)) { + Result = TRUE; + } + } + + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8 + * + * + * @param[in] EngineDescriptor A pointer of PCIe_ENGINE_DESCRIPTOR + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieIsDescriptorLinkWidthValid ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor + ) +{ + BOOLEAN Result; + UINT16 DescriptorHiLane; + UINT16 DescriptorLoLane; + UINT16 DescriptorNumberOfLanes; + + Result = FALSE; + DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; + + if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { + if (DescriptorNumberOfLanes == 1 || DescriptorNumberOfLanes == 2 || DescriptorNumberOfLanes == 4 || + DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 16) { + Result = TRUE; + } + } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { + if (DescriptorNumberOfLanes == 4 || DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 7) { + Result = TRUE; + } + } + + GNB_DEBUG_CODE ( + if (!Result) { + IDS_HDT_CONSOLE (PCIE_MISC, " Invalid Link width [Engine Lanes %d..%d]\n", + DescriptorLoLane, + DescriptorHiLane + ); + } + ); + + return Result; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h new file mode 100644 index 0000000000..7f69aeab85 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h @@ -0,0 +1,84 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Procedure to map user define topology to processor configuration + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEMAPTOPOLOGY_H_ +#define _PCIEMAPTOPOLOGY_H_ + +AGESA_STATUS +PcieMapTopologyOnComplex ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN PCIe_COMPLEX_CONFIG *Complex, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h new file mode 100644 index 0000000000..d92559cca9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe Init Library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEINITLIBV1_H_ +#define _PCIEINITLIBV1_H_ + +#include "PciePifServices.h" +#include "PciePortRegAcc.h" +#include "PciePowerMgmt.h" +#include "PcieTimer.h" +#include "PcieTopologyServices.h" +#include "PcieUtilityLib.h" +#include "PcieWrapperRegAcc.h" +#include "PcieAspmExitLatency.h" +#include "PcieSiliconServices.h" +#include "PciePortServices.h" +#include "PcieAspm.h" +#include "PciePhyServices.h" +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c new file mode 100644 index 0000000000..4642b7fa24 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c @@ -0,0 +1,179 @@ +/** + * @file + * + * PCIe link ASPM Black List + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "PcieAspmBlackList.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +UINT16 AspmBrDeviceTable[] = { + 0x1002, 0x9441, (UINT16) ~(AspmL1 | AspmL0s), + 0x10B5, 0xFFFF, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0402, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0193, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0422, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0292, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x00F9, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0141, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0092, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D0, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D1, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D2, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D3, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D5, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D7, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D8, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01DC, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01DE, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01DF, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x016A, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0392, (UINT16) ~(AspmL1 | AspmL0s), + 0x168C, 0xFFFF, (UINT16) ~(AspmL0s), + 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s), + 0x1B4B, 0x9123, (UINT16) ~(AspmL0s), + 0x1969, 0x1083, (UINT16) ~(AspmL0s) +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie ASPM Black List + * + * + * + * @param[in] LinkAsmp PCie ASPM black list + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PcieAspmBlackListFeature ( + IN PCIe_LINK_ASPM *LinkAsmp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 UpstreamDeviceId; + UINT32 DownstreamDeviceId; + UINTN i; + UINT32 DeviceId; + UINT32 VendorId; + + GnbLibPciRead (LinkAsmp->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader); + GnbLibPciRead (LinkAsmp->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader); + for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) { + VendorId = AspmBrDeviceTable[i]; + DeviceId = AspmBrDeviceTable[i + 1]; + if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) { + if (DeviceId == 0xFFFF || DeviceId == (UpstreamDeviceId >> 16) || DeviceId == (DownstreamDeviceId >> 16)) { + LinkAsmp->UpstreamAspm &= AspmBrDeviceTable[i + 2]; + LinkAsmp->DownstreamAspm &= AspmBrDeviceTable[i + 2]; + } + } + } + if ((UINT16)UpstreamDeviceId == 0x168c) { + LinkAsmp->UpstreamAspm = LinkAsmp->RequestedAspm & AspmL1; + LinkAsmp->DownstreamAspm = LinkAsmp->UpstreamAspm; + GnbLibPciRMW (LinkAsmp->UpstreamPort.AddressValue | 0x70C, AccessS3SaveWidth32, 0x0, 0x0F003F01, StdHeader); + + DeviceId = UpstreamDeviceId >> 16; + if ((DeviceId == 0x002C) || (DeviceId == 0x002B) || (DeviceId == 0x002E)) { + LinkAsmp->UpstreamAspm = LinkAsmp->RequestedAspm & AspmL0sL1; + LinkAsmp->DownstreamAspm = LinkAsmp->UpstreamAspm & AspmL1; + } + } + if (UpstreamDeviceId == 0x10831969) { + GnbLibPciRMW (LinkAsmp->UpstreamPort.AddressValue | 0x12F8, AccessS3SaveWidth32, 0xFFF7F7FF, 0, StdHeader); + } + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h new file mode 100644 index 0000000000..2857a70f29 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h @@ -0,0 +1,82 @@ +/** + * @file + * + * PCIe ASPM Black List + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEASPMBLACKLIST_H_ +#define _PCIEASPMBLACKLIST_H_ + +///PCIe ASPM Black List + +AGESA_STATUS +PcieAspmBlackListFeature ( + IN PCIe_LINK_ASPM *LinkAsmp, + IN AMD_CONFIG_PARAMS *StdHeader + ); +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c new file mode 100644 index 0000000000..744c88b53b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c @@ -0,0 +1,218 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to calculate PCIe topology segment maximum exit latency + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo; + PCI_ADDR DownstreamPort; + UINT8 LinkCount; +} PCIE_EXIT_LATENCY_DATA; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +SCAN_STATUS +PcieAspmGetMaxExitLatencyCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Determine ASPM L-state maximum exit latency for PCIe segment + * + * Scan through all link in segment to determine maxim exit latency requirement by EPs. + * + * @param[in] DownstreamPort PCI address of PCIe port + * @param[out] AspmLatencyInfo Latency info + * @param[in] StdHeader Standard configuration header + * + */ + +VOID +PcieAspmGetMaxExitLatency ( + IN PCI_ADDR DownstreamPort, + OUT PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIE_EXIT_LATENCY_DATA PcieExitLatencyData; + PcieExitLatencyData.AspmLatencyInfo = AspmLatencyInfo; + PcieExitLatencyData.ScanData.StdHeader = StdHeader; + PcieExitLatencyData.LinkCount = 0; + PcieExitLatencyData.ScanData.GnbScanCallback = PcieAspmGetMaxExitLatencyCallback; + GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieExitLatencyData.ScanData); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +SCAN_STATUS +PcieAspmGetMaxExitLatencyCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + PCIE_EXIT_LATENCY_DATA *PcieExitLatencyData; + PCIE_DEVICE_TYPE DeviceType; + UINT32 Value; + UINT8 PcieCapPtr; + UINT8 L1AcceptableLatency; + + PcieExitLatencyData = (PCIE_EXIT_LATENCY_DATA*) ScanData; + ScanStatus = SCAN_SUCCESS; + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmGetMaxExitLatencyCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + PcieExitLatencyData->DownstreamPort = Device; + PcieExitLatencyData->LinkCount++; + GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData); + PcieExitLatencyData->LinkCount--; + break; + case PcieDeviceUpstreamPort: + GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData); + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader); + ASSERT (PcieCapPtr != 0); + GnbLibPciRead ( + Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), + AccessWidth32, + &Value, + ScanData->StdHeader + ); + if ((Value & PCIE_ASPM_L1_SUPPORT_CAP) != 0) { + GnbLibPciRead ( + Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER), + AccessWidth32, + &Value, + ScanData->StdHeader + ); + L1AcceptableLatency = (UINT8) (1 << ((Value >> 9) & 0x7)); + if (PcieExitLatencyData->LinkCount > 1) { + L1AcceptableLatency = L1AcceptableLatency + PcieExitLatencyData->LinkCount; + } + if (PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency < L1AcceptableLatency) { + PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency = L1AcceptableLatency; + } + IDS_HDT_CONSOLE (PCIE_MISC, " Device max exit latency L1 - %d us\n", + L1AcceptableLatency + ); + } + break; + default: + break; + } + return SCAN_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h new file mode 100644 index 0000000000..12c16e5a69 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h @@ -0,0 +1,82 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to calculate PCIe topology segment maximum exit latency + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEASPMEXITLATENCY_H_ +#define _PCIEASPMEXITLATENCY_H_ + +VOID +PcieAspmGetMaxExitLatency ( + IN PCI_ADDR DownstreamPort, + OUT PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c new file mode 100644 index 0000000000..77def5281c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c @@ -0,0 +1,334 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe PIF initialization routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define MAX_NUM_PHYs 2 +#define MAX_NUM_LANE_PER_PHY 8 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +//Channel Type: LowLoss / HighLoss / Mob0db / Mob3db / Ext6db / Ext8db +INT8 chtype_0 /* DeemphasisSel */ [] = { 1, 0, 1, 1, 0, 0}; +INT8 chtype_1 /* DeemphGen1Nom */ [] = { 42, 42, 0, 0, 42, 42}; +INT8 chtype_2 /* DeemPh35Gen2Nom */ [] = { 42, 64, 0, 42, 64, 77}; +INT8 chtype_3 /* Deemph60Gen2NOm */ [] = { 42, 64, 0, 42, 64, 77}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * PHY lane ganging + * + * + * + * @param[out] Wrapper Pointer to internal configuration data area + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePhyApplyGanging ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT8 GangMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY]; + UINT8 MasterMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY]; + UINT16 LoPhylane; + UINT16 HiPhylane; + UINT8 Phy; + UINT16 Lane; + UINT16 PhyLinkWidth; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Enter\n"); + LibAmdMemFill (GangMatrix, 0, sizeof (GangMatrix), GnbLibGetHeader (Pcie)); + LibAmdMemFill (MasterMatrix, 0, sizeof (MasterMatrix), GnbLibGetHeader (Pcie)); + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + HiPhylane = PcieLibGetHiPhyLane (EngineList) - Wrapper->StartPhyLane; + LoPhylane = PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; + PhyLinkWidth = HiPhylane - LoPhylane + 1; + + if (PhyLinkWidth >= 8) { + for (Lane = LoPhylane; Lane <= HiPhylane; Lane++) { + ((UINT8 *) GangMatrix)[Lane] = 1; + } + } else { + if (PhyLinkWidth > 0 && PhyLinkWidth < 4) { + for (Lane = (LoPhylane / 4) * 4; Lane < (((LoPhylane / 4) * 4) + 4) ; Lane++) { + ((UINT8 *) MasterMatrix)[Lane] = 1; + } + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { + for (Lane = 0; Lane < MAX_NUM_LANE_PER_PHY; Lane++) { + D0F0xE4_PHY_6005_STRUCT D0F0xE4_PHY_6005; + D0F0xE4_PHY_6005.Value = PcieRegisterRead ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80), + Pcie + ); + D0F0xE4_PHY_6005.Field.GangedModeEn = GangMatrix [Phy][Lane]; + D0F0xE4_PHY_6005.Field.IsOwnMstr = MasterMatrix [Phy][Lane]; + PcieRegisterWrite ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80), + D0F0xE4_PHY_6005.Value, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Point "virtual" PLL clock picker away from PCIe + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePhyAvertClockPickers ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 DdiLanes; + UINT8 Nibble; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Enter\n"); + DdiLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); + for (Nibble = 0; Nibble < 4; Nibble++) { + if (DdiLanes & (0xf << (Nibble * 4))) { + PcieRegisterRMW ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_0009_ADDRESS + (Nibble & 0x1)), + D0F0xE4_PHY_0009_PCIePllSel_MASK, + 0x0 << D0F0xE4_PHY_0009_PCIePllSel_OFFSET, + FALSE, + Pcie + ); + PcieRegisterRMW ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_000B_ADDRESS + (Nibble & 0x1)), + D0F0xE4_PHY_000B_MargPktSbiEn_MASK | D0F0xE4_PHY_000B_PcieModeSbiEn_MASK, + (0x0 << D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET) | (0x0 << D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET), + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set PHY channel characteristic + * + * + * + * @param[in] Engine Pointer to engine configuration + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePhyChannelCharacteristic ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_WRAPPER_CONFIG *Wrapper; + UINT16 StartLane; + UINT16 EndLane; + UINT16 Lane; + UINT8 ChannelType; + + Wrapper = PcieConfigGetParentWrapper (Engine); + ChannelType = Engine->Type.Port.PortData.ChannelType; + StartLane = MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) - Wrapper->StartPhyLane; + EndLane = MAX (Engine->EngineData.StartLane, Engine->EngineData.EndLane) - Wrapper->StartPhyLane; + + PcieRegisterRMW ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0803_ADDRESS + (Engine->Type.Port.PortId) * 0x100), + D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK, + chtype_0 /* DeemphasisSel */[ChannelType] << D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET, + FALSE, + Pcie + ); + for (Lane = StartLane; Lane <= EndLane; Lane++) { + UINT16 PhyLane; + UINT16 Phy; + if (Lane < MAX_NUM_LANE_PER_PHY ) { + Phy = 0; + PhyLane = Lane; + } else { + Phy = 1; + PhyLane = Lane - MAX_NUM_LANE_PER_PHY; + } + PcieRegisterRMW ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80), + D0F0xE4_PHY_6006_DeemphGen1Nom_MASK, + chtype_1 /* DeemphGen1Nom */[ChannelType] << D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET, + FALSE, + Pcie + ); + PcieRegisterRMW ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80), + D0F0xE4_PHY_6006_Deemph35Gen2Nom_MASK, + chtype_2 /* DeemPh35Gen2Nom */[ChannelType] << D0F0xE4_PHY_6006_Deemph35Gen2Nom_OFFSET, + FALSE, + Pcie + ); + PcieRegisterRMW ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80), + D0F0xE4_PHY_6006_Deemph60Gen2Nom_MASK, + chtype_3 /* Deemph60Gen2NOm */[ChannelType] << D0F0xE4_PHY_6006_Deemph60Gen2Nom_OFFSET, + FALSE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * DCC recalibration + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] Pcie Pointer to global PCIe configuration + */ + +AGESA_STATUS +PciePhyForceDccRecalibration ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Phy; + UINT8 PhyLane; + for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { + for (PhyLane = 0; PhyLane < MAX_NUM_LANE_PER_PHY; PhyLane++) { + PcieRegisterWriteField ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4001_ADDRESS + PhyLane * 0x80), + D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET, + D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH, + 0x1, + FALSE, + Pcie + ); + } + } + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h new file mode 100644 index 0000000000..946de59030 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h @@ -0,0 +1,100 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe PIF initialization routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEPHYSERVICES_H_ +#define _PCIEPHYSERVICES_H_ + +VOID +PciePhyApplyGanging ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePhyAvertClockPickers ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePhyChannelCharacteristic ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PciePhyForceDccRecalibration ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c new file mode 100644 index 0000000000..8973820082 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c @@ -0,0 +1,654 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe PIF initialization routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define PIF_GANG_0to1 0x1 +#define PIF_GANG_2to3 (0x1 << 1) +#define PIF_GANG_4to5 (0x1 << 2) +#define PIF_GANG_6to7 (0x1 << 3) +#define PIF_GANG_0to3 (0x1 << 4) +#define PIF_GANG_4to7 (0x1 << 8) +#define PIF_GANG_0to7 (0x1 << 9) +#define PIF_GANG_ALL (0x1 << 25) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Apply PIF ganging for all lanes for given wrapper + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + + +VOID +PciePifApplyGanging ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT32 LaneBitmap; + UINT8 Pif; + D0F0xE4_PIF_0011_STRUCT D0F0xE4_PIF_0011[2]; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Enter\n"); + LibAmdMemFill (&D0F0xE4_PIF_0011, 0, sizeof (D0F0xE4_PIF_0011), GnbLibGetHeader (Pcie)); + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, EngineList); + switch (LaneBitmap) { + case 0x0003: + D0F0xE4_PIF_0011[0].Field.X2Lane10 = 0x1; + break; + case 0x000c: + D0F0xE4_PIF_0011[0].Field.X2Lane32 = 0x1; + break; + case 0x0030: + D0F0xE4_PIF_0011[0].Field.X2Lane54 = 0x1; + break; + case 0x00c0: + D0F0xE4_PIF_0011[0].Field.X2Lane76 = 0x1; + break; + case 0x000f: + D0F0xE4_PIF_0011[0].Field.X4Lane30 = 0x1; + break; + case 0x00f0: + D0F0xE4_PIF_0011[0].Field.X4Lane74 = 0x1; + break; + case 0x00ff: + D0F0xE4_PIF_0011[0].Field.X8Lane70 = 0x1; + break; + case 0x0300: + D0F0xE4_PIF_0011[1].Field.X2Lane10 = 1; + break; + case 0x0c00: + D0F0xE4_PIF_0011[1].Field.X2Lane32 = 0x1; + break; + case 0x3000: + D0F0xE4_PIF_0011[1].Field.X2Lane54 = 0x1; + break; + case 0xc000: + D0F0xE4_PIF_0011[1].Field.X2Lane76 = 0x1; + break; + case 0x0f00: + D0F0xE4_PIF_0011[1].Field.X4Lane30 = 0x1; + break; + case 0xf000: + D0F0xE4_PIF_0011[1].Field.X4Lane74 = 0x1; + break; + case 0xff00: + D0F0xE4_PIF_0011[1].Field.X8Lane70 = 0x1; + break; + case 0xffff: + D0F0xE4_PIF_0011[0].Field.MultiPif = 0x1; + D0F0xE4_PIF_0011[1].Field.MultiPif = 0x1; + break; + default: + break; + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0011_ADDRESS), + D0F0xE4_PIF_0011[Pif].Value, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PLL powerdown + * + * + * @param[in] LaneBitmap Power down PLL for these lanes + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + +VOID +PciePifPllPowerDown ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Nibble; + UINT16 NibbleBitmap; + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Enter\n"); + for (Nibble = 0; Nibble < 4; Nibble++) { + NibbleBitmap = (0xF << (Nibble * 4)); + if ((LaneBitmap & NibbleBitmap) == NibbleBitmap) { + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + Pcie + ); + + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff; + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + D0F0xE4_PIF_0012.Value, + TRUE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PLL init for DDI + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + +VOID +PciePifPllInitForDdi ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Nibble; + UINT32 LaneBitmap; + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Enter\n"); + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); + for (Nibble = 0; Nibble < 4; Nibble++) { + if (LaneBitmap & (0xF << (Nibble * 4))) { + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + Pcie + ); + + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x2; + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + D0F0xE4_PIF_0012.Value, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Poll for on PIF to indicate action completion + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePollPifForCompeletion ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + //UINT32 TimeStamp; + UINT8 Pif; + D0F0xE4_PIF_0015_STRUCT D0F0xE4_PIF_0015; + //TimeStamp = PcieTimerGetTimeStamp (Pcie); + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + do { + D0F0xE4_PIF_0015.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0015_ADDRESS), + Pcie + ); + //if (TIMESTAMPS_DELTA (TimeStamp, PcieTimerGetTimeStamp (Pcie)) > 100) { + // break; + //} + } while ((D0F0xE4_PIF_0015.Value & 0xff) != 0xff); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Disable fifo reset + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + + +VOID +PciePifDisableFifoReset ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET, + D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH, + 0, + FALSE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Program LS2 exit time + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePifSetLs2ExitTime ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Enter\n"); + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET, + D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH, + 0x0, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set PLL mode for L1 + * + * + * @param[in] LaneBitmap Power down PLL for these lanes + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + +VOID +PciePifSetPllModeForL1 ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Nibble; + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + for (Nibble = 0; Nibble < 4; Nibble++) { + if (LaneBitmap & (0xF << (Nibble * 4))) { + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + Pcie + ); + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2; + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2; + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + D0F0xE4_PIF_0012.Value, + TRUE, + Pcie + ); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Program receiver detection power mode + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePifSetRxDetectPowerMode ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n"); + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET, + D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH, + 0x1, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Pll ramp up time + * + * + * + * @param[in] Rampup Ramp up time + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePifSetPllRampTime ( + IN PCIE_PLL_RAMPUP_TIME Rampup, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013; + D0F0xE4_PIF_0010_STRUCT D0F0xE4_PIF_0010; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Enter\n"); + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), + Pcie + ); + D0F0xE4_PIF_0013.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), + Pcie + ); + D0F0xE4_PIF_0010.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + Pcie + ); + if (Rampup == NormalRampup) { + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; + D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x1; + D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x0; + } else { + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x3; + D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x3; + D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x6; + } + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), + D0F0xE4_PIF_0012.Value, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), + D0F0xE4_PIF_0013.Value, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + D0F0xE4_PIF_0010.Value, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down PIFs + * + * + * + * @param[in] Control Power up or Power down control + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePifPllPowerControl ( + IN PCIE_PIF_POWER_CONTROL Control, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + UINT8 PllPowerStateInOff; + PllPowerStateInOff = (Control == PowerDownPifs) ? PifPowerStateOff : PifPowerStateL0; + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), + D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET, + D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH, + PllPowerStateInOff, + FALSE, + Pcie + ); + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), + D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET, + D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH, + PllPowerStateInOff, + FALSE, + Pcie + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down PIFs + * + * + * + * @param[in] Control Power up/Down control + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePifFullPowerStateControl ( + IN PCIE_PIF_POWER_CONTROL Control, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013; + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), + Pcie + ); + D0F0xE4_PIF_0013.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), + Pcie + ); + if (Control == PowerDownPifs) { + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff; + D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateOff; + } else { + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateLS2; + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateLS2; + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0; + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0; + D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateLS2; + D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateLS2; + D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateL0; + D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateL0; + } + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), + D0F0xE4_PIF_0012.Value, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), + D0F0xE4_PIF_0013.Value, + FALSE, + Pcie + ); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h new file mode 100644 index 0000000000..d0c2a81b73 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h @@ -0,0 +1,147 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe PIF initialization routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEPIFSERVICES_H_ +#define _PCIEPIFSERVICES_H_ + +VOID +PciePifApplyGanging ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifPllPowerDown ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifPllInitForDdi ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePollPifForCompeletion ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifDisableFifoReset ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifSetLs2ExitTime ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifSetPllModeForL1 ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifSetRxDetectPowerMode ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifSetPllRampTime ( + IN PCIE_PLL_RAMPUP_TIME Rampup, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifPllPowerControl ( + IN PCIE_PIF_POWER_CONTROL Control, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifFullPowerStateControl ( + IN PCIE_PIF_POWER_CONTROL Control, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c new file mode 100644 index 0000000000..d02fbf6a06 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c @@ -0,0 +1,257 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to access PCIe port indirect register + * space. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "PciePortRegAcc.h" +#include "GnbCommonLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PCIe port indirect register. + * + * Support for unify register access through index/data pair on PCIe port + * + * @param[in] Engine Pointer to Engine descriptor for this port + * @param[in] Address Register address + * @param[in] Pcie Pointer to internal configuration data area + * @retval Register Value + */ + +UINT32 +PciePortRegisterRead ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie)); + GnbLibPciRead (Engine->Type.Port.Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie)); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe Port Indirect register. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Engine Pointer to Engine descriptor for this port + * @param[in] Address Register address + * @param[in] Value New register value + * @param[in] S3Save Save for S3 flag + * @param[in] Pcie Pointer to internal configuration data area + */ +VOID +PciePortRegisterWrite ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + ASSERT (S3Save == TRUE || S3Save == FALSE); + + IDS_HDT_CONSOLE (PCIE_PORTREG_TRACE, " *WR PCIEIND_P (%d:%d:%d):0x%04x = 0x%08x\n", + Engine->Type.Port.Address.Address.Bus, + Engine->Type.Port.Address.Address.Device, + Engine->Type.Port.Address.Address.Function, + Address, + Value + ); + GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie)); + GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie)); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe Port Indirect register field. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Engine Pointer to Engine descriptor for this port + * @param[in] Address Register address + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[in] S3Save Save for S3 flag + * @param[in] Value New register value + * @param[in] Pcie Pointer to internal configuration data area + */ + +VOID +PciePortRegisterWriteField ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Data; + UINT32 Mask; + Data = PciePortRegisterRead (Engine, Address, Pcie); + Mask = (1 << FieldWidth) - 1; + Value &= Mask; + Data &= (~(Mask << FieldOffset)); + PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe Port Indirect register field. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Engine Pointer to Engine descriptor for this port + * @param[in] Address Register address + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[in] Pcie Pointer to internal configuration data area + * @retval Register Field Value. + */ + +UINT32 +PciePortRegisterReadField ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + Value = PciePortRegisterRead (Engine, Address, Pcie); + Value = (Value >> FieldOffset) & ((1 << FieldWidth) - 1); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write PCIe port register. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Engine Pointer to Engine descriptor for this port + * @param[in] Address Register address + * @param[in] AndMask Value & (~AndMask) + * @param[in] OrMask Value | OrMask + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePortRegisterRMW ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + Value = PciePortRegisterRead (Engine, Address, Pcie); + Value = (Value & (~AndMask)) | OrMask; + PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h new file mode 100644 index 0000000000..426f3b8cba --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h @@ -0,0 +1,121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to access PCIe port indirect register space. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEPORTREGACC_H_ +#define _PCIEPORTREGACC_H_ + +UINT32 +PciePortRegisterRead ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePortRegisterWrite ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePortRegisterWriteField ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PciePortRegisterReadField ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePortRegisterRMW ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c new file mode 100644 index 0000000000..456b2552cd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c @@ -0,0 +1,533 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbSbLib.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Set completion timeout + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieCompletionTimeout ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | DxF0x80_ADDRESS, + AccessWidth32, + 0xffffffff, + 0x6 << DxF0x80_CplTimeoutValue_OFFSET, + GnbLibGetHeader (Pcie) + ); + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + PciePortRegisterWriteField ( + Engine, + DxF0xE4_x20_ADDRESS, + DxF0xE4_x20_TxFlushTlpDis_OFFSET, + DxF0xE4_x20_TxFlushTlpDis_WIDTH, + 0x0, + TRUE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init hotplug port + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieLinkInitHotplug ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + DxF0xE4_xB5_STRUCT DxF0xE4_xB5; + if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) { + DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie); + DxF0xE4_xB5.Field.line521 = 0x3; + DxF0xE4_xB5.Field.line522 = 0x3; + DxF0xE4_xB5.Field.line519 = 0x1; + PciePortRegisterWrite ( + Engine, + DxF0xE4_xB5_ADDRESS, + DxF0xE4_xB5.Value, + TRUE, + Pcie + ); + PcieRegisterWriteField ( + PcieConfigGetParentWrapper (Engine), + CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS), + D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET, + D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH, + 0x5, + TRUE, + Pcie + ); + PcieRegisterWriteField ( + PcieConfigGetParentWrapper (Engine), + WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, 0x8011 ), + 16 , + 1 , + 0x1, + TRUE, + Pcie + ); + } + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, + AccessS3SaveWidth32, + 0xffffffff, + 1 << DxF0x6C_HotplugCapable_OFFSET, + GnbLibGetHeader (Pcie) + ); + PciePortRegisterWriteField ( + Engine, + DxF0xE4_x20_ADDRESS, + DxF0xE4_x20_TxFlushTlpDis_OFFSET, + DxF0xE4_x20_TxFlushTlpDis_WIDTH, + 0x0, + TRUE, + Pcie + ); + PciePortRegisterWriteField ( + Engine, + DxF0xE4_x70_ADDRESS, + DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET, + DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH, + 0x1, + FALSE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set misc slot capability + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieLinkSetSlotCap ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | DxF0x58_ADDRESS, + AccessWidth32, + 0xffffffff, + 1 << DxF0x58_SlotImplemented_OFFSET, + GnbLibGetHeader (Pcie) + ); + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | DxF0x3C_ADDRESS, + AccessWidth32, + 0xffffffff, + 1 << DxF0x3C_IntPin_OFFSET, + GnbLibGetHeader (Pcie) + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Safe mode to force link advertize Gen1 only capability in TS + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieLinkSafeMode ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + //Engine->Type.Port.PortData.LinkSpeedCapability = PcieGen1; + PcieFmSetLinkSpeedCap (PcieGen1, Engine, Pcie); + PciePortRegisterRMW ( + Engine, + DxF0xE4_xA2_ADDRESS, + DxF0xE4_xA2_LcUpconfigureDis_MASK, + (1 << DxF0xE4_xA2_LcUpconfigureDis_OFFSET), + FALSE, + Pcie + ); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set current link speed + * + * + * @param[in] Engine Pointer to engine configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieSetLinkWidthCap ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePortRegisterRMW ( + Engine, + DxF0xE4_xA2_ADDRESS, + DxF0xE4_xA2_LcUpconfigureDis_MASK, + 0, + FALSE, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set current link speed + * + * + * @param[in] LinkSpeedCapability Link Speed Capability + * @param[in] Engine Pointer to engine configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieSetLinkSpeedCap ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + ex548_STRUCT ex548 ; + DxF0xE4_xC0_STRUCT DxF0xE4_xC0; + DxF0x88_STRUCT DxF0x88; + GnbLibPciRead ( + Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, + AccessWidth32, + &DxF0x88.Value, + GnbLibGetHeader (Pcie) + ); + ex548.Value = PciePortRegisterRead ( + Engine, + 0xa4 , + Pcie + ); + DxF0xE4_xC0.Value = PciePortRegisterRead ( + Engine, + DxF0xE4_xC0_ADDRESS, + Pcie + ); + + switch (LinkSpeedCapability) { + case PcieGen2: + ex548.Field.LcGen2EnStrap = 0x1; + ex548.Field.LcMultUpstreamAutoSpdChngEn = 0x1; + DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0; + DxF0x88.Field.TargetLinkSpeed = 0x2; + DxF0x88.Field.HwAutonomousSpeedDisable = 0x0; + break; + case PcieGen1: + ex548.Field.LcGen2EnStrap = 0x0; + ex548.Field.LcMultUpstreamAutoSpdChngEn = 0x0; + DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1; + DxF0x88.Field.TargetLinkSpeed = 0x1; + DxF0x88.Field.HwAutonomousSpeedDisable = 0x1; + PcieRegisterWriteField ( + PcieConfigGetParentWrapper (Engine), + WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId), + D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET, + D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH, + 0, + FALSE, + Pcie + ); + break; + default: + ASSERT (FALSE); + break; + } + PciePortRegisterWrite ( + Engine, + 0xa4 , + ex548.Value, + FALSE, + Pcie + ); + PciePortRegisterWrite ( + Engine, + DxF0xE4_xC0_ADDRESS, + DxF0xE4_xC0.Value, + FALSE, + Pcie + ); + GnbLibPciWrite ( + Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, + AccessWidth32, + &DxF0x88.Value, + GnbLibGetHeader (Pcie) + ); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Force compliance + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieForceCompliance ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (Engine->Type.Port.PortData.LinkSpeedCapability >= PcieGen2) { + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, + AccessWidth32, + 0xffffffff, + 0x1 << DxF0x88_EnterCompliance_OFFSET, + GnbLibGetHeader (Pcie) + ); + } else if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGen1) { + PciePortRegisterWriteField ( + Engine, + DxF0xE4_xC0_ADDRESS, + DxF0xE4_xC0_StrapForceCompliance_OFFSET, + DxF0xE4_xC0_StrapForceCompliance_WIDTH, + 0x1, + FALSE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set slot power limit + * + * + * + * @param[in] Engine Pointer to engine configuration + * @param[in] Pcie Pointer to PCIe configuration + */ + + +VOID +PcieEnableSlotPowerLimit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !PcieConfigIsSbPcieEngine (Engine)) { + IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device); + GnbLibPciIndirectRMW ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + (0x51 + (Engine->Type.Port.Address.Address.Device - 2) * 2) | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + 0xffffffff, + 1 << 20 , + GnbLibGetHeader (Pcie) + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable ASPM on SB link + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieEnableAspm ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled) { + if (PcieConfigIsSbPcieEngine (Engine)) { + SbPcieLinkAspmControl (Engine, Pcie); + } + } +} + + +UINT8 L1State = 0x1b; +/*----------------------------------------------------------------------------------------*/ +/** + * Poll for link to get into L1 + * + * + * + * @param[in] Engine Pointer to Engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePollLinkForL1Entry ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkHwStateHistory[8]; + do { + PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie); + } while (!PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), &L1State, sizeof (L1State))); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Poll for link to get into L1 + * + * + * + * @param[in] Engine Pointer to Engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePollLinkForL0Exit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkHwStateHistory[4]; + do { + PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie); + } while (LinkHwStateHistory[0] != 0x10); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h new file mode 100644 index 0000000000..9ac8ce8346 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h @@ -0,0 +1,145 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEPORTSERVICES_H_ +#define _PCIEPORTSERVICES_H_ + + +VOID +PcieSetLinkSpeedCap ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetLinkWidthCap ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieLinkSafeMode ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieCompletionTimeout ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieLinkSetSlotCap ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieLinkInitHotplug ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieForceCompliance ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieEnableSlotPowerLimit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieEnableAspm ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePollLinkForL1Entry ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePollLinkForL0Exit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c new file mode 100644 index 0000000000..f15a582b5b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c @@ -0,0 +1,424 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Power saving features/services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down unused lanes and plls + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePwrPowerDownUnusedLanes ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 UnusedLanes; + UINT32 AllLanes; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n"); + if (Wrapper->Features.PowerOffUnusedPlls != 0) { + AllLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper); + UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, Wrapper); + if (AllLanes != UnusedLanes) { + //Some lanes end up beeing used. We should keep master PLL powered up + UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, Wrapper); + } + PciePifPllPowerDown ( + UnusedLanes, + Wrapper, + Pcie + ); + } + if (Wrapper->Features.PowerOffUnusedLanes != 0) { + UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper); + PcieTopologyLaneControl ( + DisableLanes, + UnusedLanes, + Wrapper, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Lane bitmam to enable PLL power down in L1 + * + * + * @param[in] PllPowerUpLatency Pointer to wrapper config descriptor + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * @retval Lane bitmap for which PLL can be powered down in L1 + */ + +UINT32 +PcieLanesToPowerDownPllInL1 ( + IN UINT8 PllPowerUpLatency, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LaneGroupExitLatency [4]; + UINT32 LaneBitmapForPllOffInL1; + PCIe_ENGINE_CONFIG *EngineList; + UINTN Index; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Enter\n"); + LaneBitmapForPllOffInL1 = 0; + if (PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper) != 0) { + if (Wrapper->Features.PllOffInL1 != 0) { + LibAmdMemFill (&LaneGroupExitLatency[0], 0xFF, sizeof (LaneGroupExitLatency), GnbLibGetHeader (Pcie)); + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + PCIe_ASPM_LATENCY_INFO LinkLatencyInfo; + UINT32 ActiveLanesBitmap; + UINT32 HotplugLanesBitmap; + if (EngineList->EngineData.EngineType == PciePortEngine) { + LinkLatencyInfo.MaxL1ExitLatency = 0; + LinkLatencyInfo.MaxL0sExitLatency = 0; + ActiveLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, EngineList); + HotplugLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, EngineList); + if (ActiveLanesBitmap != 0 && HotplugLanesBitmap == 0 && !PcieConfigIsSbPcieEngine (EngineList)) { + PcieAspmGetMaxExitLatency (EngineList->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie)); + } + if (HotplugLanesBitmap != 0 || PcieConfigIsSbPcieEngine (EngineList)) { + LinkLatencyInfo.MaxL1ExitLatency = 0xff; + } + IDS_HDT_CONSOLE (GNB_TRACE, " Engine %d Active Lanes 0x%x, Hotplug Lanes 0x%x\n", EngineList->Type.Port.NativeDevNumber, ActiveLanesBitmap, HotplugLanesBitmap); + for (Index = 0; Index < 4; Index++) { + if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) { + if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) { + IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency); + LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency; + } + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + LaneBitmapForPllOffInL1 = 0; + for (Index = 0; Index < 4; Index++) { + IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]); + if (LaneGroupExitLatency[Index] > PllPowerUpLatency) { + LaneBitmapForPllOffInL1 |= (0xF << (Index * 4)); + } + } + } + } + IDS_HDT_CONSOLE (GNB_TRACE, " Lane bitmap %04x\n", LaneBitmapForPllOffInL1); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Exit\n"); + return LaneBitmapForPllOffInL1; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Auto-Power Down electrical Idle detector + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePwrAutoPowerDownElectricalIdleDetector ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Enter\n"); + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET, + D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH, + 0x0, + TRUE, + Pcie + ); + + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, 0x10 ), + 20 , + 3 /*D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH*/, + 0x2, + TRUE, + Pcie + ); + + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET, + D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH, + 0x1, + TRUE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Clock gating + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePwrClockGating ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + ex501_STRUCT ex501 ; + D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012; + D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014; + D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015; + ex688_STRUCT ex688 ; + UINT8 CoreId; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n"); + D0F0xE4_WRAP_8014.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8015.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8012.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), + Pcie + ); + + ex501.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x8011 ), + Pcie + ); + + if (Wrapper->Features.ClkGating == 0x1) { + D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1; + D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1; + + D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1; + + D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1; + + + ex501.Field.TxclkDynGateEnable = 0x1; + ex501.Field.TxclkRegsGateEnable = 0x1; + ex501.Field.TxclkLcntGateEnable = 0x1; + ex501.Field.RcvrDetClkEnable = 0x1; + ex501.Field.TxclkPermGateEven = 0x1; + ex501.Field.TxclkDynGateLatency = 0x3f; + ex501.Field.TxclkRegsGateLatency = 0x3f; + ex501.Field.TxclkPermGateLatency = 0x3f; + + D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7; + D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1; + D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1; + D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7; + D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1; + D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1; + + D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1; + D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0; + D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1; + D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f; + + D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1; + } + if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) { + D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1; + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), + D0F0xE4_WRAP_8014.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), + D0F0xE4_WRAP_8015.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), + D0F0xE4_WRAP_8012.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x8011 ), + ex501.Value, + TRUE, + Pcie + ); + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + PcieRegisterWriteField ( + Wrapper, + CORE_SPACE (CoreId, 0x11 ), + 0 , + 4 , + 0xf, + TRUE, + Pcie + ); + } + if (Wrapper->Features.LclkGating == 0x1) { + ex688.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x8016 ), + Pcie + ); + ex688.Field.LclkDynGateEnable = 0x1; + ex688.Field.LclkGateFree = 0x1; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x8016 ), + ex688.Value, + TRUE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n"); +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h new file mode 100644 index 0000000000..3d237e0e81 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h @@ -0,0 +1,101 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Power saving features/services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEPOWERSAVINGFEATURES_H_ +#define _PCIEPOWERSAVINGFEATURES_H_ + + +VOID +PciePwrPowerDownUnusedLanes ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PcieLanesToPowerDownPllInL1 ( + IN UINT8 PllPowerUpLatency, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePwrAutoPowerDownElectricalIdleDetector ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePwrClockGating ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl new file mode 100644 index 0000000000..56b4aa71a0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl @@ -0,0 +1,87 @@ +/** + * @file + * + * ALIB PSPP Pcie Smu Lib V1 + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 49911 $ @e \$Date: 2011-03-30 02:43:29 -0700 (Wed, 30 Mar 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + /*----------------------------------------------------------------------------------------*/ + /** + * Get current link speed + * + * Arg0 - Port Index + * + */ + + + Method (procPciePortGetCurrentLinkSpeed, 1, NotSerialized) { + Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcLinkCtrlLocal1) + ShiftRight (varLcLinkCtrlLocal1, 11, varCurrenLinkSpeedLocal2) + And (varCurrenLinkSpeedLocal2, 0x1, varCurrenLinkSpeedLocal2) + Increment (varCurrenLinkSpeedLocal2) + return (varCurrenLinkSpeedLocal2) + } + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c new file mode 100644 index 0000000000..010aae492c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c @@ -0,0 +1,284 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe complex initialization services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Gen1 voltage Index + * + * + * + * + * @param[in] StdHeader Standard configuration header + */ +UINT8 +PcieSiliconGetGen1VoltageIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Index; + UINT8 Gen1VidIndex; + UINT8 SclkVidArray[4]; + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 3, 0x15c ), + AccessWidth32, + &SclkVidArray[0], + StdHeader + ); + Gen1VidIndex = 0; + for (Index = 0; Index < 4; Index++) { + if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) { + Gen1VidIndex = Index; + } + } + return Gen1VidIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Request Pcie voltage change + * + * + * + * @param[in] VidIndex The request VID index + * @param[in] StdHeader Standard configuration header + */ +VOID +PcieSiliconRequestVoltage ( + IN UINT8 VidIndex, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ex488_STRUCT ex488 ; + ex489_STRUCT ex489 ; + + //Enable voltage client + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + 0x6a | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &ex488.Value, + StdHeader + ); + + ex488.Field.VoltageChangeEn = 0x1; + + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + 0x6a | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &ex488.Value, + StdHeader + ); + + ex488.Field.VoltageLevel = VidIndex; + ex488.Field.VoltageChangeReq = !ex488.Field.VoltageChangeReq; + + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + 0x6a | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &ex488.Value, + StdHeader + ); + do { + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + 0x6b | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &ex489.Value, + StdHeader + ); + } while (ex488.Field.VoltageChangeReq != ex489.Field.VoltageChangeAck); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Unhide all ports + * + * + * + * @param[in] Silicon Pointer to silicon configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieSiliconUnHidePorts ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + GnbLibPciIndirectRMW ( + Silicon->Address.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + (UINT32)~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), + 0x0, + GnbLibGetHeader (Pcie) + ); + GnbLibPciIndirectRMW ( + Silicon->Address.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + (UINT32)~BIT6, + BIT6, + GnbLibGetHeader (Pcie) + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Hide unused ports + * + * + * + * @param[in] Silicon Pointer to silicon configuration data area + * @param[in] Pcie Pointer to data area up to 256 byte + */ + +VOID +PcieSiliconHidePorts ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0x64_x0C_STRUCT D0F0x64_x0C; + PCIe_WRAPPER_CONFIG *WrapperList; + D0F0x64_x0C.Value = 0; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Enter\n"); + + D0F0x64_x0C.Value = BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7; + WrapperList = PcieConfigGetChildWrapper (Silicon); + while (WrapperList != NULL) { + PCIe_ENGINE_CONFIG *EngineList; + EngineList = PcieConfigGetChildEngine (WrapperList); + while (EngineList != NULL) { + if (PcieConfigIsPcieEngine (EngineList)) { + if (PcieConfigIsActivePcieEngine (EngineList) && !PcieConfigIsSbPcieEngine (EngineList)) { + D0F0x64_x0C.Value &= ~(1 << EngineList->Type.Port.Address.Address.Device); + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + WrapperList = PcieLibGetNextDescriptor (WrapperList); + } + + GnbLibPciIndirectRMW ( + Silicon->Address.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + (UINT32)~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), + D0F0x64_x0C.Value, + GnbLibGetHeader (Pcie) + ); + GnbLibPciIndirectRMW ( + Silicon->Address.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + (UINT32)~BIT6, + 0x0, + GnbLibGetHeader (Pcie) + ); + IDS_HDT_CONSOLE (GNB_TRACE, "Write D0F0x64_x0C.Value = %x\n", D0F0x64_x0C.Value); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Exit\n"); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h new file mode 100644 index 0000000000..22d07a113d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h @@ -0,0 +1,99 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe Complex Services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIESILICONSERVICES_H_ +#define _PCIESILICONSERVICES_H_ + +UINT8 +PcieSiliconGetGen1VoltageIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieSiliconRequestVoltage ( + IN UINT8 VidIndex, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieSiliconUnHidePorts ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSiliconHidePorts ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl new file mode 100644 index 0000000000..3c46ef675b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl @@ -0,0 +1,244 @@ +/** + * @file + * + * ALIB PSPP Pcie Smu Lib V1 + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + /*----------------------------------------------------------------------------------------*/ + /** + * SMU indirect register read + * + * Arg0 - Smu register offset + * + */ + Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) { + Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) + // Access 32 bit width + Increment (Arg0) + // Reverse ReqToggle + Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) + // Assign Address and ReqType = 0 + Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0) + + procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) + + Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0) + return (Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * SMU indirect register Write + * + * Arg0 - Smu register offset + * Arg1 - Value + * Arg2 - Width, 0 = 16, 1 = 32 + * + */ + Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) { + Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) + // Get low 16 bit value + Store (And (Arg1, 0xFFFF), Local1) + // Reverse ReqToggle + Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) + // Assign Address + Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0) + // ReqType = 1 + Or (Local0, 0x02000000, Local0) + // Assign Low 16 bit value + Or (Local0, Local1, Local0) + + procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) + + if (LEqual (Arg2, 1)) { + // Get high 16 bit value + Store (ShiftRight (Arg1, 16), Local1) + // Reverse ReqToggle + Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) + // Assign Address + Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0) + // Assign High 16 bit value + Or (Local0, Local1, Local0) + + procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) + } + + } + + /*----------------------------------------------------------------------------------------*/ + /** + * SMU Service request + * + * Arg0 - Smu service id + * Arg1 - Flags - Poll Ack = 1, Poll down = 2 + * + */ + Method (procNbSmuServiceRequest, 2, NotSerialized) { + Store ("NbSmuServiceRequest Enter", Debug) + Store ("Request id =", Debug) + Store (Arg0, Debug) + + Or (ShiftLeft (Arg0, 3), 0x1, Local0) + procNbSmuIndirectRegisterWrite (0x3, Local0, 1) + + if (LAnd (Arg1, 1)) { + while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) { + Store ("--Wait Ack--", Debug) + } + } + if (LAnd (Arg1, 2)) { + while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) { + Store ("--Wait Done--", Debug) + } + } + // Clear IRQ register + procNbSmuIndirectRegisterWrite (0x3, 0, 1) + Store ("NbSmuServiceRequest Exit", Debug) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Write RCU register + * + * Arg0 - Register Address + * Arg1 - Register Data + * + */ + Method (procSmuRcuWrite, 2, NotSerialized) { + procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) + procNbSmuIndirectRegisterWrite (0x5, Arg1, 1) + + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read RCU register + * + * Arg0 - Register Address + * Retval - RCU register value + */ + Method (procSmuRcuRead, 1, NotSerialized) { + procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) + Store (procNbSmuIndirectRegisterRead (0x5), Local0) + return (Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * SMU SRBM Register Read + * + * Arg0 - FCR register address + * + */ + Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) { + //SMUx0B_x8600 + Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) + //SMUx0B_x8604 + Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) + //SMUx0B_x8608 + Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) + //Write SMU RCU + procSmuRcuWrite (0x8600, Local0) + procSmuRcuWrite (0x8604, Local1) + procSmuRcuWrite (0x8608, Local2) + // ServiceId + if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) { + procNbSmuServiceRequest (0xD, 0x3) + } + if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) { + procNbSmuServiceRequest (0xB, 0x3) + } + return (procSmuRcuRead(0x8650)) + } + + + /*----------------------------------------------------------------------------------------*/ + /** + * SMU SRBM Register Write + * + * Arg0 - FCR register address + * Arg1 - Value + * + */ + Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) { + //SMUx0B_x8600 + Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) + //SMUx0B_x8604 + Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) + //SMUx0B_x8608 + Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) + Or (Local2, ShiftLeft (1, 16), Local2) + //Write SMU RCU + procSmuRcuWrite (0x8600, Local0) + procSmuRcuWrite (0x8604, Local1) + procSmuRcuWrite (0x8608, Local2) + //Write Data + procSmuRcuWrite (0x8650, Arg1) + // ServiceId + procNbSmuServiceRequest (0xB, 0x3) + } + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuVidReq.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuVidReq.esl new file mode 100644 index 0000000000..14a474d0e9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuVidReq.esl @@ -0,0 +1,107 @@ +/** + * @file + * + * ALIB PSPP Pcie Smu Lib V1 + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 61048 $ @e \$Date: 2011-10-31 12:20:41 +0800 (Mon, 31 Oct 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + /*----------------------------------------------------------------------------------------*/ + /** + * Request VID + * + * Arg0 - 1 - GEN1 2 - GEN2 + * Arg1 - 0 = do not wait intil voltage is set + * 1 = wait until voltage is set + */ + Method (procPcieSetVoltage, 2, Serialized) { + Store ("PcieSetVoltage Enter", Debug) + Store (procIndirectRegisterRead (0x0, 0x60, 0xEA), Local1) + //Enable voltage change + Or (Local1, 0x2, Local1) + procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1) + //Clear voltage index + And (Local1, Not (ShiftLeft (0x3, 3)), Local1) + + if (LEqual (Arg0, DEF_LINK_SPEED_GEN1)) { + Store (varGen1Vid, Local3) + } else { + Store (varGen2Vid, Local3) + } + + Store (Concatenate (" Voltage Index:", ToHexString (Local3), Local6), Debug) + //Set new voltage index + Or (Local1, ShiftLeft (Local3, 3), Local1) + //Togle request + And (Not (Local1), 0x4, Local2) + Or (And (Local1, Not (0x4)), Local2, Local1) + procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1) + if (LNotEqual (Arg1, 0)) { + while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) { + And (procIndirectRegisterRead (0x0, 0x60, 0xEB), 0x1, Local1) + } + } + Store ("PcieSetVoltage Exit", Debug) + } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c new file mode 100644 index 0000000000..49cea04a02 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe timer access procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbTimerLib.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Get PCIe timer timestamp + * + * + * + * @param[in] Pcie Pointer to internal configuration data area + * @retval Time stamp value + */ + +UINT32 +PcieTimerGetTimeStamp ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + return GnbLibTimeStamp (GnbLibGetHeader (Pcie)); +} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h new file mode 100644 index 0000000000..dfdf414f71 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h @@ -0,0 +1,82 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe timer access procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIETIMER_H_ +#define _PCIETIMER_H_ + +UINT32 +PcieTimerGetTimeStamp ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#define TIMESTAMPS_DELTA(Time2, Time1) ((Time2 > Time1) ? (Time2 - Time1) : (0xffffffffull - Time1 + Time2)) + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c new file mode 100644 index 0000000000..0a9c7b3fed --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -0,0 +1,804 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe topology initialization service procedures. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 66529 $ @e \$Date: 2012-03-09 08:32:22 -0600 (Fri, 09 Mar 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Cleanup reconfig + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyCleanUpReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (PcieLibIsPcieWrapper (Wrapper)) { + PcieRegisterRMW ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062_ConfigXferMode_MASK, + 1 << D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET, + FALSE, + Pcie + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Prepare for reconfiguration + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyPrepareForReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; + UINT8 CoreId; + if (PcieLibIsPcieWrapper (Wrapper)) { + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + PcieRegisterWriteField ( + Wrapper, + CORE_SPACE (CoreId, 0x11 ), + 0 , + 4 , + 0xf, + FALSE, + Pcie + ); + } + + D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0; + D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + } +} + + +UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate mux array index + * + * + * + * @param[in, out] LaneMuxSelectorArrayPtr Pointer to mux selector array + * @param[in] LaneMuxValue The value that match to array + * @retval Index Index successfully mapped + */ +STATIC UINT8 +PcieTopologyLocateMuxIndex ( + IN OUT UINT8 *LaneMuxSelectorArrayPtr, + IN UINT8 LaneMuxValue + ) +{ + UINT8 Index; + for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++ ) { + if (LaneMuxSelectorArrayPtr [Index] == LaneMuxValue) { + return Index; + } + } + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Apply lane mux + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieTopologyApplyLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT8 CurrentPhyLane; + UINT8 CurrentCoreLane; + UINT8 CoreLaneIndex; + UINT8 PhyLaneIndex; + UINT8 NumberOfPhyLane; + UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)]; + UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)]; + UINT8 Index; + UINT32 TxMaxSelectorValue; + UINT32 RxMaxSelectorValue; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Enter\n"); + if (PcieLibIsPcieWrapper (Wrapper)) { + EngineList = PcieConfigGetChildEngine (Wrapper); + LibAmdMemCopy ( + &TxLaneMuxSelectorArray[0], + &LaneMuxSelectorTable[0], + sizeof (LaneMuxSelectorTable), + GnbLibGetHeader (Pcie) + ); + LibAmdMemCopy ( + &RxLaneMuxSelectorArray[0], + &LaneMuxSelectorTable[0], + sizeof (LaneMuxSelectorTable), + GnbLibGetHeader (Pcie) + ); + while (EngineList != NULL) { + if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { + CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; + NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList); + CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane; + if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) { + CurrentCoreLane = CurrentCoreLane + PcieConfigGetNumberOfCoreLane (EngineList) - NumberOfPhyLane; + } + for (Index = 0; Index < NumberOfPhyLane; Index = Index + 2 ) { + CoreLaneIndex = (CurrentCoreLane + Index) / 2; + PhyLaneIndex = (CurrentPhyLane + Index) / 2; + + if (RxLaneMuxSelectorArray [CoreLaneIndex] != PhyLaneIndex) { + RxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (RxLaneMuxSelectorArray, PhyLaneIndex)] = RxLaneMuxSelectorArray [CoreLaneIndex]; + RxLaneMuxSelectorArray [CoreLaneIndex] = PhyLaneIndex; + } + if (TxLaneMuxSelectorArray [PhyLaneIndex] != CoreLaneIndex) { + TxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (TxLaneMuxSelectorArray, CoreLaneIndex)] = TxLaneMuxSelectorArray [PhyLaneIndex]; + TxLaneMuxSelectorArray [PhyLaneIndex] = CoreLaneIndex; + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + RxMaxSelectorValue = 0; + TxMaxSelectorValue = 0; + for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++) { + RxMaxSelectorValue |= (RxLaneMuxSelectorArray[Index] << (Index * 4)); + TxMaxSelectorValue |= (TxLaneMuxSelectorArray[Index] << (Index * 4)); + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS), + TxMaxSelectorValue, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS), + RxMaxSelectorValue, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Select master PLL + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[out] ConfigChanged Pointer to boolean indicator that configuration was changed + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieTopologySelectMasterPll ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT16 MasterLane; + UINT16 MasterHotplugLane; + D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013; + D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013_BASE; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n"); + MasterLane = 0xFFFF; + MasterHotplugLane = 0xFFFF; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieConfigIsEngineAllocated (EngineList) && EngineList->Type.Port.PortData.PortPresent != PortDisabled && PcieConfigIsPcieEngine (EngineList)) { + if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + MasterHotplugLane = PcieConfigGetPcieEngineMasterLane (EngineList); + } else { + MasterLane = PcieConfigGetPcieEngineMasterLane (EngineList); + if (PcieConfigIsSbPcieEngine (EngineList)) { + break; + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + + if (MasterLane == 0xffff) { + if (MasterHotplugLane != 0xffff) { + MasterLane = MasterHotplugLane; + } else { + MasterLane = 0x0; + } + } + + D0F0xE4_WRAP_8013.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8013_BASE.Value = D0F0xE4_WRAP_8013.Value; + if ( MasterLane <= 3 ) { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; + Wrapper->MasterPll = 0xA; + } else if (MasterLane <= 7) { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1; + D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; + Wrapper->MasterPll = 0xB; + } else if (MasterLane <= 11) { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x1; + D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; + Wrapper->MasterPll = 0xC; + } else { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x1; + Wrapper->MasterPll = 0xD; + } + if (ConfigChanged != NULL) { + *ConfigChanged = (D0F0xE4_WRAP_8013.Value == D0F0xE4_WRAP_8013_BASE.Value) ? FALSE : TRUE; + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + D0F0xE4_WRAP_8013.Value, + FALSE, + Pcie + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute/clean up reconfiguration + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyExecuteReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; + D0F0xE4_WRAP_8060_STRUCT D0F0xE4_WRAP_8060; + + if (PcieLibIsPcieWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Enter\n"); + + PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie); + + D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8060.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + D0F0xE4_WRAP_8060.Field.Reconfigure = 0x1; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), + D0F0xE4_WRAP_8060.Value, + FALSE, + Pcie + ); + do { + D0F0xE4_WRAP_8060.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), + Pcie + ); + + } while (D0F0xE4_WRAP_8060.Field.Reconfigure == 1); + D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable lane reversal + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologySetLinkReversal ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n"); + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + if (PcieLibIsPcieEngine (EngineList)) { + if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) { + PciePortRegisterWriteField ( + EngineList, + 0xc1 , + 4 , + 1 , + 0x1, + FALSE, + Pcie + ); + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Reduce link width + * + * + * @param[in] LinkWidth Link width + * @param[in] Engine Pointer to Engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyReduceLinkWidth ( + IN UINT8 LinkWidth, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_WRAPPER_CONFIG *Wrapper; + UINT32 LinkReversed; + UINT8 DeltaLinkWidthBitmap; + UINT32 LanesToDisable; + Wrapper = PcieConfigGetParentWrapper (Engine); + LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie); + + DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1; + LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane + LinkWidth))); + + PcieTopologyLaneControl ( + DisableLanes, + LanesToDisable, + Wrapper, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Lanes enable/disable control + * + * @param[in] Control Lane control action + * @param[in] LaneBitMap Core lanes bitmap + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyLaneControl ( + IN LANE_CONTROL Control, + IN UINT32 LaneBitMap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8023_STRUCT D0F0xE4_WRAP_8023; + D0F0xE4_WRAP_8023.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), + Pcie + ); + + if (Control == EnableLanes) { + D0F0xE4_WRAP_8023.Value |= LaneBitMap; + } else if (Control == DisableLanes) { + D0F0xE4_WRAP_8023.Value &= (~LaneBitMap); + } + D0F0xE4_WRAP_8023.Value &= ((1 << Wrapper->NumberOfLanes) - 1); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), + D0F0xE4_WRAP_8023.Value, + TRUE, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init SRBM reset + * + * @param[in] SrbmResetEnable SRBM reset enable flag. + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyInitSrbmReset ( + IN BOOLEAN SrbmResetEnable, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8063_STRUCT D0F0xE4_WRAP_8063; + D0F0xE4_WRAP_8063.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS), + Pcie + ); + if (SrbmResetEnable) { + D0F0xE4_WRAP_8063.Field.line331 = 0x1; + D0F0xE4_WRAP_8063.Field.line332 = 0x1; + D0F0xE4_WRAP_8063.Field.line338 = 0x1; + D0F0xE4_WRAP_8063.Field.line339 = 0x1; + D0F0xE4_WRAP_8063.Field.line340 = 0x1; + } else { + D0F0xE4_WRAP_8063.Field.line331 = 0x0; + D0F0xE4_WRAP_8063.Field.line332 = 0x0; + D0F0xE4_WRAP_8063.Field.line338 = 0x0; + D0F0xE4_WRAP_8063.Field.line339 = 0x0; + D0F0xE4_WRAP_8063.Field.line340 = 0x0; + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS), + D0F0xE4_WRAP_8063.Value, + FALSE, + Pcie + ); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set core configuration according to PCIe port topology + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[out] ConfigChanged Pointer to boolean indicator that configuration was changed + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +PcieTopologySetCoreConfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 CoreId; + AGESA_STATUS Status; + D0F0xE4_WRAP_0080_STRUCT D0F0xE4_WRAP_0080; + + Status = AGESA_SUCCESS; + if (PcieLibIsPcieWrapper (Wrapper)) { + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + UINT64 ConfigurationSignature; + UINT8 NewConfigurationValue; + ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId); + Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue); + if (Status == AGESA_SUCCESS) { + IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s\n", + PcieFmDebugGetWrapperNameString (Wrapper), + CoreId, + PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue) + ); + D0F0xE4_WRAP_0080.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS), + Pcie + ); + if (ConfigChanged != NULL) { + if (D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig != NewConfigurationValue) { + *ConfigChanged = TRUE; + } + } + D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig = NewConfigurationValue; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS), + D0F0xE4_WRAP_0080.Value, + FALSE, + Pcie + ); + } else { + IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n", + PcieFmDebugGetWrapperNameString (Wrapper), + ((UINT32*)&ConfigurationSignature)[1], + ((UINT32*)&ConfigurationSignature)[0] + ); + PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); + } + } + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Relinquish control to DDI for specific lanes + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieSetDdiOwnPhy ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + ex502_STRUCT ex502 ; + UINT32 LaneBitmap; + + if (PcieLibIsDdiWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Enter\n"); + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); + ex502.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x8040 ), + Pcie + ); + if ((LaneBitmap & BIT0) != 0) { + ex502.Field.OwnPhyA = 0x1; + } + if ((LaneBitmap & BIT4) != 0) { + ex502.Field.OwnPhyB = 0x1; + } + if ((LaneBitmap & BIT8) != 0) { + ex502.Field.OwnPhyC = 0x1; + } + if ((LaneBitmap & BIT12) != 0) { + ex502.Field.OwnPhyD = 0x1; + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x8040 ), + ex502.Value, + FALSE, + Pcie + ); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set TX control for PCIe lanes + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieWrapSetTxS1CtrlForLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8025_STRUCT D0F0xE4_WRAP_8025; + UINT32 LaneBitmap; + UINTN Index; + D0F0xE4_WRAP_8025.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), + Pcie + ); + Index = 0; + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper); + while (LaneBitmap != 0) { + if ((LaneBitmap & 0xf) != 0) { + D0F0xE4_WRAP_8025.Value &= (~(0xff << (Index * 8))); + D0F0xE4_WRAP_8025.Value |= (((0x03 << 3) | 0x1) << (Index * 8)); + } + LaneBitmap >>= 4; + ++Index; + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), + D0F0xE4_WRAP_8025.Value, + FALSE, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set TX control for lane muxes + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieWrapSetTxOffCtrlForLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), + 0x1f1f1f1f, + FALSE, + Pcie + ); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h new file mode 100644 index 0000000000..59c4ffcd94 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h @@ -0,0 +1,168 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe topology initialization service procedures. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. 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BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIETOPOLOGYSERVICES_H_ +#define _PCIETOPOLOGYSERVICES_H_ + +/// Lane Control +typedef enum { + EnableLanes, ///< Enable Lanes + DisableLanes ///< Disable Lanes +} LANE_CONTROL; + +VOID +PcieTopologyCleanUpReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyPrepareForReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieTopologySetCoreConfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyApplyLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologySelectMasterPll ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyExecuteReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologySetLinkReversal ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +VOID +PcieTopologyReduceLinkWidth ( + IN UINT8 LinkWidth, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyLaneControl ( + IN LANE_CONTROL Control, + IN UINT32 LaneBitMap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyInitSrbmReset ( + IN BOOLEAN SrbmResetEnable, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetDdiOwnPhy ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieWrapSetTxS1CtrlForLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieWrapSetTxOffCtrlForLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c new file mode 100644 index 0000000000..29dc02473b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c @@ -0,0 +1,688 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe utility. Various supporting functions. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/// Lane type +typedef enum { + LaneTypeCore, ///< Core Lane + LaneTypePhy, ///< Package Phy Lane + LaneTypeNativePhy ///< Native Phy Lane +} LANE_TYPE; + +/// Lane Property +typedef enum { + LanePropertyConfig, ///< Configuration + LanePropertyActive, ///< Active + LanePropertyAllocated ///< Allocated +} LANE_PROPERTY; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef struct { + UINT32 Flags; + PCIE_LINK_SPEED_CAP LinkSpeedCapability; +} PCIE_GLOBAL_GEN_CAP_WORKSPACE; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Get link state history from HW state machine + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[out] History Buffer to save history + * @param[in] Length Buffer length + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieUtilGetLinkHwStateHistory ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT UINT8 *History, + IN UINT8 Length, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 ReadLength; + UINT32 LocalHistory [6]; + UINT16 Index; + ASSERT (Length <= 16); + ASSERT (Length > 0); + if (Length > 6*4) { + Length = 6*4; + } + ReadLength = (Length + 3) / 4; + for (Index = 0; Index < ReadLength; Index++) { + LocalHistory[Index] = PciePortRegisterRead ( + Engine, + DxF0xE4_xA5_ADDRESS + Index, + Pcie + ); + } + LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie)); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Search array for specific pattern + * + * + * @param[in] Buf1 Pointer to source buffer which will be subject of search + * @param[in] Buf1Length Length of the source buffer + * @param[in] Buf2 Pointer to pattern buffer + * @param[in] Buf2Length Length of the pattern buffer + * @retval TRUE Pattern found + * @retval TRUE Pattern not found + */ + +BOOLEAN +PcieUtilSearchArray ( + IN UINT8 *Buf1, + IN UINTN Buf1Length, + IN UINT8 *Buf2, + IN UINTN Buf2Length + ) +{ + UINT8 *CurrentBuf1Ptr; + CurrentBuf1Ptr = Buf1; + while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { + UINT8 *SourceBufPtr; + UINT8 *PatternBufPtr; + UINTN PatternBufLength; + SourceBufPtr = CurrentBuf1Ptr; + PatternBufPtr = Buf2; + PatternBufLength = Buf2Length; + while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0)); + if (PatternBufLength == 0) { + return TRUE; + } + CurrentBuf1Ptr++; + } + return FALSE; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if link reversed + * + * + * @param[in] HwLinkState Check for HW auto link reversal + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to PCIe config descriptor + * @retval TRUE if link reversed + */ +BOOLEAN +PcieUtilIsLinkReversed ( + IN BOOLEAN HwLinkState, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 LinkReversal; + + LinkReversal = (Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? 1 : 0; + if (HwLinkState) { + DxF0xE4_x50_STRUCT DxF0xE4_x50; + DxF0xE4_x50.Value = PciePortRegisterRead ( + Engine, + DxF0xE4_x50_ADDRESS, + Pcie + ); + LinkReversal ^= DxF0xE4_x50.Field.PortLaneReversal; + } + return ((LinkReversal & BIT0) != 0) ? TRUE : FALSE; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get link width detected during training + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * @retval Link width + */ +UINT8 +PcieUtilGetLinkWidth ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkWidth; + DxF0xE4_xA2_STRUCT DxF0xE4_xA2; + DxF0xE4_xA2.Value = PciePortRegisterRead ( + Engine, + DxF0xE4_xA2_ADDRESS, + Pcie + ); + switch (DxF0xE4_xA2.Field.LcLinkWidthRd) { + case 0x6: + LinkWidth = 16; + break; + case 0x5: + LinkWidth = 12; + break; + case 0x4: + LinkWidth = 8; + break; + case 0x3: + LinkWidth = 4; + break; + case 0x2: + LinkWidth = 2; + break; + case 0x1: + LinkWidth = 1; + break; + default: + LinkWidth = 0; + } + return LinkWidth; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bitmap of PCIE engine lane of requested type + * + * + * @param[in] LaneType Lane type + * @param[in] LaneProperty Lane Property + * @param[in] Engine Pointer to engine config descriptor + * @retval Lane bitmap + */ + +STATIC UINT32 +PcieUtilGetPcieEngineLaneBitMap ( + IN LANE_TYPE LaneType, + IN LANE_PROPERTY LaneProperty, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT32 LaneBitmap; + UINT8 Width; + UINT16 Offset; + UINT16 LoPhylane; + UINT16 HiPhylane; + PCIe_PLATFORM_CONFIG *Pcie; + + Width = 0; + Offset = 0; + LaneBitmap = 0; + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); + + if (PcieConfigIsPcieEngine (Engine)) { + if (LaneType == LaneTypeCore && LaneProperty == LanePropertyConfig) { + Width = PcieConfigGetNumberOfCoreLane (Engine); + Offset = Engine->Type.Port.StartCoreLane; + LaneBitmap = ((1 << Width) - 1) << Offset; + } else if (PcieConfigIsEngineAllocated (Engine)) { + if (LaneType == LaneTypeNativePhy) { + LaneBitmap = PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine); + LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine); + } else { + if (LaneType == LaneTypeCore) { + if (LaneProperty == LanePropertyActive) { + Width = PcieUtilGetLinkWidth (Engine, Pcie); + Offset = PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane; + } else if (LaneProperty == LanePropertyAllocated) { + Width = PcieConfigGetNumberOfPhyLane (Engine); + Offset = PcieUtilIsLinkReversed (FALSE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane; + } + } + if (LaneType == LaneTypePhy) { + LoPhylane = PcieLibGetLoPhyLane (Engine); + HiPhylane = PcieLibGetHiPhyLane (Engine); + if (LaneProperty == LanePropertyActive) { + Width = PcieUtilGetLinkWidth (Engine, Pcie); + Offset = (PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (HiPhylane - Width + 1) : LoPhylane) - PcieConfigGetParentWrapper (Engine)->StartPhyLane; + } else if (LaneProperty == LanePropertyAllocated) { + Width = PcieConfigGetNumberOfPhyLane (Engine); + Offset = LoPhylane - PcieConfigGetParentWrapper (Engine)->StartPhyLane; + } + } + LaneBitmap = ((1 << Width) - 1) << Offset; + } + } + } + return LaneBitmap; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bitmap of PCIE engine lane of requested type + * + * + * @param[in] LaneType Lane type + * @param[in] LaneProperty Lane Property + * @param[in] Engine Pointer to engine config descriptor + * @retval Lane bitmap + */ + +STATIC UINT32 +PcieUtilGetDdiEngineLaneBitMap ( + IN LANE_TYPE LaneType, + IN LANE_PROPERTY LaneProperty, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT32 LaneBitmap; + UINT8 Width; + UINT16 Offset; + Width = 0; + Offset = 0; + LaneBitmap = 0; + if (PcieConfigIsDdiEngine (Engine)) { + if (PcieConfigIsEngineAllocated (Engine)) { + if (LaneType == LaneTypePhy && ((LaneProperty == LanePropertyActive && (Engine->InitStatus & INIT_STATUS_DDI_ACTIVE)) || (LaneProperty == LanePropertyAllocated))) { + Width = PcieConfigGetNumberOfPhyLane (Engine); + Offset = PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane; + LaneBitmap = ((1 << Width) - 1) << Offset; + } + if (LaneType == LaneTypeNativePhy) { + LaneBitmap = PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine); + LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine); + } + } + } + return LaneBitmap; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bitmap of engine lane of requested type + * + * + * @param[in] IncludeLaneType Include Lane type + * @param[in] ExcludeLaneType Exclude Lane type + * @param[in] Engine Pointer to engine config descriptor + * @retval Lane bitmap + */ + +UINT32 +PcieUtilGetEngineLaneBitMap ( + IN UINT32 IncludeLaneType, + IN UINT32 ExcludeLaneType, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT32 LaneBitmap; + LaneBitmap = 0; + if (IncludeLaneType & LANE_TYPE_PCIE_LANES) { + if (IncludeLaneType & LANE_TYPE_PCIE_CORE_CONFIG) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine); + } + if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)) { + if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); + } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); + } else { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyActive, Engine); + } + } + } + if ((IncludeLaneType & LANE_TYPE_PCIE_SB_CORE_CONFIG) && PcieConfigIsSbPcieEngine (Engine)) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine); + } + if ((IncludeLaneType & LANE_TYPE_PCIE_CORE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & LANE_TYPE_PCIE_PHY) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE)) { + if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); + } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); + } else { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine); + } + } + } + if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); + } + } + if (IncludeLaneType & LANE_TYPE_DDI_LANES) { + if (IncludeLaneType & LANE_TYPE_DDI_PHY) { + LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE) { + LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) { + LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine); + } + } + if (ExcludeLaneType != 0) { + LaneBitmap &= (~PcieUtilGetEngineLaneBitMap (ExcludeLaneType, 0, Engine)); + } + return LaneBitmap; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bitmap of phy lane confugred for master pll + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @retval Lane bitmap + */ + +STATIC UINT32 +PcieUtilGetMasterPllLaneBitMap ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + if (Wrapper->MasterPll != 0) { + return 0xf << (Wrapper->MasterPll - 0xA) * 4; + } + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bitmap of Wrapper lane of requested type + * + * + * @param[in] IncludeLaneType Include Lane type + * @param[in] ExcludeLaneType Exclude Lane type + * @param[in] Wrapper Pointer to wrapper config descriptor + * @retval Lane bitmap + */ + +UINT32 +PcieUtilGetWrapperLaneBitMap ( + IN UINT32 IncludeLaneType, + IN UINT32 ExcludeLaneType, + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT32 LaneBitmap; + EngineList = PcieConfigGetChildEngine (Wrapper); + LaneBitmap = 0; + if ((IncludeLaneType | ExcludeLaneType) != 0) { + if ((IncludeLaneType & LANE_TYPE_ALL) == LANE_TYPE_ALL) { + LaneBitmap = (1 << (Wrapper->NumberOfLanes)) - 1; + if (ExcludeLaneType != 0) { + LaneBitmap &= (~PcieUtilGetWrapperLaneBitMap (ExcludeLaneType, 0, Wrapper)); + } + } else { + while (EngineList != NULL) { + LaneBitmap |= PcieUtilGetEngineLaneBitMap (IncludeLaneType, ExcludeLaneType, EngineList); + EngineList = PcieLibGetNextDescriptor (EngineList); + } + if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) { + LaneBitmap |= PcieUtilGetMasterPllLaneBitMap (Wrapper); + } + if ((ExcludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) { + LaneBitmap &= (~PcieUtilGetMasterPllLaneBitMap (Wrapper)); + } + } + } + return LaneBitmap; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Program port register table + * + * + * + * @param[in] Table Pointer to table + * @param[in] Length number of entries + * @param[in] Engine Pointer to engine config descriptor + * @param[in] S3Save Save for S3 flag + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PciePortProgramRegisterTable ( + IN PCIE_PORT_REGISTER_ENTRY *Table, + IN UINTN Length, + IN PCIe_ENGINE_CONFIG *Engine, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINTN Index; + UINT32 Value; + for (Index = 0; Index < Length; Index++) { + Value = PciePortRegisterRead ( + Engine, + Table[Index].Reg, + Pcie + ); + Value &= (~Table[Index].Mask); + Value |= Table[Index].Data; + PciePortRegisterWrite ( + Engine, + Table[Index].Reg, + Value, + S3Save, + Pcie + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Lock registers + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieLockRegisters ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 CoreId; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n"); + if (PcieLibIsPcieWrapper (Wrapper)) { + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + PcieRegisterWriteField ( + Wrapper, + CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS), + D0F0xE4_CORE_0010_HwInitWrLock_OFFSET, + D0F0xE4_CORE_0010_HwInitWrLock_WIDTH, + 0x1, + TRUE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Training state handling + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Indicate if engine in non final state + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieUtilGlobalGenCapabilityCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability; + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + PCIE_HOTPLUG_TYPE HotPlugType; + UINT32 Flags; + + Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS; + GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer; + LinkSpeedCapability = PcieGen1; + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS; + } + HotPlugType = Engine->Type.Port.PortData.LinkHotplug; + if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) { + Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS; + } + if ((GlobalGenCapability->Flags & Flags) != 0) { + ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0); + LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine); + if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) { + GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Determine global GEN capability + * + * + * @param[in] Flags global GEN capability flags + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +PCIE_LINK_SPEED_CAP +PcieUtilGlobalGenCapability ( + IN UINT32 Flags, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP GlobalCapability; + PCIE_GLOBAL_GEN_CAP_WORKSPACE GlobalGenCap; + + GlobalGenCap.LinkSpeedCapability = PcieGen1; + GlobalGenCap.Flags = Flags; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieUtilGlobalGenCapabilityCallback, + &GlobalGenCap, + Pcie + ); + + GlobalCapability = GlobalGenCap.LinkSpeedCapability; + + return GlobalCapability; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h new file mode 100644 index 0000000000..207aeb6efe --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h @@ -0,0 +1,158 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe utility. Various supporting functions. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEUTILLIB_H_ +#define _PCIEUTILLIB_H_ + +/// Core lanes +typedef enum { + AllCoreLanes, ///< All core lanes + AllocatedCoreLanes, ///< Allocated core lanes + ActiveCoreLanes, ///< Active core lanes + HotplugCoreLanes, ///< Hot plug core lanes + SbCoreLanes, ///< South bridge core lanes +} CORE_LANES; + +/// DDI lanes +typedef enum { + DdiAllLanes, ///< All DDI Lanes + DdiActiveLanes ///< Active DDI Lanes +} DDI_LANES; + +BOOLEAN +PcieUtilSearchArray ( + IN UINT8 *Buf1, + IN UINTN Buf1Length, + IN UINT8 *Buf2, + IN UINTN Buf2Length + ); + +VOID +PcieUtilGetLinkHwStateHistory ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT UINT8 *History, + IN UINT8 Length, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +BOOLEAN +PcieUtilIsLinkReversed ( + IN BOOLEAN HwLinkState, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +UINT8 +PcieUtilGetLinkWidth ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +UINT32 +PcieUtilGetEngineLaneBitMap ( + IN UINT32 IncludeLaneType, + IN UINT32 ExcludeLaneType, + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT32 +PcieUtilGetWrapperLaneBitMap ( + IN UINT32 IncludeLaneType, + IN UINT32 ExcludeLaneType, + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +VOID +PciePortProgramRegisterTable ( + IN PCIE_PORT_REGISTER_ENTRY *Table, + IN UINTN Length, + IN PCIe_ENGINE_CONFIG *Engine, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieLockRegisters ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +PCIE_LINK_SPEED_CAP +PcieUtilGlobalGenCapability ( + IN UINT32 Flags, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c new file mode 100644 index 0000000000..a76bc5e0f5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c @@ -0,0 +1,324 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE +/*----------------------------------------------------------------------------------------*/ +/** + * Read PCIe register value. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to Wrapper descriptor + * @param[in] Address Register address + * @param[in] Pcie Pointer to global PCIe configuration + * @retval Register Value + */ +UINT32 +PcieRegisterRead ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) { + Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000); + } + return PcieSiliconRegisterRead (PcieConfigGetParentSilicon (Wrapper), Address, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PCIe register value. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Silicon Pointer to silicon descriptor + * @param[in] Address Register address + * @param[in] Pcie Pointer to global PCIe configuration + * @retval Register Value + */ + +UINT32 +PcieSiliconRegisterRead ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie)); + GnbLibPciRead (Silicon->Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie)); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe register value. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to wrapper descriptor + * @param[in] Address Register address + * @param[in] Value New register value + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieRegisterWrite ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) { + Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000); + } + PcieSiliconRegisterWrite ( + PcieConfigGetParentSilicon (Wrapper), + Address, + Value, + S3Save, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe register value. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Silicon Pointer to silicon descriptor + * @param[in] Address Register address + * @param[in] Value New register value + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieSiliconRegisterWrite ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + IDS_HDT_CONSOLE (PCIE_HOSTREG_TRACE, " *WR %s (%d:%d:%d):0x%08x = 0x%08x\n", + PcieFmDebugGetHostRegAddressSpaceString (Silicon, (UINT16) (Address >> 16)), + Silicon->Address.Address.Bus, + Silicon->Address.Address.Device, + Silicon->Address.Address.Function, + Address, + Value + ); + GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie)); + GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie)); +} +/*----------------------------------------------------------------------------------------*/ +/** + * Read PCIe register field. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to wrapper descriptor + * @param[in] Address Register address + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[in] Pcie Pointer to global PCIe configuration + * @retval Register field value + */ + +UINT32 +PcieRegisterReadField ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + Value = PcieRegisterRead (Wrapper, Address, Pcie); + Value = (Value >> FieldOffset) & (~(0xFFFFFFFF << FieldWidth)); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe register field. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to wrapper descriptor + * @param[in] Address Register address + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[in] Value Value to write + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ + + +VOID +PcieRegisterWriteField ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TempValue; + UINT32 Mask; + TempValue = PcieRegisterRead (Wrapper, Address, Pcie); + Mask = (~(0xFFFFFFFF << FieldWidth)); + Value &= Mask; + TempValue &= (~(Mask << FieldOffset)); + PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write PCIe register. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to wrapper descriptor + * @param[in] Address Register address + * @param[in] AndMask Value & (~AndMask) + * @param[in] OrMask Value | OrMask + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieRegisterRMW ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieSiliconRegisterRMW ( + PcieConfigGetParentSilicon (Wrapper), + Address, + AndMask, + OrMask, + S3Save, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write PCIe register. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Silicon Pointer to silicon descriptor + * @param[in] Address Register address + * @param[in] AndMask Value & (~AndMask) + * @param[in] OrMask Value | OrMask + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieSiliconRegisterRMW ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + Value = PcieSiliconRegisterRead (Silicon, Address, Pcie); + Value = (Value & (~AndMask)) | OrMask; + PcieSiliconRegisterWrite (Silicon, Address, Value, S3Save, Pcie); +} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h new file mode 100644 index 0000000000..c0e4e2ff60 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h @@ -0,0 +1,154 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEWRAPPERREGACC_H_ +#define _PCIEWRAPPERREGACC_H_ + +//#define WRAP_SPACE(w, x) (0x01300000ul | (w << 16) | (x)) +//#define CORE_SPACE(c, x) (0x00010000ul | (c << 24) | (x)) +//#define PHY_SPACE(w, p, x) (0x00200000ul | ((p + 1) << 24) | (w << 16) | (x)) +//#define PIF_SPACE(w, p, x) (0x00100000ul | ((p + 1) << 24) | (w << 16) | (x)) +#define IMP_SPACE(x) (0x01080000ul | (x)) + +UINT32 +PcieRegisterRead ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieRegisterWrite ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PcieRegisterReadField ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieRegisterWriteField ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieRegisterRMW ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PcieSiliconRegisterRead ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSiliconRegisterWrite ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSiliconRegisterRMW ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h new file mode 100644 index 0000000000..6b156fe300 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h @@ -0,0 +1,79 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe Init Library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBPCIEINITLIBV4_H_ +#define _GNBPCIEINITLIBV4_H_ + +#include "PcieWrapperServicesV4.h" +#include "PciePowerMgmtV4.h" +#include "PciePortServicesV4.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c new file mode 100644 index 0000000000..fe5430672e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c @@ -0,0 +1,322 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Configure Max Payload + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "PcieMaxPayloadV4.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEMAXPAYLOADV4_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + UINT8 MaxPayload; +} PCIE_MAX_PAYLOAD_DATA; + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +SCAN_STATUS +PcieGetMaxPayloadCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +SCAN_STATUS +PcieSetMaxPayloadCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +AGESA_STATUS +PciePayloadBlackListFeature ( + IN PCI_ADDR Device, + IN UINT8 *MaxPayload, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Determine maximum payload size for PCIe segment + * + * Scan through all link in segment to determine maximum payload by EPs. + * + * @param[in] DownstreamPort PCI address of PCIe port + * @param[in] StdHeader Standard configuration header + * + */ + +VOID +PcieSetMaxPayload ( + IN PCI_ADDR DownstreamPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIE_MAX_PAYLOAD_DATA PcieMaxPayloadData; + + IDS_HDT_CONSOLE (GNB_TRACE, " PcieSetMaxPayload for Device = %d:%d:%d\n", + DownstreamPort.Address.Bus, + DownstreamPort.Address.Device, + DownstreamPort.Address.Function + ); + PcieMaxPayloadData.MaxPayload = MAX_PAYLOAD; + PcieMaxPayloadData.ScanData.StdHeader = StdHeader; + PcieMaxPayloadData.ScanData.GnbScanCallback = PcieGetMaxPayloadCallback; + GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData); + PcieMaxPayloadData.ScanData.GnbScanCallback = PcieSetMaxPayloadCallback; + GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData); + IDS_HDT_CONSOLE (GNB_TRACE, " PcieSetMaxPayloadExit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device Max Payload - save SMALLEST Max Payload for PCIe Segment + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +SCAN_STATUS +PcieGetMaxPayloadCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + PCIE_MAX_PAYLOAD_DATA *PcieMaxPayloadData; + PCIE_DEVICE_TYPE DeviceType; + UINT32 Value; + UINT8 PcieCapPtr; + UINT8 DeviceMaxPayload; + + PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " PcieGetMaxPayloadCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRead ( + Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER), + AccessWidth32, + &Value, + ScanData->StdHeader + ); + DeviceMaxPayload = (UINT8) (Value & 0x7); + PciePayloadBlackListFeature (Device, &DeviceMaxPayload, ScanData->StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, " Found DeviceMaxPayload as %d (Value = %x\n", DeviceMaxPayload, Value); + if (DeviceMaxPayload < PcieMaxPayloadData->MaxPayload) { + PcieMaxPayloadData->MaxPayload = DeviceMaxPayload; + } + } + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + case PcieDeviceUpstreamPort: + GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData); + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + break; + default: + break; + } + return SCAN_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure the Max Payload setting to all devices in the PCIe Segment + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +SCAN_STATUS +PcieSetMaxPayloadCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + PCIE_MAX_PAYLOAD_DATA *PcieMaxPayloadData; + PCIE_DEVICE_TYPE DeviceType; + UINT8 PcieCapPtr; + + PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " PcieSetMaxPayloadCallback for Device = %d:%d:%d to %d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function, + PcieMaxPayloadData->MaxPayload + ); + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRMW ( + Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CTRL_REGISTER), + AccessWidth32, + ~(UINT32) (0x7 << 5), + ((UINT32)PcieMaxPayloadData->MaxPayload << 5), + ScanData->StdHeader + ); + } + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + case PcieDeviceUpstreamPort: + GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData); + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + break; + default: + break; + } + return SCAN_SUCCESS; +} + +UINT16 PayloadBlacklistDeviceTable[] = { + 0x1969, 0x1083, (UINT16) MAX_PAYLOAD_128 +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Max_Payload_Size Black List + * + * + * + * @param[in] Device PCI_ADDR of PCIe Device to evaluate + * @param[in] MaxPayload Pointer to Max_Payload_Size value + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PciePayloadBlackListFeature ( + IN PCI_ADDR Device, + IN UINT8 *MaxPayload, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TargetDeviceId; + UINTN i; + UINT32 DeviceId; + UINT32 VendorId; + + GnbLibPciRead (Device.AddressValue, AccessWidth32, &TargetDeviceId, StdHeader); + for (i = 0; i < (sizeof (PayloadBlacklistDeviceTable) / sizeof (UINT16)); i = i + 3) { + VendorId = PayloadBlacklistDeviceTable[i]; + DeviceId = PayloadBlacklistDeviceTable[i + 1]; + if (VendorId == (UINT16)TargetDeviceId) { + if (DeviceId == 0xFFFF || DeviceId == (TargetDeviceId >> 16)) { + *MaxPayload = (UINT8) PayloadBlacklistDeviceTable[i + 2]; + } + } + } + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.h new file mode 100644 index 0000000000..470235e4cc --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Configure Max Payload + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEMAXPAYLOADV4_H_ +#define _PCIEMAXPAYLOADV4_H_ + +VOID +PcieSetMaxPayload ( + IN PCI_ADDR DownstreamPort, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c new file mode 100644 index 0000000000..d90d6cdce7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c @@ -0,0 +1,215 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "PciePortServicesV4.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set current link speed + * + * + * @param[in] LinkSpeedCapability Link Speed Capability + * @param[in] Engine Pointer to engine configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieSetLinkSpeedCapV4 ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + DxF0xE4_xA4_STRUCT DxF0xE4_xA4; + DxF0xE4_xC0_STRUCT DxF0xE4_xC0; + DxF0x88_STRUCT DxF0x88; + GnbLibPciRead ( + Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, + AccessWidth32, + &DxF0x88.Value, + GnbLibGetHeader (Pcie) + ); + DxF0xE4_xA4.Value = PciePortRegisterRead ( + Engine, + DxF0xE4_xA4_ADDRESS, + Pcie + ); + DxF0xE4_xC0.Value = PciePortRegisterRead ( + Engine, + DxF0xE4_xC0_ADDRESS, + Pcie + ); + + switch (LinkSpeedCapability) { + case PcieGen2: + DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1; + DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1; + DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0; + DxF0x88.Field.TargetLinkSpeed = 0x2; + DxF0x88.Field.HwAutonomousSpeedDisable = 0x0; + break; + case PcieGen1: + DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0; + DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0; + DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1; + DxF0x88.Field.TargetLinkSpeed = 0x1; + DxF0x88.Field.HwAutonomousSpeedDisable = 0x1; + PcieRegisterWriteField ( + PcieConfigGetParentWrapper (Engine), + WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId), + D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET, + D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH, + 0, + FALSE, + Pcie + ); + break; + default: + ASSERT (FALSE); + break; + } + PciePortRegisterWrite ( + Engine, + DxF0xE4_xA4_ADDRESS, + DxF0xE4_xA4.Value, + FALSE, + Pcie + ); + PciePortRegisterWrite ( + Engine, + DxF0xE4_xC0_ADDRESS, + DxF0xE4_xC0.Value, + FALSE, + Pcie + ); + GnbLibPciWrite ( + Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, + AccessWidth32, + &DxF0x88.Value, + GnbLibGetHeader (Pcie) + ); +} +/*----------------------------------------------------------------------------------------*/ +/** + * Enable passing TLP prefix to IOMMU if IOMMU enabled + * + * + * @param[in] Engine Pointer to engine configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieInitPortForIommuV4 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePortRegisterRMW ( + Engine, + DxF0xE4_xC1_ADDRESS, + DxF0xE4_xC1_StrapE2EPrefixEn_MASK | DxF0xE4_xC1_StrapExtendedFmtSupported_MASK, + (1 << DxF0xE4_xC1_StrapE2EPrefixEn_OFFSET) | (1 << DxF0xE4_xC1_StrapExtendedFmtSupported_OFFSET), + TRUE, + Pcie + ); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h new file mode 100644 index 0000000000..1420e4712b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h @@ -0,0 +1,91 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEPORTSERVICESV4_H_ +#define _PCIEPORTSERVICESV4_H_ + + +VOID +PcieSetLinkSpeedCapV4 ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieInitPortForIommuV4 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c new file mode 100644 index 0000000000..30a901191f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c @@ -0,0 +1,328 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Power saving features/services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Clock gating + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePwrClockGatingV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011; + D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012; + D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014; + D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015; + D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016; + UINT8 CoreId; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingV4 Enter\n"); + D0F0xE4_WRAP_8014.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8015.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8012.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8011.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), + Pcie + ); + + if (Wrapper->Features.ClkGating == 0x1) { + D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1; + D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1; + + D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1; + + D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1; + + + D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1; + D0F0xE4_WRAP_8011.Field.RcvrDetClkEnable = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f; + D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f; + D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f; + + D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7; + D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1; + D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1; + D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7; + D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1; + D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1; + + D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1; + D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0; + D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1; + D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f; + D0F0xE4_WRAP_8015.Field.line477 = 0x0; + D0F0xE4_WRAP_8015.Field.line478 = 0x0; + D0F0xE4_WRAP_8015.Field.line479 = 0x3; + D0F0xE4_WRAP_8015.Field.line480 = 0x1; + D0F0xE4_WRAP_8015.Field.line482 = 0x0; + D0F0xE4_WRAP_8015.Field.line483 = 0x0; + D0F0xE4_WRAP_8015.Field.line484 = 0x0; + D0F0xE4_WRAP_8015.Field.line485 = 0x1; + D0F0xE4_WRAP_8015.Field.line486 = 0x1; + + D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGateDigCEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGateDigDEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1; + } + if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) { + D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1; + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), + D0F0xE4_WRAP_8014.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), + D0F0xE4_WRAP_8015.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), + D0F0xE4_WRAP_8012.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), + D0F0xE4_WRAP_8011.Value, + TRUE, + Pcie + ); + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + PcieRegisterWriteField ( + Wrapper, + CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS), + D0F0xE4_CORE_0011_DynClkLatency_OFFSET, + D0F0xE4_CORE_0011_DynClkLatency_WIDTH, + 0xf, + TRUE, + Pcie + ); + } + if (Wrapper->Features.LclkGating == 0x1) { + D0F0xE4_WRAP_8016.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1; + D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), + D0F0xE4_WRAP_8016.Value, + TRUE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingV4 Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down DDI plls + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePwrPowerDownDdiPllsV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownDdiPllsV4 Enter\n"); + if (PcieConfigIsDdiWrapper (Wrapper) && !PcieConfigIsPcieWrapper (Wrapper)) { + PcieRegisterRMW ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8020_ADDRESS), + D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK, + 0x1 << D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET, + FALSE, + Pcie + ); + PciePollPifForCompeletion (Wrapper, Pcie); + PcieRegisterRMW ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), + D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK | D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK, + (0x1 << D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET) | (0x1 << D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET), + FALSE, + Pcie + ); + PciePollPifForCompeletion (Wrapper, Pcie); + PcieRegisterRMW ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), + D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK | D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK, + (0x7 << D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET) | (0x7 << D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET), + FALSE, + Pcie + ); + PcieRegisterRMW ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8020_ADDRESS), + D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK, + 0x0 << D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownDdiPllsV4 Exit\n"); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h new file mode 100644 index 0000000000..447571edbb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h @@ -0,0 +1,86 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Power saving features/services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEPOWERSAVINGFEATURESV4_H_ +#define _PCIEPOWERSAVINGFEATURESV4_H_ + +VOID +PciePwrClockGatingV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePwrPowerDownDdiPllsV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieServiceV4.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieServiceV4.esl new file mode 100644 index 0000000000..d7ea99ffbc --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieServiceV4.esl @@ -0,0 +1,89 @@ +/** + * @file + * + * ALIB PSPP Pcie Smu Lib V1 + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 55681 $ @e \$Date: 2011-06-24 14:34:00 -0700 (Fri, 24 Jun 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + + +/*----------------------------------------------------------------------------------------*/ + /** + * Get current link speed + * + * Arg0 - Port Index + * + */ + + + Method (procPciePortGetCurrentLinkSpeed, 1, NotSerialized) { + Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcLinkCtrlLocal1) + ShiftRight (varLcLinkCtrlLocal1, 13, varCurrenLinkSpeedLocal2) + And (varCurrenLinkSpeedLocal2, 0x3, varCurrenLinkSpeedLocal2); + Increment (varCurrenLinkSpeedLocal2) + return (varCurrenLinkSpeedLocal2) + } \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl new file mode 100644 index 0000000000..5486edbc97 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl @@ -0,0 +1,105 @@ +/** + * @file + * + * ALIB PSPP Pcie Smu Lib V1 + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + /*----------------------------------------------------------------------------------------*/ + /** + * SMU Service request + * + * Arg0 - Smu service id + * + */ + Method (procNbSmuServiceRequest, 1, NotSerialized) { + Store ("NbSmuServiceRequest Enter", Debug) + Store (Concatenate (" Request id = ", ToHexString (Arg0), Local6), Debug) + + while (LNotEqual (And (procIndirectRegisterRead (0x0, 0xB8, 0xE0003004), 0x2), 0x2)) { + Store ("--Wait Init Done--", Debug) + } + + Store (procIndirectRegisterRead (0x0, 0xB8, 0xE0003000), Local0) + // Reverse IntToggle[0], clean ServiceIndex[16:1] + Or (And (Local0, 0xFFFE0000), And (Not (And (Local0, 0x00000001)), 0x1), Local0) + // Assign ID + Or (Local0, ShiftLeft (Arg0, 1), Local0) + procIndirectRegisterWrite (0x0, 0xB8, 0xE0003000, Local0) + + while (LNotEqual (And (procIndirectRegisterRead (0x0, 0xB8, 0xE0003004), 0x1), 0x1)) { + Store ("--Wait Init Ack--", Debug) + } + + while (LNotEqual (And (procIndirectRegisterRead (0x0, 0xB8, 0xE0003004), 0x2), 0x2)) { + Store ("--Wait Init Done--", Debug) + } + + Store ("NbSmuServiceRequest Exit", Debug) + } + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuVidReqV4.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuVidReqV4.esl new file mode 100644 index 0000000000..b91ea6c028 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuVidReqV4.esl @@ -0,0 +1,124 @@ +/** + * @file + * + * ALIB PSPP Pcie Smu Lib V1 + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + + + /*----------------------------------------------------------------------------------------*/ + /** + * Request VID + * + * Arg0 - 1 - GEN1 2 - GEN2 + * Arg1 - 0 = do not wait intil voltage is set + * 1 = wait until voltage is set + */ + Method (procPcieSetVoltage, 2, Serialized) { + Store ("PcieSetVoltage Enter", Debug) + // Get real vid by index + if (LEqual (Arg0, DEF_LINK_SPEED_GEN1)) { + Store (DeRefOf (Index (varSclkVid, varGen1Vid)), local3) + } else { + Store (DeRefOf (Index (varSclkVid, varGen2Vid)), local3) + } + + // GMMx63C/GMMx640 -- CG_Reg = reg - 0x600 + // Store REQ in local2 + And (procIndirectRegisterRead (0x0, 0xB8, 0xE000203C), 0x4, Local2) + // Store ACK in local1 + And (procIndirectRegisterRead (0x0, 0xB8, 0xE0002040), 0x1, Local1) + // Compare REQ with ACK + while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) { + And (procIndirectRegisterRead (0x0, 0xB8, 0xE0002040), 0x1, Local1) + } + Store (procIndirectRegisterRead (0x0, 0xB8, 0xE000203C), Local1) + //Enable voltage change + if (LEqual (Arg0, DEF_LINK_SPEED_GEN1)) { + And (Local1, 0xFFFFFFFD, Local1) + } else { + Or (Local1, 0x2, Local1) + } + procIndirectRegisterWrite (0x0, 0xB8, 0xE000203C, Local1) + //Clear voltage index + And (Local1, Not (ShiftLeft (0xFF, 8)), Local1) + + Store (Concatenate (" Voltage Index:", ToHexString (local3), Local6), Debug) + //Set new voltage index + Or (Local1, ShiftLeft (local3, 8), Local1) + //Togle request + And (Not (Local1), 0x4, Local2) + Or (And (Local1, Not (0x4)), Local2, Local1) + procIndirectRegisterWrite (0x0, 0xB8, 0xE000203C, Local1) + if (LNotEqual (Arg1, 0)) { + while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) { + And (procIndirectRegisterRead (0x0, 0xB8, 0xE0002040), 0x1, Local1) + } + } + Store ("PcieSetVoltage Exit", Debug) + } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c new file mode 100644 index 0000000000..15cabc76d6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c @@ -0,0 +1,277 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe wrapper services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "PcieWrapperServicesV4.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Relinquish control to DDI for specific lanes + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieSetDdiOwnPhyV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + + UINT32 LaneBitmap; + UINT8 Slice; + if (PcieLibIsDdiWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Enter\n"); + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); + for (Slice = 0; Slice < 4; Slice++) { + if ((LaneBitmap & (1 << (Slice * 4))) != 0) { + PcieRegisterRMW ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS + Slice), + D0F0xE4_WRAP_8040_OwnSlice_MASK, + 1 << D0F0xE4_WRAP_8040_OwnSlice_OFFSET, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute/clean up reconfiguration + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyExecuteReconfigV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; + PCIe_SILICON_CONFIG *Silicon; + + if (PcieLibIsPcieWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Enter\n"); + + PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie); + + D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + + Silicon = PcieConfigGetParentSilicon (Wrapper); + + GnbLibPciIndirectRMW ( + Silicon->Address.AddressValue | D0F0xB8_ADDRESS, + D0F0xBC_x1F630_ADDRESS, + AccessWidth32, + (UINT32) ~D0F0xBC_x1F630_RECONF_WRAPPER_MASK, + Wrapper->WrapId << D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET, + GnbLibGetHeader (Pcie) + ); + + GnbSmuServiceRequestV4 ( + Silicon->Address, + SMC_MSG_RECONFIGURE, + 0, + GnbLibGetHeader (Pcie) + ); + + D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set SSID + * + * + * @param[in] Ssid SSID + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieSetSsidV4 ( + IN UINT32 Ssid, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (PcieLibIsPcieWrapper (Wrapper)) { + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0046_ADDRESS), + Ssid, + FALSE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable lane reversal + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologySetLinkReversalV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n"); + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + if (PcieLibIsPcieEngine (EngineList)) { + if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) { + PciePortRegisterWriteField ( + EngineList, + DxF0xE4_xC1_ADDRESS, + DxF0xE4_xC1_StrapReverseLanes_OFFSET, + DxF0xE4_xC1_StrapReverseLanes_WIDTH, + 0x1, + FALSE, + Pcie + ); + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n"); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h new file mode 100644 index 0000000000..533f80b906 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h @@ -0,0 +1,104 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe wrapper services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEWRAPPERSERVICESV4_H_ +#define _PCIEWRAPPERSERVICESV4_H_ + + +VOID +PcieSetDdiOwnPhyV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +VOID +PcieTopologyExecuteReconfigV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetSsidV4 ( + IN UINT32 Ssid, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologySetLinkReversalV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h new file mode 100644 index 0000000000..71d852fbb3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h @@ -0,0 +1,78 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe training library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBPCIETRAININGV1_H_ +#define _GNBPCIETRAININGV1_H_ + +#include "PcieTraining.h" +#include "PcieWorkarounds.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c new file mode 100644 index 0000000000..8f7cbdaaf2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c @@ -0,0 +1,907 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link training + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "PcieWorkarounds.h" +#include "PcieTraining.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +PcieSetResetStateOnEngines ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTrainingCheckResetDuration ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTrainingDeassertReset ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTrainingBrokenLine ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTrainingGen2Fail ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +GNB_DEBUG_CODE ( +VOID +STATIC +PcieTrainingDebugDumpPortState ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); +); + +/*----------------------------------------------------------------------------------------*/ +/** + * Set link State + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] State State to set + * @param[in] UpdateTimeStamp Update time stamp + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieTrainingSetPortState ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIE_LINK_TRAINING_STATE State, + IN BOOLEAN UpdateTimeStamp, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TimeStamp; + CurrentEngine->Type.Port.State = (UINT8) State; + if (UpdateTimeStamp) { + TimeStamp = PcieTimerGetTimeStamp (Pcie); + CurrentEngine->Type.Port.TimeStamp = TimeStamp; + } + GNB_DEBUG_CODE ( + PcieTrainingDebugDumpPortState (CurrentEngine, Pcie) + ); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set state for all engines connected to same reset ID + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Pointer to Reset Id + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieSetResetStateOnEngines ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 ResetId; + ResetId = *(UINT8 *)Buffer; + if (Engine->Type.Port.PortData.ResetId == ResetId && !PcieConfigIsSbPcieEngine (Engine)) { + PcieTrainingSetPortState (Engine, LinkStateResetDuration, TRUE, Pcie); + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | DxF0x68_ADDRESS, + AccessWidth32, + (UINT32) ~DxF0x68_LinkDis_MASK, + 1 << DxF0x68_LinkDis_OFFSET, + GnbLibGetHeader (Pcie) + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Assert GPIO port reset. + * + * Transition to LinkStateResetDuration state + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingAssertReset ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SLOT_RESET_INFO ResetInfo; + ResetInfo.ResetControl = AssertSlotReset; + ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId; + LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie)); + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieSetResetStateOnEngines, + (VOID *)&CurrentEngine->Type.Port.PortData.ResetId, + Pcie + ); + AgesaPcieSlotResetControl (0, &ResetInfo); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check for reset duration + * + * Transition to LinkStateResetDuration state + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieTrainingCheckResetDuration ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TimeStamp; + TimeStamp = PcieTimerGetTimeStamp (Pcie); + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkGpioResetAssertionTime) { + PcieTrainingSetPortState (CurrentEngine, LinkStateResetExit, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Deassert GPIO port reset. + * + * Transition to LinkStateResetDuration state + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Platform configuration + * + */ +VOID +PcieTrainingDeassertReset ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SLOT_RESET_INFO ResetInfo; + ResetInfo.ResetControl = DeassertSlotReset; + ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId; + LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie)); + AgesaPcieSlotResetControl (0, &ResetInfo); + GnbLibPciRMW ( + CurrentEngine->Type.Port.Address.AddressValue | DxF0x68_ADDRESS, + AccessWidth32, + (UINT32) ~DxF0x68_LinkDis_MASK, + 0 << DxF0x68_LinkDis_OFFSET, + GnbLibGetHeader (Pcie) + ); + PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check for after reset deassertion timeout + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingCheckResetTimeout ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TimeStamp; + TimeStamp = PcieTimerGetTimeStamp (Pcie); + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkResetToTrainingTime) { + PcieTrainingSetPortState (CurrentEngine, LinkStateReleaseTraining, FALSE, Pcie); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Release training + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingRelease ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkTrainingState; + PcieRegisterWriteField ( + PcieConfigGetParentWrapper (CurrentEngine), + WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId), + D0F0xE4_WRAP_0800_HoldTraining_OFFSET, + D0F0xE4_WRAP_0800_HoldTraining_WIDTH, + 0, + FALSE, + Pcie + ); + if (CurrentEngine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + LinkTrainingState = LinkStateCompliance; + } else { + LinkTrainingState = LinkStateDetectPresence; + } + PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Detect presence of any EP on the link + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieTrainingDetectPresence ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkHwStateHistory[4]; + UINT32 TimeStamp; + PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie); + if (LinkHwStateHistory[0] > 4) { + PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie); + return; + } + TimeStamp = PcieTimerGetTimeStamp (Pcie); + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkReceiverDetectionPooling) { + PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie); + } +} + +UINT8 FailPattern1 [] = {0x2a, 0x6}; +UINT8 FailPattern2 [] = {0x2a, 0x9}; +UINT8 FailPattern3 [] = {0x2a, 0xb}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Detect Link State + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieTrainingDetectLinkState ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkHwStateHistory[16]; + UINT32 TimeStamp; + UINT8 LinkTrainingState; + PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie); + if (LinkHwStateHistory[0] == 0x10) { + PcieTrainingSetPortState (CurrentEngine, LinkStateL0, FALSE, Pcie); + return; + }; + TimeStamp = PcieTimerGetTimeStamp (Pcie); + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkL0Pooling) { + LinkTrainingState = LinkStateTrainingFail; + PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 16, Pcie); + if (LinkHwStateHistory[0] == 0x7) { + LinkTrainingState = LinkStateCompliance; + } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern1, sizeof (FailPattern1))) { + LinkTrainingState = LinkStateBrokenLane; + } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern2, sizeof (FailPattern2))) { + LinkTrainingState = LinkStateGen2Fail; + } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern3, sizeof (FailPattern3))) { + LinkTrainingState = LinkStateGen2Fail; + } + PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Broken Lane + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieTrainingBrokenLine ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 CurrentLinkWidth; + UINT8 LinkTrainingState; + CurrentLinkWidth = PcieUtilGetLinkWidth (CurrentEngine, Pcie); + if (CurrentLinkWidth < PcieConfigGetNumberOfPhyLane (CurrentEngine) && CurrentLinkWidth > 0) { + CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY; + PcieTopologyReduceLinkWidth (CurrentLinkWidth, CurrentEngine, Pcie); + LinkTrainingState = LinkStateResetAssert; + PutEventLog ( + AGESA_WARNING, + GNB_EVENT_BROKEN_LANE_RECOVERY, + CurrentEngine->Type.Port.Address.AddressValue, + 0, + 0, + 0, + GnbLibGetHeader (Pcie) + ); + } else { + LinkTrainingState = LinkStateGen2Fail; + } + PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if link fail because device does not support Gen2 + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieTrainingGen2Fail ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkTrainingState; + if (CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode != PcieGen1) { + PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_GEN2_RECOVERY, 0); + CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode = PcieGen1; + PcieLinkSafeMode (CurrentEngine, Pcie); + LinkTrainingState = LinkStateResetAssert; + PutEventLog ( + AGESA_WARNING, + GNB_EVENT_BROKEN_LANE_RECOVERY, + CurrentEngine->Type.Port.Address.AddressValue, + 0, + 0, + 0, + GnbLibGetHeader (Pcie) + ); + } else { + LinkTrainingState = LinkStateTrainingFail; + } + PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Link in L0 + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieCheckLinkL0 ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie); +} +/*----------------------------------------------------------------------------------------*/ +/** + * Check if link fail because device does not support Gen X + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingCheckVcoNegotiation ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TimeStamp; + DxF0x128_STRUCT DxF0x128; + TimeStamp = PcieTimerGetTimeStamp (Pcie); + GnbLibPciRead (CurrentEngine->Type.Port.Address.AddressValue | DxF0x128_ADDRESS, AccessWidth32, &DxF0x128, GnbLibGetHeader (Pcie)); + if (DxF0x128.Field.VcNegotiationPending == 0) { + UINT16 NumberOfPhyLane; + NumberOfPhyLane = PcieConfigGetNumberOfPhyLane (CurrentEngine); + if (Pcie->GfxCardWorkaround == GfxWorkaroundEnable && NumberOfPhyLane >= 8) { + // Limit exposure of workaround to x8 and x16 port. + PcieTrainingSetPortState (CurrentEngine, LinkStateGfxWorkaround, TRUE, Pcie); + } else { + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie); + } + return; + } + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 1000) { + PcieTrainingSetPortState (CurrentEngine, LinkStateRetrain, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if for GFX workaround condition + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingGfxWorkaround ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TimeStamp; + GFX_WORKAROUND_STATUS GfxWorkaroundStatus; + TimeStamp = PcieTimerGetTimeStamp (Pcie); + + GfxWorkaroundStatus = PcieGfxCardWorkaround (CurrentEngine->Type.Port.Address, GnbLibGetHeader (Pcie)); + switch (GfxWorkaroundStatus) { + case GFX_WORKAROUND_DEVICE_NOT_READY: + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= (3 * 1000000)) { + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie); + } + break; + case GFX_WORKAROUND_SUCCESS: + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie); + break; + case GFX_WORKAROUND_RESET_DEVICE: + if (CurrentEngine->Type.Port.GfxWrkRetryCount < 5) { + CurrentEngine->Type.Port.GfxWrkRetryCount++; + PcieTrainingSetPortState (CurrentEngine, LinkStateResetAssert, TRUE, Pcie); + } else { + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie); + } + break; + default: + ASSERT (FALSE); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Retrain link + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingRetrainLink ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePortRegisterWriteField ( + CurrentEngine, + DxF0xE4_xA2_ADDRESS, + DxF0xE4_xA2_LcReconfigNow_OFFSET, + DxF0xE4_xA2_LcReconfigNow_WIDTH, + 1, + FALSE, + Pcie + ); + PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Training fail on this port + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingFail ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_TRAINING_FAIL, 0); + PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Links training success + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieTrainingSuccess ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_TRAINING_SUCCESS, 0); + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Links in compliance + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingCompliance ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE, 0); + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCie EP not present + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingNotPresent ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if ((CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugServer)) { + } else { + PcieRegisterWriteField ( + PcieConfigGetParentWrapper (CurrentEngine), + WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId), + D0F0xE4_WRAP_0800_HoldTraining_OFFSET, + D0F0xE4_WRAP_0800_HoldTraining_WIDTH, + 1, + FALSE, + Pcie + ); + } + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Final state. Port training completed. + * + * Initialization status recorded in PCIe_ENGINE_CONFIG.InitStatus + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingCompleted ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Training state handling + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Indicate if engine in non final state + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieTrainingPortCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + BOOLEAN *TrainingComplete; + TrainingComplete = (BOOLEAN *) Buffer; + if (Engine->Type.Port.State < Pcie->TrainingExitState) { + *TrainingComplete = FALSE; + } else { + return; + } + switch (Engine->Type.Port.State) { + case LinkStateResetAssert: + PcieTrainingAssertReset (Engine, Pcie); + break; + case LinkStateResetDuration: + PcieTrainingCheckResetDuration (Engine, Pcie); + break; + case LinkStateResetExit: + PcieTrainingDeassertReset (Engine, Pcie); + break; + case LinkTrainingResetTimeout: + PcieTrainingCheckResetTimeout (Engine, Pcie); + break; + case LinkStateReleaseTraining: + PcieTrainingRelease (Engine, Pcie); + break; + case LinkStateDetectPresence: + PcieTrainingDetectPresence (Engine, Pcie); + break; + case LinkStateDetecting: + PcieTrainingDetectLinkState (Engine, Pcie); + break; + case LinkStateBrokenLane: + PcieTrainingBrokenLine (Engine, Pcie); + break; + case LinkStateGen2Fail: + PcieTrainingGen2Fail (Engine, Pcie); + break; + case LinkStateL0: + PcieCheckLinkL0 (Engine, Pcie); + break; + case LinkStateVcoNegotiation: + PcieTrainingCheckVcoNegotiation (Engine, Pcie); + break; + case LinkStateRetrain: + PcieTrainingRetrainLink (Engine, Pcie); + break; + case LinkStateTrainingFail: + PcieTrainingFail (Engine, Pcie); + break; + case LinkStateGfxWorkaround: + PcieTrainingGfxWorkaround (Engine, Pcie); + break; + case LinkStateTrainingSuccess: + PcieTrainingSuccess (Engine, Pcie); + break; + case LinkStateCompliance: + PcieTrainingCompliance (Engine, Pcie); + break; + case LinkStateDeviceNotPresent: + PcieTrainingNotPresent (Engine, Pcie); + break; + case LinkStateTrainingCompleted: + PcieTrainingCompleted (Engine, Pcie); + break; + default: + break; + } + +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Main link training procedure + * + * Port end up in three possible state LinkStateTrainingNotPresent/LinkStateCompliance/ + * LinkStateTrainingSuccess + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +PcieTraining ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + BOOLEAN TrainingComplete; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Enter\n"); + do { + TrainingComplete = TRUE; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieTrainingPortCallback, + &TrainingComplete, + Pcie + ); + } while (!TrainingComplete); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Exit [%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump port state on state transition + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +GNB_DEBUG_CODE ( +VOID +STATIC +PcieTrainingDebugDumpPortState ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + IDS_HDT_CONSOLE (PCIE_MISC, " Port %d:%d:%d State [%s] Time Stamp [%d]\n", + CurrentEngine->Type.Port.Address.Address.Bus, + CurrentEngine->Type.Port.Address.Address.Device, + CurrentEngine->Type.Port.Address.Address.Function, + (CurrentEngine->Type.Port.State == LinkStateTrainingFail) ? "LinkStateTrainingFail " : ( + (CurrentEngine->Type.Port.State == LinkStateTrainingSuccess) ? "LinkStateTrainingSuccess " : ( + (CurrentEngine->Type.Port.State == LinkStateCompliance) ? "LinkStateCompliance " : ( + (CurrentEngine->Type.Port.State == LinkStateDeviceNotPresent) ? "LinkStateDeviceNotPresent" : ( + (CurrentEngine->Type.Port.State == LinkStateResetAssert) ? "LinkStateResetAssert " : ( + (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetDuration " : ( + (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetExit " : ( + (CurrentEngine->Type.Port.State == LinkTrainingResetTimeout) ? "LinkTrainingResetTimeout " : ( + (CurrentEngine->Type.Port.State == LinkStateReleaseTraining) ? "LinkStateReleaseTraining " : ( + (CurrentEngine->Type.Port.State == LinkStateDetectPresence) ? "LinkStateDetectPresence " : ( + (CurrentEngine->Type.Port.State == LinkStateDetecting) ? "LinkStateDetecting " : ( + (CurrentEngine->Type.Port.State == LinkStateBrokenLane) ? "LinkStateBrokenLane " : ( + (CurrentEngine->Type.Port.State == LinkStateGen2Fail) ? "LinkStateGen2Fail " : ( + (CurrentEngine->Type.Port.State == LinkStateL0) ? "LinkStateL0 " : ( + (CurrentEngine->Type.Port.State == LinkStateVcoNegotiation) ? "LinkStateVcoNegotiation " : ( + (CurrentEngine->Type.Port.State == LinkStateGfxWorkaround) ? "LinkStateGfxWorkaround " : ( + (CurrentEngine->Type.Port.State == LinkStateTrainingCompleted) ? "LinkStateTrainingComplete" : ( + (CurrentEngine->Type.Port.State == LinkStateRetrain) ? "LinkStateRetrain " : ( + (CurrentEngine->Type.Port.State == LinkStateResetExit) ? "LinkStateResetExit " : "Unknown")))))))))))))))))), + CurrentEngine->Type.Port.TimeStamp + ); +} +) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h new file mode 100644 index 0000000000..c84b522d7c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h @@ -0,0 +1,90 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link training + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIETRAINING_H_ +#define _PCIETRAINING_H_ + + +AGESA_STATUS +PcieTraining ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTrainingSetPortState ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIE_LINK_TRAINING_STATE State, + IN BOOLEAN UpdateTimeStamp, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c new file mode 100644 index 0000000000..858dcbe4e7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c @@ -0,0 +1,402 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various workarounds + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbRegistersLN.h" +#include "PcieWorkarounds.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieConfigureBridgeResources ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieFreeBridgeResources ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +GFX_WORKAROUND_STATUS +PcieDeskewWorkaround ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +GFX_WORKAROUND_STATUS +PcieNvWorkaround ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieProgramCpuMmio ( + OUT UINT32 *SaveValues, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieRestoreCpuMmio ( + IN UINT32 *RestoreValues, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +PcieIsDeskewCardDetected ( + IN UINT16 DeviceId + ); + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * ATI RV370/RV380 card workaround + * + * + * + * @param[in] Port PCI addreses of the port + * @param[in] StdHeader Standard configuration header + * @retval GFX_WORKAROUND_STATUS Return the GFX Card Workaround status + */ +GFX_WORKAROUND_STATUS +PcieGfxCardWorkaround ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GFX_WORKAROUND_STATUS Status; + UINT16 DeviceId; + UINT16 VendorId; + UINT8 DevClassCode; + UINT32 SaveValueData[2]; + PCI_ADDR Ep; + + Status = GFX_WORKAROUND_SUCCESS; + + Ep.AddressValue = MAKE_SBDFO (0, Port.Address.Bus + Port.Address.Device, 0, 0, 0); + if (PcieConfigureBridgeResources (Port, StdHeader) == AGESA_SUCCESS) { + GnbLibPciRead (Ep.AddressValue | 0x00, AccessWidth16, &DeviceId, StdHeader); + Status = GFX_WORKAROUND_DEVICE_NOT_READY; + if (DeviceId != 0xffff) { + GnbLibPciRead (Ep.AddressValue | 0x02, AccessWidth16, &VendorId, StdHeader); + if (VendorId != 0xffff) { + GnbLibPciRead (Ep.AddressValue | 0x0B, AccessWidth8, &DevClassCode, StdHeader); + Status = GFX_WORKAROUND_SUCCESS; + if (DevClassCode == 3) { + PcieProgramCpuMmio (SaveValueData, StdHeader); + if (VendorId == 0x1002 && PcieIsDeskewCardDetected (DeviceId)) { + Status = PcieDeskewWorkaround (Ep, StdHeader); + } else if (VendorId == 0x10DE) { + Status = PcieNvWorkaround (Ep, StdHeader); + } + PcieRestoreCpuMmio (SaveValueData, StdHeader); + } + } + } + PcieFreeBridgeResources (Port, StdHeader); + } + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * RV370/RV380 Deskew workaround + * + * + * + * @param[in] Device Pcie Address of ATI RV370/RV380 card. + * @param[in] StdHeader Standard configuration header + */ +GFX_WORKAROUND_STATUS +PcieDeskewWorkaround ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN MmioBase; + UINT16 MmioData1; + UINT32 MmioData2; + + MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; + if (MmioBase == 0) { + return GFX_WORKAROUND_SUCCESS; + } + GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , (UINT32)~BIT1, (UINT32)BIT1, StdHeader); + GnbLibMemRMW (MmioBase + 0x120, AccessWidth16, 0, 0xb700, StdHeader); + GnbLibMemRead (MmioBase + 0x120, AccessWidth16, &MmioData1, StdHeader); + if (MmioData1 == 0xb700) { + GnbLibMemRMW (MmioBase + 0x124, AccessWidth32, 0, 0x13, StdHeader); + GnbLibMemRead (MmioBase + 0x124, AccessWidth32, &MmioData2, StdHeader); + if (MmioData2 == 0x13) { + GnbLibMemRead (MmioBase + 0x12C, AccessWidth32, &MmioData2, StdHeader); + if (MmioData2 & BIT8) { + return GFX_WORKAROUND_RESET_DEVICE; + } + } + } + GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, (UINT32)~BIT1, 0x0, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, StdHeader); + + return GFX_WORKAROUND_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * NV43 card workaround (lost SSID) + * + * + * + * @param[in] Device Pcie Address of NV43 card. + * @param[in] StdHeader Standard configuration header + */ +GFX_WORKAROUND_STATUS +PcieNvWorkaround ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 DeviceSSID; + UINTN MmioBase; + UINT32 MmioData3; + + MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; + if (MmioBase == 0) { + return GFX_WORKAROUND_SUCCESS; + } + GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, ((UINT32)MmioBase) | 1, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x2, StdHeader); + GnbLibPciRead (Device.AddressValue | 0x2c, AccessWidth32, &DeviceSSID, StdHeader); + GnbLibMemRead (MmioBase + 0x54, AccessWidth32, &MmioData3, StdHeader); + if (DeviceSSID != MmioData3) { + GnbLibPciRMW (Device.AddressValue | 0x40, AccessWidth32, 0x0, MmioData3, StdHeader); + } + GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, 0x0, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x0, StdHeader); + return GFX_WORKAROUND_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Allocate temporary resources for Pcie P2P bridge + * + * + * + * @param[in] Port Pci Address of Port to initialize. + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +PcieConfigureBridgeResources ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + UINT32 MmioBase; + + MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; + if (MmioBase == 0) { + return AGESA_WARNING; + } + Value = Port.Address.Bus + ((Port.Address.Bus + Port.Address.Device) << 8) + ((Port.Address.Bus + Port.Address.Device) << 16); + GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader); + Value = MmioBase + (MmioBase >> 16); + GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader); + Value = 0x000fff0; + GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader); + Value = 0x2; + GnbLibPciWrite (Port.AddressValue | 0x4 , AccessWidth8, &Value, StdHeader); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Free temporary resources for Pcie P2P bridge + * + * + * + * @param[in] Port Pci Address of Port to clear resource allocation. + * @param[in] StdHeader Standard configuration header + */ +VOID +PcieFreeBridgeResources ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + + Value = 0; + GnbLibPciWrite (Port.AddressValue | 0x4 , AccessWidth8, &Value, StdHeader); + GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader); + GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader); + GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader); + +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Save CPU MMIO register + * + * + * + * @param[out] UINT32 SaveValues + * @param[in] StdHeader Standard configuration header + * + */ +VOID +PcieProgramCpuMmio ( + OUT UINT32 *SaveValues, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + //Save CPU MMIO Register + GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, SaveValues, StdHeader); + GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, SaveValues + 1, StdHeader); + + //Write Temp Pcie MMIO to CPU + GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, (UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8, StdHeader); + GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, ((UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8) | 0x3, StdHeader); + +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Restore CPU MMIO register + * + * + * + * @param[in] PCIe_PLATFORM_CONFIG Pcie + * @param[in] StdHeader Standard configuration header + */ +VOID +PcieRestoreCpuMmio ( + IN UINT32 *RestoreValues, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + //Restore CPU MMIO Register + GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, *RestoreValues, StdHeader); + GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, *(RestoreValues + 1), StdHeader); + +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if card required test for deskew workaround + * + * + * + * @param[in] DeviceId Device ID + */ + +BOOLEAN +PcieIsDeskewCardDetected ( + IN UINT16 DeviceId + ) +{ + if ((DeviceId >= 0x3150 && DeviceId <= 0x3152) || (DeviceId == 0x3154) || + (DeviceId == 0x3E50) || (DeviceId == 0x3E54) || + ((DeviceId & 0xfff8) == 0x5460) || ((DeviceId & 0xfff8) == 0x5B60)) { + return TRUE; + } + return FALSE; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h new file mode 100644 index 0000000000..3f67635c20 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h @@ -0,0 +1,82 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various workarounds + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEWORKAROUNDS_H_ +#define _PCIEWORKAROUNDS_H_ + +GFX_WORKAROUND_STATUS +PcieGfxCardWorkaround ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c new file mode 100644 index 0000000000..64f8df5576 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c @@ -0,0 +1,178 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB CNB library. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "cpuServices.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbLib.h" +#include "GnbLibPciAcc.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Host bridge PCI Address + * + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard configuration header + * @retval PCI address of GNB for a given socket/silicon. + */ + +PCI_ADDR +GnbFmGetPciAddress ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR Gnb; + Gnb.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + return Gnb; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bus range decoded by GNB + * + * Final bus allocation can not be assumed until AmdInitMid + * + * @param[in] GnbHandle GNB handle + * @param[out] StartBusNumber Beggining of the Bus Range + * @param[out] EndBusNumber End of the Bus Range + * @param[in] StdHeader Standard configuration header + * @retval Satus + */ + +AGESA_STATUS +GnbFmGetBusDecodeRange ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *StartBusNumber, + OUT UINT8 *EndBusNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *StartBusNumber = 0x0; + *EndBusNumber = 0xff; + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get link to which GNB connected to + * + * + * @param[in] GnbHandle GNB handle + * @param[out] LinkId Link to which GNB connected to + * @param[in] StdHeader Standard configuration header + * @retval Satus + */ + +AGESA_STATUS +GnbFmGetLinkId ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *LinkId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + *LinkId = 0x00; + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c new file mode 100644 index 0000000000..5a1db75fd9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c @@ -0,0 +1,146 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * SB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbIommu.h" +#include "GnbCommonLib.h" +#include "GnbIvrsLib.h" +#include "GnbSbIommuLib.h" +#include "GnbSbLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVHD entry + * + * + * @param[in] Ivhd IVHD header pointer + * @param[in] StdHeader Standard configuration header + * + */ +VOID +SbCreateIvhdEntries ( + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR Start; + PCI_ADDR End; + PCI_ADDR PciAddress; + UINT32 Value; + IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Entry\n"); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 4, 0); +// P2P alias entry + GnbLibPciRead (PciAddress.AddressValue | 0x18, AccessWidth32, &Value, StdHeader); + Start.AddressValue = MAKE_SBDFO (0, (Value >> 8) & 0xff, 0, 0, 0); + End.AddressValue = MAKE_SBDFO (0, (Value >> 16) & 0xff, 0x1f, 0x7, 0); + GnbIvhdAddDeviceAliasRangeEntry (Start, End, PciAddress, 0, Ivhd, StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0); +// HPET + GnbIvhdAddSpecialDeviceEntry (IvhdSpecialDeviceHpet, PciAddress, 0, 0, Ivhd, StdHeader); +// APIC + GnbIvhdAddSpecialDeviceEntry ( + IvhdSpecialDeviceIoapic, + PciAddress, + GnbLiGetIoapicId (SbGetSbIoApicBaseAddress (StdHeader), StdHeader), + 0xD7, + Ivhd, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Exit\n"); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h new file mode 100644 index 0000000000..264c48e74f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h @@ -0,0 +1,82 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * SB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBSBIOMMULIB_H_ +#define _GNBSBIOMMULIB_H_ + + +VOID +SbCreateIvhdEntries ( + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c new file mode 100644 index 0000000000..15da5f28ca --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c @@ -0,0 +1,159 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * SB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbCommonLib.h" +#include "GnbSbLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +/*----------------------------------------------------------------------------------------*/ +/** + *Get SB IOAPIC Base Address + * + * + * @param[in] StdHeader Standard configuration header + * @retval APIC base address + */ +UINT32 +SbGetSbIoApicBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ApicBaseAddress; + GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x34, 4, &ApicBaseAddress, StdHeader); + return ApicBaseAddress & 0xfffffff8; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Get SB MMIO Base Address + * + * + * @param[in] StdHeader Standard configuration header + * @retval MMIO base address + */ +UINT32 +SbGetSbMmioBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 MmioBaseAddress; + GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x24, 4, &MmioBaseAddress, StdHeader); + return MmioBaseAddress & 0xfffffffc; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Alink config address + * + * @param[in] StdHeader Standard configuration header + * @retval Alink base address + */ +/*----------------------------------------------------------------------------------------*/ + +UINT16 +SbGetAlinkIoAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + UINT16 AlinkPortAddress; + GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0xE0, 2, &AlinkPortAddress, StdHeader); + return AlinkPortAddress; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h new file mode 100644 index 0000000000..3ba80d462e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h @@ -0,0 +1,105 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * SB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBSBLIB_H_ +#define _GNBSBLIB_H_ + +#include "GnbPcie.h" + +UINT32 +SbGetSbIoApicBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +SbGetSbMmioBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT16 +SbGetAlinkIoAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +SbPcieInitAspm ( + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +SbPcieLinkAspmControl ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c new file mode 100644 index 0000000000..a592041fe5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c @@ -0,0 +1,169 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB-SB link procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbSbLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable/Disable ASPM on GNB-SB link + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +AGESA_STATUS +SbPcieLinkAspmControl ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + PCIE_ASPM_TYPE Aspm; + + Aspm = Engine->Type.Port.PortData.LinkAspm; + + Status = SbPcieInitAspm (Aspm, GnbLibGetHeader (Pcie)); + if (Status != AGESA_SUCCESS) { + return AGESA_UNSUPPORTED; + } + + PcieAspmEnableOnFunction (Engine->Type.Port.Address, Aspm, GnbLibGetHeader (Pcie)); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init SB ASPM. + * Enable ASPM states on SB + * + * + * @param[in] Aspm ASPM bitmap. + * @param[in] StdHeader Standard configuration header + */ +/*----------------------------------------------------------------------------------------*/ + +AGESA_STATUS +SbPcieInitAspm ( + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 AlinkPort; + + AlinkPort = SbGetAlinkIoAddress (StdHeader); + ASSERT (AlinkPort != 0); + if (AlinkPort == 0) { + return AGESA_UNSUPPORTED; + } + GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x40000038, StdHeader); + GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0x0, 0xA0, StdHeader); + GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x4000003c, StdHeader); + GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffff00ff, 0x6900, StdHeader); + GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x80000068, StdHeader); + GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xfffffffc, Aspm, StdHeader); + return AGESA_SUCCESS; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c new file mode 100644 index 0000000000..bb0a47ca40 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c @@ -0,0 +1,155 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Interface to initialize Graphics Controller at mid POST + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbCommonLib.h" +#include "GnbGfxFamServices.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GfxInitSview ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Init SVIEW configuration + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxInitSview ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GFX_PLATFORM_CONFIG *Gfx; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = GfxLocateConfigData (StdHeader, &Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + if (GfxLibIsControllerPresent (StdHeader)) { + if (!GfxFmIsVbiosPosted (Gfx)) { + GFX_VBIOS_IMAGE_INFO VbiosImageInfo; + LibAmdMemCopy (&VbiosImageInfo.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + VbiosImageInfo.ImagePtr = NULL; + VbiosImageInfo.GfxPciAddress = Gfx->GfxPciAddress; + VbiosImageInfo.Flags = GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST; + GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xff, BIT1 | BIT2 | BIT0, StdHeader); + Status = AgesaGetVbiosImage (0, &VbiosImageInfo); + if (Status == AGESA_SUCCESS && VbiosImageInfo.ImagePtr != NULL) { + GfxLibCopyMemToFb (VbiosImageInfo.ImagePtr, 0, (*((UINT8*) VbiosImageInfo.ImagePtr + 2)) << 9, Gfx); + } else { + GfxFmDisableController (StdHeader); + AgesaStatus = AGESA_ERROR; + } + GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xf8, BIT1 | BIT2, StdHeader); + } + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c new file mode 100644 index 0000000000..8d7d5dbb02 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c @@ -0,0 +1,384 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbLib.h" +#include "GnbTimerLib.h" +#include "GnbFamServices.h" +#include "GnbTable.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +GnbProcessTableRegisterRmw ( + IN GNB_HANDLE *GnbHandle, + IN GNB_REGISTER_SERVICE *GnbRegisterAccessProtocol, + IN GNB_RMW_BLOCK *Data, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Process table + * + * @param[in] GnbHandle Gnb handle + * @param[in] Table Table pointer + * @param[in] Property Property + * @param[in] Flags Flags + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +GnbProcessTable ( + IN GNB_HANDLE *GnbHandle, + IN GNB_TABLE *Table, + IN UINT32 Property, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *EntryPointer; + UINT64 Data; + UINT64 Temp; + UINT64 Mask; + UINT32 WriteAccFlags; + GNB_REGISTER_SERVICE *GnbRegisterAccessProtocol; + CPU_LOGICAL_ID LogicalId; + AGESA_STATUS Status; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Enter\n"); + IDS_HDT_CONSOLE (GNB_TRACE, " Property - 0x%08x\n", Property); + + GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader); + EntryPointer = (UINT8 *) Table; + WriteAccFlags = 0; + if ((Flags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) { + WriteAccFlags |= GNB_REG_ACC_FLAG_S3SAVE; + } + + Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (VOID **)&GnbRegisterAccessProtocol, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + + while (*EntryPointer != GnbEntryTerminate) { + Data = 0; + Temp = 0; + switch (*EntryPointer) { + case GnbEntryWr: + GnbRegisterAccessProtocol->Write ( + GnbHandle, + ((GNB_TABLE_ENTRY_WR*) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_WR*) EntryPointer)->Address, + &((GNB_TABLE_ENTRY_WR*) EntryPointer)->Value, + WriteAccFlags, + StdHeader + ); + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_WR); + break; + case GnbEntryPropertyWr: + if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Property) != 0) { + GnbRegisterAccessProtocol->Write ( + GnbHandle, + ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Address, + &((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Value, + WriteAccFlags, + StdHeader + ); + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_WR); + break; + case GnbEntryFullWr: + if ((Property & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Property) != 0) { + if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Revision) != 0) { + GnbRegisterAccessProtocol->Write ( + GnbHandle, + ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Address, + &((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Value, + WriteAccFlags, + StdHeader + ); + } + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_WR); + break; + case GnbEntryRmw: + GnbProcessTableRegisterRmw ( + GnbHandle, + GnbRegisterAccessProtocol, + &((GNB_TABLE_ENTRY_RMW *) EntryPointer)->Data, + WriteAccFlags, + StdHeader + ); + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_RMW); + break; + case GnbEntryPropertyRmw: + if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Property) != 0) { + GnbProcessTableRegisterRmw ( + GnbHandle, + GnbRegisterAccessProtocol, + &((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Data, + WriteAccFlags, + StdHeader + ); + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_RMW); + break; + case GnbEntryRevRmw: + if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_REV_RMW *) EntryPointer)->Revision) != 0) { + GnbProcessTableRegisterRmw ( + GnbHandle, + GnbRegisterAccessProtocol, + &((GNB_TABLE_ENTRY_REV_RMW *) EntryPointer)->Data, + WriteAccFlags, + StdHeader + ); + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_REV_RMW); + break; + case GnbEntryFullRmw: + if ((Property & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Property) != 0) { + if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Revision) != 0) { + GnbProcessTableRegisterRmw ( + GnbHandle, + GnbRegisterAccessProtocol, + &((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Data, + WriteAccFlags, + StdHeader + ); + } + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_RMW); + break; + case GnbEntryPoll: + do { + GnbRegisterAccessProtocol->Read ( + GnbHandle, + ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->Address, + &Data, + 0, + StdHeader + ); + } while ((Data & ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->CompareValue); + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_POLL); + break; + case GnbEntryPropertyPoll: + if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Property) != 0) { + do { + GnbRegisterAccessProtocol->Read ( + GnbHandle, + ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Address, + &Data, + 0, + StdHeader + ); + } while ((Data & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->CompareValue); + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_POLL); + break; + case GnbEntryFullPoll: + if ((Property & ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->Property) != 0) { + if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Revision) != 0) { + do { + GnbRegisterAccessProtocol->Read ( + GnbHandle, + ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->Address, + &Data, + 0, + StdHeader + ); + } while ((Data & ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->CompareValue); + } + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_POLL); + break; + case GnbEntryCopy: + GnbRegisterAccessProtocol->Read ( + GnbHandle, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcRegisterSpaceType, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcAddress, + &Data, + 0, + StdHeader + ); + Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldWidth) - 1; + Data = (Data >> ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldOffset) & Mask; + GnbRegisterAccessProtocol->Read ( + GnbHandle, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress, + &Temp, + 0, + StdHeader + ); + Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldWidth) - 1; + Temp = Temp & ( ~ (Mask << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset)); + Temp = Temp | ((Data & Mask) << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset); + GnbRegisterAccessProtocol->Write ( + GnbHandle, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress, + &Temp, + WriteAccFlags, + StdHeader + ); + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_COPY); + break; + case GnbEntryStall: + if ((WriteAccFlags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) { + GnbLibStallS3Save (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader); + } else { + GnbLibStall (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader); + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_STALL); + break; + default: + ASSERT (FALSE); + IDS_HDT_CONSOLE (NB_MISC, " ERROR!!! Regiter table parse\n"); + return AGESA_ERROR; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Supporting function for register read modify write + * + * @param[in] GnbHandle Gnb handle + * @param[in] GnbRegisterAccessProtocol Register access protocol + * @param[in] Data Data pointer + * @param[in] Flags Flags + * @param[in] StdHeader Standard configuration header + */ + +VOID +STATIC +GnbProcessTableRegisterRmw ( + IN GNB_HANDLE *GnbHandle, + IN GNB_REGISTER_SERVICE *GnbRegisterAccessProtocol, + IN GNB_RMW_BLOCK *Data, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 Value; + Value = 0; + GnbRegisterAccessProtocol->Read ( + GnbHandle, + Data->RegisterSpaceType, + Data->Address, + &Value, + 0, + StdHeader + ); + Value = (Value & (~ (UINT64) Data->AndMask)) | Data->OrMask; + GnbRegisterAccessProtocol->Write ( + GnbHandle, + Data->RegisterSpaceType, + Data->Address, + &Value, + Flags, + StdHeader + ); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.h new file mode 100644 index 0000000000..02b0f52b46 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.h @@ -0,0 +1,265 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBTABLE_H_ +#define _GNBTABLE_H_ + +#include "GnbPcie.h" + +#pragma pack (push, 1) + +#define GNB_TABLE_FLAGS_FORCE_S3_SAVE 0x00000001ul + +typedef UINT8 GNB_TABLE; + +#define __DATA(x) x + +#define _DATA32(Data) (__DATA(Data)) & 0xFF, ((__DATA(Data)) >> 8) & 0xFF, ((__DATA(Data)) >> 16) & 0xFF, ((__DATA(Data)) >> 24) & 0xFF +#define _DATA64(Data) _DATA32(Data & 0xfffffffful) , _DATA32(Data >> 32) + +/// Entry type +typedef enum { + GnbEntryWr, ///< Write register + GnbEntryPropertyWr, ///< Write register check property + GnbEntryFullWr, ///< Write Rgister check revision and property + GnbEntryRmw, ///< Read Modify Write register + GnbEntryPropertyRmw, ///< Read Modify Write register check property + GnbEntryRevRmw, ///< Read Modify Write register check revision + GnbEntryFullRmw, ///< Read Modify Write register check revision and property + GnbEntryPoll, ///< Poll register + GnbEntryPropertyPoll, ///< Poll register check property + GnbEntryFullPoll, ///< Poll register check property + GnbEntryCopy, ///< Copy field from one register to another + GnbEntryStall, ///< Copy field from one register to another + GnbEntryTerminate = 0xFF ///< Terminate table +} GNB_TABLE_ENTRY_TYPE; + +#define GNB_ENTRY_WR(RegisterSpaceType, Address, Value) \ + GnbEntryWr, RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) + +/// Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 Value; ///< Value +} GNB_TABLE_ENTRY_WR; + +#define GNB_ENTRY_PROPERTY_WR(Property, RegisterSpaceType, Address, Value) \ + GnbEntryPropertyWr, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) + +/// Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 Value; ///< Value +} GNB_TABLE_ENTRY_PROPERTY_WR; + + +#define GNB_ENTRY_RMW(RegisterSpaceType, Address, AndMask, OrMask) \ + GnbEntryRmw, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) + +///Read Modify Write data Block +typedef struct { + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 AndMask; ///< And Mask + UINT32 OrMask; ///< Or Mask +} GNB_RMW_BLOCK; + +/// Read Modify Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + GNB_RMW_BLOCK Data; ///< Data +} GNB_TABLE_ENTRY_RMW; + +#define GNB_ENTRY_FULL_WR(Property, Revision, RegisterSpaceType, Address, Value) \ + GnbEntryFullWr, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) + +/// Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + UINT64 Revision; ///< Revision + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 Value; ///< Value +} GNB_TABLE_ENTRY_FULL_WR; + + +#define GNB_ENTRY_PROPERTY_RMW(Property, RegisterSpaceType, Address, AndMask, OrMask) \ + GnbEntryPropertyRmw, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) + +/// Read Modify Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + GNB_RMW_BLOCK Data; ///< Data +} GNB_TABLE_ENTRY_PROPERTY_RMW; + +#define GNB_ENTRY_REV_RMW(Rev, RegisterSpaceType, Address, AndMask, OrMask) \ + GnbEntryRevRmw, _DATA64 (Rev), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) + +/// Read Modify Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT64 Revision; ///< revision + GNB_RMW_BLOCK Data; ///< Data +} GNB_TABLE_ENTRY_REV_RMW; + +#define GNB_ENTRY_FULL_RMW(Property, Revision, RegisterSpaceType, Address, AndMask, OrMask) \ + GnbEntryFullRmw, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) + +/// Read Modify Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + UINT64 Revision; ///< Revision + GNB_RMW_BLOCK Data; ///< Data +} GNB_TABLE_ENTRY_FULL_RMW; + +#define GNB_ENTRY_POLL(RegisterSpaceType, Address, AndMask, CompareValue) \ + GnbEntryPoll, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue) +/// Poll register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 AndMask; ///< End mask + UINT32 CompareValue; ///< Compare value +} GNB_TABLE_ENTRY_POLL; + +#define GNB_ENTRY_PROPERTY_POLL(Property, RegisterSpaceType, Address, AndMask, CompareValue) \ + GnbEntryPropertyPoll, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue) +/// Poll register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 AndMask; ///< End mask + UINT32 CompareValue; ///< Compare value +} GNB_TABLE_ENTRY_PROPERTY_POLL; + +#define GNB_ENTRY_FULL_POLL(Property, Revision, RegisterSpaceType, Address, AndMask, CompareValue) \ + GnbEntryFullPoll, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue) +/// Poll register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + UINT64 Revision; ///< Revision + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 AndMask; ///< End mask + UINT32 CompareValue; ///< Compare value +} GNB_TABLE_ENTRY_FULL_POLL; + +#define GNB_ENTRY_COPY(DestRegSpaceType, DestAddress, DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, SrcAddress, SrcFieldOffset, SrcFieldWidth) \ + GnbEntryCopy, DestRegSpaceType, _DATA32 (DestAddress), DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, _DATA32 (SrcAddress), SrcFieldOffset, SrcFieldWidth + +/// Copy regster entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT8 DestRegisterSpaceType; ///< Register space + UINT32 DestAddress; ///< Register address + UINT8 DestFieldOffset; ///< Field Offset + UINT8 DestFieldWidth; ///< Field Width + UINT8 SrcRegisterSpaceType; ///< Register space + UINT32 SrcAddress; ///< Register address + UINT8 SrcFieldOffset; ///< Field Offset + UINT8 SrcFieldWidth; ///< Field Width +} GNB_TABLE_ENTRY_COPY; + +#define GNB_ENTRY_STALL(Microsecond) \ + GnbEntryStall, _DATA32 (Microsecond) + +/// Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Microsecond; ///< Value +} GNB_TABLE_ENTRY_STALL; + +#define GNB_ENTRY_TERMINATE GnbEntryTerminate + +AGESA_STATUS +GnbProcessTable ( + IN GNB_HANDLE *GnbHandle, + IN GNB_TABLE *Table, + IN UINT32 Property, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#pragma pack (pop) + +#endif -- cgit v1.2.3