From c2f2bd0a6d00a7f8df4005f148f67373db6d26d6 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Wed, 6 Mar 2013 22:13:42 +0400 Subject: AGESA: Fix CR0_PE bit define AGESA code has wrong definition of CR0_PE bit (1 instead of 0). PE [Protected Mode Enable] is 0 bit in CR0 register (If PE=1, system is in protected mode, else system is in real mode) Bit 1 is MP [Monitor co-processor] (Controls interaction of WAIT/FWAIT instructions with TS flag in CR0) System uses CR0_PE define, but I didn't expect any consequences because of this bug. Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1 Signed-off-by: Konstantin Aladyshev Reviewed-on: http://review.coreboot.org/2591 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/vendorcode/amd/agesa/f15/gcccar.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/vendorcode/amd/agesa/f15') diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index 3627da6df3..b20c77e575 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -115,7 +115,7 @@ CU_CFG3 = 0x0C001102B /* Combined Unit Configuration COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ -CR0_PE = 1 # Protection Enable +CR0_PE = 0 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable -- cgit v1.2.3