From b97dc871d99c91270bb80be6ce6d1937e5169b7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 18 Apr 2016 12:09:00 +0300 Subject: AGESA: Drop unused assembly files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I0a452b6234b02222be82ca8694868e1ffbfceaee Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/14396 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- .../f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm | 113 ----- .../f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm | 127 ------ src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm | 345 -------------- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm | 157 ------- src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm | 497 --------------------- .../amd/agesa/f14/Proc/Recovery/Mem/mru.asm | 187 -------- 6 files changed, 1426 deletions(-) delete mode 100644 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm delete mode 100644 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm delete mode 100644 src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm delete mode 100644 src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm delete mode 100644 src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm delete mode 100644 src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm (limited to 'src/vendorcode/amd/agesa/f14/Proc') diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm deleted file mode 100644 index 4112659226..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm +++ /dev/null @@ -1,113 +0,0 @@ -;/** -; * @file -; * -; * AGESA Family 10h Revision D support routines. -; * -; * @xrefitem bom "File Content Label" "Release Content" -; * @e project: AGESA -; * @e sub-project: CPU/F10 -; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $ -; */ -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - - .XLIST - .LIST - - .586P - -;=============================================== -;=============================================== -;== -;== M E M O R Y P R E S E N T S E G M E N T -;== -;=============================================== -;=============================================== - .MODEL flat - .CODE - -;====================================================================== -; F10RevDProbeFilterCritical: Performs critical sequence for probe -; filter initialization. -; -; In: -; PciAddress Full PCI address of the node to init -; PciRegister Current value of F3x1D4 -; -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -F10RevDProbeFilterCritical PROC NEAR C PUBLIC USES EAX ECX EDX, PciAddress:DWORD, PciRegister:DWORD - - mov ecx, 0C001001Fh - rdmsr - push eax - push ecx - push edx - or dh, 40h - wrmsr - - mov eax, 810003D4h - - mov ecx, PciRegister - mov edx, PciAddress - shr edx, 4 - and dh, 0F8h - or ah, dh - - or cl, 2 - db 0Fh, 0AEh, 0F0h ; MFENCE - - mov dx, 0CF8h ; Set Reg Config Space - db 0Fh, 0AEh, 0F0h ; MFENCE - - out dx, eax - db 0Fh, 0AEh, 0F0h ; MFENCE - - mov dl, 0FCh ; Set DX to Pci Config Data - mov eax, ecx ;Set config Reg data - db 0Fh, 0AEh, 0F0h ; MFENCE - - out dx, eax ; move data to return position - db 0Fh, 0AEh, 0F0h ; MFENCE - - pop edx - pop ecx - pop eax - wrmsr - ret - -F10RevDProbeFilterCritical ENDP - -END diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm deleted file mode 100644 index 4353190451..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm +++ /dev/null @@ -1,127 +0,0 @@ -;/** -; * @file -; * -; * AGESA Family 10h Revision D support routines. -; * -; * @xrefitem bom "File Content Label" "Release Content" -; * @e project: AGESA -; * @e sub-project: CPU/F10 -; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $ -; */ -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - - .XLIST - .LIST - -;=============================================== -;=============================================== -;== -;== M E M O R Y P R E S E N T S E G M E N T -;== -;=============================================== -;=============================================== - .CODE - -;====================================================================== -; F10RevDProbeFilterCritical: Performs critical sequence for probe -; filter initialization. -; -; In: -; PciAddress Full PCI address of the node to init -; PciRegister Current value of F3x1D4 -; -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -PUBLIC F10RevDProbeFilterCritical -F10RevDProbeFilterCritical PROC - - push rax - push rcx - push rdx - push rsi - push rdi - - mov esi, ecx - mov edi, edx - - mov ecx, 0C001001Fh - rdmsr - push rax - push rcx - push rdx - or dh, 40h - wrmsr - - mov eax, 810003D4h - - mov ecx, edi - mov edx, esi - - shr edx, 4 - and dh, 0F8h - or ah, dh - - or cl, 2 - mfence - - mov dx, 0CF8h ; Set Reg Config Space - mfence - - out dx, eax - mfence - - mov dl, 0FCh ; Set DX to Pci Config Data - mov eax, ecx ;Set config Reg data - mfence - - out dx, eax ; move data to return position - mfence - - pop rdx - pop rcx - pop rax - wrmsr - - pop rdi - pop rsi - pop rdx - pop rcx - pop rax - ret - -F10RevDProbeFilterCritical ENDP - -END diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm deleted file mode 100644 index de5201d1b1..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm +++ /dev/null @@ -1,345 +0,0 @@ -;/** -; * @file -; * -; * Agesa pre-memory miscellaneous support, including ap halt loop. -; * -; * @xrefitem bom "File Content Label" "Release Content" -; * @e project: AGESA -; * @e sub-project: CPU -; * @e \$Revision: 35270 $ @e \$Date: 2010-07-20 00:02:41 +0800 (Tue, 20 Jul 2010) $ -; */ -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - - .XLIST - INCLUDE agesa.inc - INCLUDE cpcarmac.inc - .LIST - - .586P - -;=============================================== -;=============================================== -;== -;== M E M O R Y A B S E N T S E G M E N T -;== -;=============================================== -;=============================================== - .MODEL flat - .CODE -;====================================================================== -; ExecuteFinalHltInstruction: Disables the stack and performs -; a hlt instruction on an AP. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; eax, ebx, ecx, edx, esp -; -;====================================================================== -PUBLIC ExecuteFinalHltInstruction -ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR - - mov esi, StandardHeader ; The code must reference all parameters to avoid a build warning - mov esi, HaltFlags - mov edi, ApMtrrSettingList - ; Do these special steps in case if the core is part of a compute unit - ; Note: The following bits are family specific flags, that gets set during build time, - ; and indicates things like "family cache control methodology", etc. - ; esi bit0 = 0 -> not a Primary core - ; esi bit0 = 1 -> Primary core - ; esi bit1 = 0 -> Cache disable - ; esi bit1 = 1 -> Cache enable - .if (esi & 2h) - ; Set CombineCr0Cd bit - mov ecx, CU_CFG3 - _RDMSR - bts edx, (COMBINE_CR0_CD - 32) - _WRMSR - ; Clear the CR0.CD bit - mov eax, CR0 ; Make sure cache is enabled for all APs - btr eax, CR0_CD - btr eax, CR0_NW - mov CR0, eax ; Write back to CR0 - .else - mov eax, CR0 ; Make sure cache is disabled for all APs - bts eax, CR0_CD ; Disable cache - bts eax, CR0_NW - mov CR0, eax ; Write back to CR0 - .endif - - .if (esi & 1h) - ; This core is a primary core and needs to do all the MTRRs, including shared MTRRs. - mov esi, edi ; Get ApMtrrSettingList - - ; Configure the MTRRs on the AP so - ; when it runs remote code it will execute - ; out of RAM instead of ROM. - - ; Disable MTRRs and turn on modification enable bit - mov ecx, MTRR_SYS_CFG - _RDMSR - btr eax, MTRR_VAR_DRAM_EN ; Disable - bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable - btr eax, MTRR_FIX_DRAM_EN ; Disable - bts eax, SYS_UC_LOCK_EN - _WRMSR - - ; Setup default values for Fixed-Sized MTRRs - ; Set 7FFFh-00000h as WB - mov ecx, AMD_AP_MTRR_FIX64k_00000 - mov eax, 1E1E1E1Eh - mov edx, eax - _WRMSR - - ; Set 9FFFFh-80000h also as WB - mov ecx, AMD_AP_MTRR_FIX16k_80000 - _WRMSR - - ; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO - mov ecx, AMD_AP_MTRR_FIX16k_A0000 - xor eax, eax - xor edx, edx - _WRMSR - - ; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO - xor eax, eax - xor edx, edx - mov ecx, AMD_AP_MTRR_FIX4k_C0000 - -CDLoop: - _WRMSR - inc ecx - cmp ecx, AMD_AP_MTRR_FIX4k_D8000 - jbe CDLoop - - ; Set FFFFFh-E0000h as Uncacheable Memory - mov eax, 18181818h - mov edx, eax - - mov ecx, AMD_AP_MTRR_FIX4k_E0000 - -EFLoop: - _WRMSR - inc ecx - cmp ecx, AMD_AP_MTRR_FIX4k_F8000 - jbe EFLoop - - ; If IBV provided settings for Fixed-Sized MTRRs, - ; overwrite the default settings. - .if ((esi != 0) && (esi != 0FFFFFFFFh)) - mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr - ; While we are not at the end of the list - .while (ecx != CPU_LIST_TERMINAL) - ; Ensure that the MSR address is valid for Fixed-Sized MTRRs - .if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ - (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000)) - mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData - mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData - _WRMSR - .endif - add esi, sizeof (AP_MTRR_SETTINGS) - mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr - .endw - .endif - - ; restore variable MTRR6 and MTRR7 to default states - mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6 - xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7 - xor edx, edx - .while (cl < 010h) - _WRMSR - inc cl - .endw - - ; Enable fixed-range and variable-range MTRRs - mov ecx, AMD_MTRR_DEFTYPE - _RDMSR - bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn - bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn - _WRMSR - - ; Enable Top-of-Memory setting - ; Enable use of RdMem/WrMem bits attributes - mov ecx, MTRR_SYS_CFG - _RDMSR - bts eax, MTRR_VAR_DRAM_EN ; Enable - btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable - bts eax, MTRR_FIX_DRAM_EN ; Enable - _WRMSR - - mov esi, (1 SHL FLAG_IS_PRIMARY) - .else ; end if primary core - xor esi, esi - .endif - ; Make sure not to touch any Shared MSR from this point on - - AMD_DISABLE_STACK_FAMILY_HOOK - - xor eax, eax - -@@: - cli - hlt - jmp @B ;ExecuteHltInstruction - ret -ExecuteFinalHltInstruction ENDP - -;====================================================================== -; ExecuteHltInstruction: Performs a hlt instruction. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; eax, ebx, ecx, edx, esp -; -;====================================================================== -PUBLIC ExecuteHltInstruction -ExecuteHltInstruction PROC NEAR C - cli - hlt - ret -ExecuteHltInstruction ENDP - -;====================================================================== -; NmiHandler: Simply performs an IRET. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -PUBLIC NmiHandler -NmiHandler PROC NEAR C - iretd -NmiHandler ENDP - -;====================================================================== -; GetCsSelector: Returns the current protected mode CS selector. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -PUBLIC GetCsSelector -GetCsSelector PROC NEAR C, CsSelector:PTR - push ax - push ebx - - call FarCallGetCs - mov ebx, CsSelector - mov [ebx], ax - pop ebx - pop ax - ret -GetCsSelector ENDP - -;====================================================================== -; FarCallGetCs: -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; none -; -; WARNING: This routine has a mirror routine in the PREMEM segment. -; These two routines MUST be sync'd for content. -;====================================================================== -FarCallGetCs PROC FAR PRIVATE - - mov ax, ss:[esp + 4] - retf - -FarCallGetCs ENDP - -;====================================================================== -; SetIdtr: -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; none -; -; WARNING: This routine has a mirror routine in the PREMEM segment. -; These two routines MUST be sync'd for content. -;====================================================================== -PUBLIC SetIdtr -SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR - mov ebx, IdtPtr - lidt fword ptr ss:[ebx] - ret -SetIdtr ENDP - -;====================================================================== -; ExecuteWbinvdInstruction: Performs a wbinvd instruction. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -PUBLIC ExecuteWbinvdInstruction -ExecuteWbinvdInstruction PROC NEAR C - wbinvd ; Write back the cache tag RAMs - ret -ExecuteWbinvdInstruction ENDP - -END diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm deleted file mode 100644 index f1411fa21b..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm +++ /dev/null @@ -1,157 +0,0 @@ -;/** -; * @file -; * -; * Agesa pre-memory miscellaneous support, including ap halt loop. -; * -; * @xrefitem bom "File Content Label" "Release Content" -; * @e project: AGESA -; * @e sub-project: CPU -; * @e \$Revision: 10071 $ @e \$Date: 2008-12-16 18:03:04 -0600 (Tue, 16 Dec 2008) $ -; */ -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - - text SEGMENT - - -;====================================================================== -; ExecuteFinalHltInstruction: Performs a hlt instruction. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; eax, ebx, ecx, edx, esp -; -;====================================================================== -ExecuteFinalHltInstruction PROC PUBLIC -@@: - cli - hlt - jmp @B ;ExecuteHltInstruction -ExecuteFinalHltInstruction ENDP - -;====================================================================== -; ExecuteHltInstruction: Performs a hlt instruction. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; eax, ebx, ecx, edx, esp -; -;====================================================================== -ExecuteHltInstruction PROC PUBLIC - cli - hlt - ret -ExecuteHltInstruction ENDP - -;====================================================================== -; NmiHandler: Simply performs an IRET. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -NmiHandler PROC PUBLIC - iretq -NmiHandler ENDP - -;====================================================================== -; GetCsSelector: Returns the current protected mode CS selector. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -GetCsSelector PROC PUBLIC - ; This stub function is here to avoid compilation errors. - ; At this time, there is no need to provide a 64 bit function. - ret -GetCsSelector ENDP - -;====================================================================== -; SetIdtr: -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; none -; -; WARNING: This routine has a mirror routine in the PREMEM segment. -; These two routines MUST be sync'd for content. -;====================================================================== -SetIdtr PROC PUBLIC - ; This stub function is here to avoid compilation errors. - ; At this time, there is no need to provide a 64 bit function. - ret -SetIdtr ENDP - -;====================================================================== -; ExecuteWbinvdInstruction: Performs a wbinvd instruction. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -ExecuteWbinvdInstruction PROC PUBLIC - wbinvd ; Write back the cache tag RAMs - ret -ExecuteWbinvdInstruction ENDP - -END diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm deleted file mode 100644 index 63c85b94aa..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm +++ /dev/null @@ -1,497 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; $Workfile:: mu.asm $ $Revision:: 274#$ $Date: 2010-03-04 06:16:56 +0800 (Thu, 04 Mar 2010) $ -; Description: Main memory controller system configuration for AGESA -; -; -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** -;============================================================================ - - - .XLIST - .LIST - - .686p - .MODEL FLAT - .CODE - ASSUME FS: NOTHING - -; Define the calling convention used for the C library modules -;@attention - This should be in a central include file -CALLCONV EQU NEAR C - - -;=============================================================================== -;memUOutPort: -; -; Do a 32 Bit IO Out operation using edx. -; NOTE: This function will be obsolete in the future. -; -; In: Port - port number -; Value - value to be written -; -; Out: -; -; All registers preserved. -;=============================================================================== -MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD - pushad - mov edx,Port - mov eax,Value - out dx,al - popad - ret -MemUOutPort ENDP - - -;---------------------------------------------------------------------------- -; _SFENCE(); -; -_SFENCE macro - db 0Fh,0AEh,0F8h - endm - -;---------------------------------------------------------------------------- -; _MFENCE(); -; -_MFENCE macro - db 0Fh,0AEh,0F0h - endm - -;---------------------------------------------------------------------------- -; _EXECFENCE(); -; -_EXECFENCE macro - out 0EDh,al ;prevent speculative execution of following instructions - endm - -;=============================================================================== -;MemUWriteCachelines: -; Write a test pattern to DRAM -; -; In: Pattern - pointer to the write pattern -; Address - Physical address to be read -; ClCount - number of cachelines to be read -; Out: -; -;All registers preserved. -;=============================================================================== -MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD - pushad - push ds - - mov eax,Address - push ss - pop ds - xor edx,edx - mov edx, DWORD PTR Pattern - mov esi,edx - mov edx,16 - _EXECFENCE - xor ecx, ecx - mov cx,ClCount - shl ecx,2 - @@: - db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi] - db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits) - add eax,edx - add esi,edx - loop @B - - pop ds - popad - ret -MemUWriteCachelines ENDP - -;=============================================================================== -;MemUReadCachelines: -; -; Read a pattern of 72 bit times (per DQ), to test dram functionality. The -;pattern is a stress pattern which exercises both ISI and crosstalk. The number -;of cache lines to fill is dependent on DCT width mode and burstlength. -; -; In: Buffer - pointer to a buffer where read data will be stored -; Address - Physical address to be read -; ClCount - number of cachelines to be read -; Out: -; -;All registers preserved. -;=============================================================================== -MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD -LOCAL Count:BYTE - pushad - ; First, issue continuous dummy reads to fill up the cache - mov eax,Address - .if (ClCount > 18) - mov cx,ClCount - shr cx,4 - mov Count,cl - .while (Count != 0) - push eax - mov edi,eax - add edi,128 ;bias value (to account for signed displacement) - ;clflush opcode=0F AE /7 - mov esi,edi - mov ebx,esi - mov ecx,esi - mov edx,esi - add edi,4*64 ;TestAddr+4 cache lines - add ebx,8*64 ;TestAddr+8 cache lines - add ecx,12*64 ;TestAddr+12 cache lines - add edx,16*64 ;TestAddr+16 cache lines - sub edx,128 - _EXECFENCE - mov eax,fs:[esi-128] ;TestAddr - _MFENCE - mov eax,fs:[esi-64] ;TestAddr+1 cache line - _MFENCE - mov eax,fs:[esi] ;TestAddr+2 cache lines - _MFENCE - mov eax,fs:[esi+64] ;TestAddr+3 cache lines - _MFENCE - mov eax,fs:[edi-128] ;TestAddr+4 cache lines - _MFENCE - mov eax,fs:[edi-64] ;TestAddr+5 cache lines - _MFENCE - mov eax,fs:[edi] ;TestAddr+6 cache lines - _MFENCE - mov eax,fs:[edi+64] ;TestAddr+7 cache lines - _MFENCE - mov eax,fs:[ebx-128] ;TestAddr+8 cache lines - _MFENCE - mov eax,fs:[ebx-64] ;TestAddr+9 cache lines - _MFENCE - mov eax,fs:[ebx] ;TestAddr+10 cache lines - _MFENCE - mov eax,fs:[ebx+64] ;TestAddr+11 cache lines - _MFENCE - mov eax,fs:[ecx-128] ;TestAddr+12 cache lines - _MFENCE - mov eax,fs:[ecx-64] ;TestAddr+13 cache lines - _MFENCE - mov eax,fs:[ecx] ;TestAddr+14 cache lines - _MFENCE - mov eax,fs:[ecx+64] ;TestAddr+15 cache lines - _MFENCE - pop eax - add eax,(16*64) ;Next 16CL - dec Count - .endw - .else - mov edi,eax - add edi,128 ;bias value (to account for signed displacement) - ;clflush opcode=0F AE /7 - mov esi,edi - mov ebx,esi - mov ecx,esi - mov edx,esi - add edi,4*64 ;TestAddr+4 cache lines - add ebx,8*64 ;TestAddr+8 cache lines - add ecx,12*64 ;TestAddr+12 cache lines - add edx,16*64 ;TestAddr+16 cache lines - sub edx,128 - .if(ClCount == 1) - _MFENCE - mov eax,fs:[esi-128] ;TestAddr - _MFENCE - .elseif(ClCount == 3) - _EXECFENCE - mov eax,fs:[esi-128] ;TestAddr - _MFENCE - mov eax,fs:[esi-64] ;TestAddr+1 cache line - _MFENCE - mov eax,fs:[esi] ;TestAddr+2 cache lines - _MFENCE - .elseif(ClCount == 6) - _EXECFENCE - mov eax,fs:[esi-128] ;TestAddr - _MFENCE - mov eax,fs:[esi-64] ;TestAddr+1 cache line - _MFENCE - mov eax,fs:[esi] ;TestAddr+2 cache lines - _MFENCE - mov eax,fs:[esi+64] ;TestAddr+3 cache lines - _MFENCE - mov eax,fs:[edi-128] ;TestAddr+4 cache lines - _MFENCE - mov eax,fs:[edi-64] ;TestAddr+5 cache lines - _MFENCE - .elseif(ClCount == 9) - _EXECFENCE - mov eax,fs:[esi-128] ;TestAddr - _MFENCE - mov eax,fs:[esi-64] ;TestAddr+1 cache line - _MFENCE - mov eax,fs:[esi] ;TestAddr+2 cache lines - _MFENCE - mov eax,fs:[esi+64] ;TestAddr+3 cache lines - _MFENCE - mov eax,fs:[edi-128] ;TestAddr+4 cache lines - _MFENCE - mov eax,fs:[edi-64] ;TestAddr+5 cache lines - _MFENCE - mov eax,fs:[edi] ;TestAddr+6 cache lines - _MFENCE - mov eax,fs:[edi+64] ;TestAddr+7 cache lines - _MFENCE - mov eax,fs:[ebx-128] ;TestAddr+8 cache lines - _MFENCE - .elseif(ClCount == 18) - _EXECFENCE - mov eax,fs:[esi-128] ;TestAddr - _MFENCE - mov eax,fs:[esi-64] ;TestAddr+1 cache line - _MFENCE - mov eax,fs:[esi] ;TestAddr+2 cache lines - _MFENCE - mov eax,fs:[esi+64] ;TestAddr+3 cache lines - _MFENCE - mov eax,fs:[edi-128] ;TestAddr+4 cache lines - _MFENCE - mov eax,fs:[edi-64] ;TestAddr+5 cache lines - _MFENCE - mov eax,fs:[edi] ;TestAddr+6 cache lines - _MFENCE - mov eax,fs:[edi+64] ;TestAddr+7 cache lines - _MFENCE - mov eax,fs:[ebx-128] ;TestAddr+8 cache lines - _MFENCE - mov eax,fs:[ebx-64] ;TestAddr+9 cache lines - _MFENCE - mov eax,fs:[ebx] ;TestAddr+10 cache lines - _MFENCE - mov eax,fs:[ebx+64] ;TestAddr+11 cache lines - _MFENCE - mov eax,fs:[ecx-128] ;TestAddr+12 cache lines - _MFENCE - mov eax,fs:[ecx-64] ;TestAddr+13 cache lines - _MFENCE - mov eax,fs:[ecx] ;TestAddr+14 cache lines - _MFENCE - mov eax,fs:[ecx+64] ;TestAddr+15 cache lines - _MFENCE - mov eax,fs:[edx] ;TestAddr+16 cache lines - _MFENCE - mov eax,fs:[edx+64] ;TestAddr+17 cache lines - _MFENCE - .endif - .endif - _MFENCE - - ; Then, copy data to buffer - mov esi,Address - xor edx,edx - mov edx,DWORD PTR Buffer - mov edi,edx - xor ecx, ecx - mov cx,ClCount - shl ecx,6 - @@: - mov al,fs:[esi] - mov ss:[edi],al - inc esi - inc edi - loop @B - - popad - ret -MemUReadCachelines ENDP - -;=============================================================================== -;MemUDummyCLRead: -; -; Perform a single cache line read from a given physical address. -; -; In: Address - Physical address to be read -; ClCount - number of cachelines to be read -; Out: -; -;All registers preserved. -;=============================================================================== -MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD - _SFENCE - pushad - mov eax,Address - mov dl,fs:[eax] - popad - ret -MemUDummyCLRead ENDP - -;=============================================================================== -;MemUFlushPattern: -; -; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used -;to ensure cache miss on the next read training. -; -; In: Address - Physical address to be flushed -; ClCount - number of cachelines to be flushed -; Out: -; -;All registers preserved. -;=============================================================================== -MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD - pushad - mov edi,Address - movzx ecx,ClCount - @@: - _MFENCE ; Force strong ordering of clflush - db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi] - _MFENCE - add edi,64 - loop @B - popad - ret -MemUFlushPattern ENDP - - -;=============================================================================== -;MemUGetWrLvNblErr: -; Read ClCount number of cachelines then return the bitmap that indicates -; the write leveling result of each byte lane. -; -; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result -; Address - Physical address to be sampled -; ClCount - number of cachelines to be read -; -; OUT: ErrBitmap - WL result -; -;All registers preserved -;=============================================================================== -MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD -LOCAL ZeroCount[32]:WORD - - pushad - mov esi,Address - _EXECFENCE - ;Cache fill - movzx ecx,ClCount - @@: - mov eax,fs:[esi] - add esi,64 - loop @B - _MFENCE - - ; Then, count the number of 0's - ;push es - ;push ss - ;pop es - lea edi,ZeroCount - mov cx,SIZEOF ZeroCount - mov al,0 - rep stosb - ;pop es - - mov esi,Address - lea edi,ZeroCount - mov cx,ClCount - shl cx,6 - .while(cx > 0) - mov al,fs:[esi] - test al,00Fh ;check lower nibble - .if(ZERO?) - inc WORD PTR [edi] - .endif - add edi,2 - test al,0F0h ;check upper nibble - .if(ZERO?) - inc WORD PTR [edi] - .endif - add edi,2 - inc esi - dec cx - test cx,07h - .if(ZERO?) - sub edi,(16*2) - sub cx,8 - add esi,8 - .endif - .endw - - ; Then, average and compress data to error bits - lea esi,ZeroCount - mov dx,ClCount - shl dx,1 - xor eax,eax - xor ecx,ecx - mov cl,0 - .while(cl<16) - .if(WORD PTR [esi] < dx) - bts eax,ecx - .endif - add esi,2 - inc cl - .endw - xor edx,edx - mov dx,WORD PTR ErrBitmap - mov [edx], ax - - popad - ret -MemUGetWrLvNblErr ENDP - -;=============================================================================== -;AlignPointerTo16Byte: -; Modifies BufferPtr to be 16 byte aligned -; -; In: BufferPtrPtr - Pointer to buffer pointer -; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned -; -;All registers preserved. -;=============================================================================== -AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD - push edx - push eax - mov edx, BufferPtrPtr - mov eax, [edx] - add eax, 16 - and ax, 0FFF0h - mov [edx], eax - pop eax - pop edx - ret -AlignPointerTo16Byte ENDP - -;=============================================================================== -;MemUMFenceInstr: -; Serialize instruction -; -; In: -; Out: -; -;All registers preserved. -;=============================================================================== -MemUMFenceInstr PROC CALLCONV PUBLIC - _MFENCE - ret -MemUMFenceInstr ENDP - - END - diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm deleted file mode 100644 index 56db233be6..0000000000 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm +++ /dev/null @@ -1,187 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; $Workfile:: mu.asm $ $Revision:: 237#$ $Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $ -; Description: Main memory controller system configuration for AGESA DDR 2 -; -; -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** -;============================================================================ - - - .XLIST - .LIST - .686p - .MODEL FLAT - .CODE - ASSUME FS: NOTHING - - -; Define the calling convention used for the C library modules -;@attention - This should be in a central include file -CALLCONV EQU NEAR C - - -;=============================================================================== -;MemRecUOutPort: -; -; Do a 32 Bit IO Out operation using edx. -; NOTE: This function will be obsolete in the future. -; -; In: Port - port number -; Value - value to be written to port -; -; Out: -; -;All registers preserved except for "Out:" -;=============================================================================== -MemRecUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD - pushad - mov edx,Port - mov eax,Value - out dx,al - popad - ret -MemRecUOutPort ENDP - - - -;---------------------------------------------------------------------------- -; _MFENCE(); -; -_MFENCE macro - db 0Fh,0AEh,0F0h - endm - -;---------------------------------------------------------------------------- -; _EXECFENCE(); -; -_EXECFENCE macro - out 0EDh,al ;prevent speculative execution of following instructions - endm - -;=============================================================================== -;MemRecUWrite1CL: -; -; Write data from buffer to a system address -; -; In: Address - System address to read from -; Pattern - pointer pattern. -; -; Out: -; -;All registers preserved except for "Out:" -;=============================================================================== -MemRecUWrite1CL PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD - pushad - push ds - - mov eax,Address - push ss - pop ds - xor edx,edx - mov edx, DWORD PTR Pattern - mov esi,edx - mov edx,16 - _EXECFENCE - mov ecx,4 - @@: - db 66h,0Fh,6Fh,06 ;MOVDQA xmm0,[esi] - db 64h,66h,0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits) - add eax,edx - add esi,edx - loop @B - - pop ds - popad - ret -MemRecUWrite1CL ENDP - -;=============================================================================== -;MemRecURead1CL: -; -; Read one cacheline to buffer -; -; In: Buffer - pointer buffer. -; : Address - System address to read from -; -; Out: -; -;All registers preserved except for "Out:" -;=============================================================================== -MemRecURead1CL PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD - - pushad - - mov esi,Address - xor edx,edx - mov edx,DWORD PTR Buffer - mov edi,edx - mov ecx,64 - @@: - mov al,fs:[esi] - mov ss:[edi],al - inc esi - inc edi - loop @B - - popad - ret -MemRecURead1CL ENDP - - -;=============================================================================== -;MemRecUFlushPattern: -; -; Flush one cache line -; -; In: Address - System address [31:0] -; Out: -; -;All registers preserved except for "Out:" -;=============================================================================== -MemRecUFlushPattern PROC CALLCONV PUBLIC Address:DWORD - pushad - mov eax,Address - _EXECFENCE - ;clflush fs:[eax] - db 064h ;access relative to FS BASE prefix - db 00Fh ;opcode - db 0AEh ;opcode - db 038h ;eax indirect addressing - _MFENCE - popad - ret -MemRecUFlushPattern ENDP - - - - END - -- cgit v1.2.3