From c8e4742f918b6029137bbe4e5d8fda9df52cb274 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 31 Aug 2017 08:52:12 +0300 Subject: AGESA vendorcode: Move PlatformInstall.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All thse Option.*Install.h files are about configuring what eventually is referenced in the final libagesa build. It's self-contained so isolate these together with PlatformInstall.h to hide them from rest of the build. Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/21298 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- .../amd/agesa/f12/Config/OptionC6Install.h | 140 + .../amd/agesa/f12/Config/OptionCpbInstall.h | 144 + .../f12/Config/OptionCpuCacheFlushOnHaltInstall.h | 117 + .../f12/Config/OptionCpuCoreLevelingInstall.h | 109 + .../agesa/f12/Config/OptionCpuFamiliesInstall.h | 382 ++ .../agesa/f12/Config/OptionCpuFeaturesInstall.h | 75 + .../amd/agesa/f12/Config/OptionDmiInstall.h | 206 + .../amd/agesa/f12/Config/OptionFamily12hInstall.h | 696 ++++ .../amd/agesa/f12/Config/OptionFchInstall.h | 928 +++++ .../agesa/f12/Config/OptionGfxRecoveryInstall.h | 53 + .../amd/agesa/f12/Config/OptionGnbInstall.h | 592 +++ .../amd/agesa/f12/Config/OptionHtInstall.h | 304 ++ .../amd/agesa/f12/Config/OptionHwC1eInstall.h | 80 + .../amd/agesa/f12/Config/OptionIdsInstall.h | 414 ++ .../amd/agesa/f12/Config/OptionIoCstateInstall.h | 132 + .../amd/agesa/f12/Config/OptionL3FeaturesInstall.h | 104 + .../agesa/f12/Config/OptionLowPwrPstateInstall.h | 86 + .../amd/agesa/f12/Config/OptionMemoryInstall.h | 4202 ++++++++++++++++++++ .../agesa/f12/Config/OptionMemoryRecoveryInstall.h | 599 +++ .../agesa/f12/Config/OptionMsgBasedC1eInstall.h | 116 + .../agesa/f12/Config/OptionMultiSocketInstall.h | 94 + .../f12/Config/OptionPreserveMailboxInstall.h | 122 + .../amd/agesa/f12/Config/OptionPstateInstall.h | 254 ++ .../amd/agesa/f12/Config/OptionS3ScriptInstall.h | 91 + .../amd/agesa/f12/Config/OptionSlitInstall.h | 79 + .../amd/agesa/f12/Config/OptionSratInstall.h | 73 + .../amd/agesa/f12/Config/OptionSwC1eInstall.h | 80 + .../amd/agesa/f12/Config/OptionWheaInstall.h | 74 + .../amd/agesa/f12/Config/PlatformInstall.h | 2588 ++++++++++++ .../amd/agesa/f12/Include/OptionC6Install.h | 140 - .../amd/agesa/f12/Include/OptionCpbInstall.h | 144 - .../f12/Include/OptionCpuCacheFlushOnHaltInstall.h | 117 - .../f12/Include/OptionCpuCoreLevelingInstall.h | 109 - .../agesa/f12/Include/OptionCpuFamiliesInstall.h | 382 -- .../agesa/f12/Include/OptionCpuFeaturesInstall.h | 75 - .../amd/agesa/f12/Include/OptionDmiInstall.h | 206 - .../amd/agesa/f12/Include/OptionFamily12hInstall.h | 696 ---- .../amd/agesa/f12/Include/OptionFchInstall.h | 928 ----- .../agesa/f12/Include/OptionGfxRecoveryInstall.h | 53 - .../amd/agesa/f12/Include/OptionGnbInstall.h | 592 --- .../amd/agesa/f12/Include/OptionHtInstall.h | 304 -- .../amd/agesa/f12/Include/OptionHwC1eInstall.h | 80 - .../amd/agesa/f12/Include/OptionIdsInstall.h | 414 -- .../amd/agesa/f12/Include/OptionIoCstateInstall.h | 132 - .../agesa/f12/Include/OptionL3FeaturesInstall.h | 104 - .../agesa/f12/Include/OptionLowPwrPstateInstall.h | 86 - .../amd/agesa/f12/Include/OptionMemoryInstall.h | 4202 -------------------- .../f12/Include/OptionMemoryRecoveryInstall.h | 599 --- .../agesa/f12/Include/OptionMsgBasedC1eInstall.h | 116 - .../agesa/f12/Include/OptionMultiSocketInstall.h | 94 - .../f12/Include/OptionPreserveMailboxInstall.h | 122 - .../amd/agesa/f12/Include/OptionPstateInstall.h | 254 -- .../amd/agesa/f12/Include/OptionS3ScriptInstall.h | 91 - .../amd/agesa/f12/Include/OptionSlitInstall.h | 79 - .../amd/agesa/f12/Include/OptionSratInstall.h | 73 - .../amd/agesa/f12/Include/OptionSwC1eInstall.h | 80 - .../amd/agesa/f12/Include/OptionWheaInstall.h | 74 - .../amd/agesa/f12/Include/PlatformInstall.h | 2588 ------------ src/vendorcode/amd/agesa/f12/Makefile.inc | 2 + 59 files changed, 12936 insertions(+), 12934 deletions(-) create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionC6Install.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionCpbInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionCpuCacheFlushOnHaltInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionCpuCoreLevelingInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionCpuFeaturesInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionDmiInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionFchInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionGfxRecoveryInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionGnbInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionHtInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionHwC1eInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionIoCstateInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionL3FeaturesInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionLowPwrPstateInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionMemoryInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionMemoryRecoveryInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionMsgBasedC1eInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionMultiSocketInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionPreserveMailboxInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionPstateInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionS3ScriptInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionSlitInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionSratInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionSwC1eInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/OptionWheaInstall.h create mode 100644 src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionC6Install.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionCpbInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionCpuCacheFlushOnHaltInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionCpuCoreLevelingInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionCpuFamiliesInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionCpuFeaturesInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionFamily12hInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionFchInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionGfxRecoveryInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionGnbInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionHtInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionHwC1eInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionIdsInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionIoCstateInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionLowPwrPstateInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionMemoryRecoveryInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionMsgBasedC1eInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionMultiSocketInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionPreserveMailboxInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionS3ScriptInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionSlitInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionSratInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionSwC1eInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/OptionWheaInstall.h delete mode 100644 src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h (limited to 'src/vendorcode/amd/agesa/f12') diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionC6Install.h b/src/vendorcode/amd/agesa/f12/Config/OptionC6Install.h new file mode 100644 index 0000000000..e5c2c8e2ee --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionC6Install.h @@ -0,0 +1,140 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: C6 C-state + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_C6_STATE_INSTALL_H_ +#define _OPTION_C6_STATE_INSTALL_H_ + +#include "cpuC6State.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_C6_STATE_FEAT +#define F12_C6_STATE_SUPPORT +#define F14_ON_C6_STATE_SUPPORT +#define F15_OR_C6_STATE_SUPPORT + +#if OPTION_C6_STATE == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + #if OPTION_FAMILY12H_LN == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; + #undef OPTION_C6_STATE_FEAT + #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, + extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support; + #undef F12_C6_STATE_SUPPORT + #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support}, + + #if OPTION_EARLY_SAMPLES == TRUE + extern F_F12_ES_C6_INIT F12C6A0Workaround; + + CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support = + { + F12C6A0Workaround + }; + #else + CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support = + { + (PF_F12_ES_C6_INIT) CommonVoid + }; + #endif + + #endif + #endif + #endif + + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + #if (OPTION_FAMILY14H_ON == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; + #undef OPTION_C6_STATE_FEAT + #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, + extern CONST C6_FAMILY_SERVICES ROMDATA F14OnC6Support; + #undef F14_ON_C6_STATE_SUPPORT + #define F14_ON_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14OnC6Support}, + + CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support = + { + (PF_F14_ON_ES_IS_C6_SUPPORTED) CommonVoid, + (PF_F14_ON_ES_C6_INIT) CommonVoid + }; + #endif + #endif + #endif + + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if (OPTION_FAMILY15H_OR == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; + #undef OPTION_C6_STATE_FEAT + #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, + extern CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support; + #undef F15_OR_C6_STATE_SUPPORT + #define F15_OR_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrC6Support}, + CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support = + { + (PF_F15_OR_ES_IS_C6_SUPPORTED) CommonVoid + }; + #endif + #endif + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] = +{ + F12_C6_STATE_SUPPORT + F14_ON_C6_STATE_SUPPORT + F15_OR_C6_STATE_SUPPORT + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable = +{ + (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &C6FamilyServiceArray[0] +}; + +#endif // _OPTION_C6_STATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionCpbInstall.h new file mode 100644 index 0000000000..72720063c7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionCpbInstall.h @@ -0,0 +1,144 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Core Performance Boost + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 46389 $ @e \$Date: 2011-02-01 11:22:49 +0800 (Tue, 01 Feb 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_CPB_INSTALL_H_ +#define _OPTION_CPB_INSTALL_H_ + +#include "cpuCpb.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPB_FEAT +#define F10_CPB_SUPPORT +#define F12_CPB_SUPPORT +#define F14_ON_CPB_SUPPORT +#define F15_OR_CPB_SUPPORT + +#if OPTION_CPB == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) + // Family 10h + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if OPTION_FAMILY10H_PH == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; + #undef OPTION_CPB_FEAT + #define OPTION_CPB_FEAT &CpuFeatureCpb, + extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport; + #undef F10_CPB_SUPPORT + #define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport}, + #endif + #endif + #endif + + // Family 12h + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + #if OPTION_FAMILY12H_LN == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; + #undef OPTION_CPB_FEAT + #define OPTION_CPB_FEAT &CpuFeatureCpb, + extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport; + #undef F12_CPB_SUPPORT + #define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport}, +// CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport = +// { +// (PF_F12_ES_CPB_INIT) CommonVoid +// }; + #endif + #endif + #endif + + // Family 14h + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + #if OPTION_FAMILY14H_ON == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; + #undef OPTION_CPB_FEAT + #define OPTION_CPB_FEAT &CpuFeatureCpb, + extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport; + #undef F14_ON_CPB_SUPPORT + #define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport}, + #endif + #endif + #endif + + // Family 15h + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if (OPTION_FAMILY15H_OR == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; + #undef OPTION_CPB_FEAT + #define OPTION_CPB_FEAT &CpuFeatureCpb, + extern CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport; + #undef F15_OR_CPB_SUPPORT + #define F15_OR_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15OrCpbSupport}, + + CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport = + { + (PF_F15_OR_ES_IS_CPB_SUPPORTED) CommonVoid + }; + #endif + #endif + #endif + + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] = +{ + F10_CPB_SUPPORT + F12_CPB_SUPPORT + F14_ON_CPB_SUPPORT + F15_OR_CPB_SUPPORT + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable = +{ + (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &CpbFamilyServiceArray[0] +}; + +#endif // _OPTION_CPB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionCpuCacheFlushOnHaltInstall.h new file mode 100644 index 0000000000..15949d0e34 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionCpuCacheFlushOnHaltInstall.h @@ -0,0 +1,117 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: CPU Cache Flush On Halt + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44737 $ @e \$Date: 2011-01-05 15:59:55 +0800 (Wed, 05 Jan 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ +#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ + +#include "cpuPostInit.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT +#define F10_BL_CPU_CFOH_SUPPORT +#define F10_DA_CPU_CFOH_SUPPORT +#define F10_CPU_CFOH_SUPPORT +#define F15_OR_CPU_CFOH_SUPPORT + +#if OPTION_CPU_CFOH == TRUE + #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt; + #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT + #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt, + + #if OPTION_FAMILY10H_BL == TRUE + extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt; + #undef F10_BL_CPU_CFOH_SUPPORT + #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt}, + #endif + + #if OPTION_FAMILY10H_DA == TRUE + extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt; + #undef F10_DA_CPU_CFOH_SUPPORT + #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt}, + #endif + + #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE) + extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt; + #undef F10_CPU_CFOH_SUPPORT + #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt}, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt; + #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT + #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt, + + #if OPTION_FAMILY15H_OR == TRUE + extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt; + #undef F15_OR_CPU_CFOH_SUPPORT + #define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15OrCacheFlushOnHalt}, + #endif + #endif + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] = +{ + F10_BL_CPU_CFOH_SUPPORT + F10_DA_CPU_CFOH_SUPPORT + F10_CPU_CFOH_SUPPORT + F15_OR_CPU_CFOH_SUPPORT + {0, NULL} +}; +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable = +{ + (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &CacheFlushOnHaltFamilyServiceArray[0] +}; + +#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionCpuCoreLevelingInstall.h new file mode 100644 index 0000000000..c598283b6b --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionCpuCoreLevelingInstall.h @@ -0,0 +1,109 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: CPU Core Leveling + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_ +#define _OPTION_CPU_CORELEVELING_INSTALL_H_ + + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPU_CORE_LEVELING_FEAT +#define F10_REVE_CPU_CORELEVELING_SUPPORT +#define F10_REVD_CPU_CORELEVELING_SUPPORT +#define F10_REVC_CPU_CORELEVELING_SUPPORT +#define F15_OR_CPU_CORELEVELING_SUPPORT + +#if OPTION_CPU_CORELEVLING == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) + // Family 10h + #if OPTION_FAMILY10H == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling; + #undef OPTION_CPU_CORE_LEVELING_FEAT + #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling, + #if OPTION_FAMILY10H_HY == TRUE + extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling; + #undef F10_REVD_CPU_CORELEVELING_SUPPORT + #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling}, + #endif + + #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) + extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling; + #undef F10_REVC_CPU_CORELEVELING_SUPPORT + #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling}, + #endif + + #if (OPTION_FAMILY10H_PH == TRUE) + extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling; + #undef F10_REVE_CPU_CORELEVELING_SUPPORT + #define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling}, + #endif + #endif + // Family 15h + #if OPTION_FAMILY15H == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling; + #undef OPTION_CPU_CORE_LEVELING_FEAT + #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling, + + extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling; + #undef F15_OR_CPU_CORELEVELING_SUPPORT + #define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling}, + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] = +{ + F10_REVE_CPU_CORELEVELING_SUPPORT + F10_REVD_CPU_CORELEVELING_SUPPORT + F10_REVC_CPU_CORELEVELING_SUPPORT + {0, NULL} +}; +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable = +{ + (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &CoreLevelingFamilyServiceArray[0] +}; + +#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h new file mode 100644 index 0000000000..b161cd3be7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h @@ -0,0 +1,382 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of all appropriate CPU family specific support. + * + * This file generates the defaults tables for all family specific + * combinations. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/* Default all CPU Specific Service members to off. They + will be enabled as needed by cross referencing families + with entry points in the family / model install files. */ +#define GET_PSTATE_POWER FALSE +#define GET_PSTATE_FREQ FALSE +#define DISABLE_PSTATE FALSE +#define TRANSITION_PSTATE FALSE +#define PROC_IDD_MAX FALSE +#define GET_TSC_RATE FALSE +#define PSTATE_TRANSITION_LATENCY FALSE +#define GET_PSTATE_REGISTER_INFO FALSE +#define GET_PSTATE_MAX_STATE FALSE +#define SET_PSTATE_LEVELING_REG FALSE +#define GET_NB_FREQ FALSE +#define GET_NB_IDD_MAX FALSE +#define IS_NBCOF_INIT_NEEDED FALSE +#define AP_INITIAL_LAUNCH FALSE +#define GET_AP_MAILBOX_FROM_HW FALSE +#define SET_AP_CORE_NUMBER FALSE +#define GET_AP_CORE_NUMBER FALSE +#define TRANSFER_AP_CORE_NUMBER FALSE +#define ID_POSITION_INITIAL_APICID FALSE +#define SAVE_FEATURES FALSE +#define WRITE_FEATURES FALSE +#define SET_DOWN_CORE_REG FALSE +#define SET_WARM_RESET_FLAG FALSE +#define GET_WARM_RESET_FLAG FALSE +#define USES_REGISTER_TABLES FALSE +#define BASE_FAMILY_PCI FALSE +#define MODEL_SPECIFIC_PCI FALSE +#define BASE_FAMILY_MSR FALSE +#define MODEL_SPECIFIC_MSR FALSE +#define BRAND_STRING1 FALSE +#define BRAND_STRING2 FALSE +#define BASE_FAMILY_HT_PCI FALSE +#define MODEL_SPECIFIC_HT_PCI FALSE +#define BASE_FAMILY_WORKAROUNDS FALSE +#define GET_PATCHES FALSE +#define GET_PATCHES_EQUIVALENCE_TABLE FALSE +#define GET_CACHE_INFO FALSE +#define GET_SYSTEM_PM_TABLE FALSE +#define GET_WHEA_INIT FALSE +#define GET_CFOH_REG FALSE +#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE +#define IS_NB_PSTATE_ENABLED FALSE + +/* + * Pull in family specific services based on entry point + */ +#if AGESA_ENTRY_INIT_RESET == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef GET_AP_MAILBOX_FROM_HW + #define GET_AP_MAILBOX_FROM_HW TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef TRANSFER_AP_CORE_NUMBER + #define TRANSFER_AP_CORE_NUMBER TRUE +#endif + +#if AGESA_ENTRY_INIT_RECOVERY == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef USES_REGISTER_TABLES + #define USES_REGISTER_TABLES TRUE + #undef BASE_FAMILY_PCI + #define BASE_FAMILY_PCI TRUE + #undef MODEL_SPECIFIC_PCI + #define MODEL_SPECIFIC_PCI TRUE + #undef BASE_FAMILY_MSR + #define BASE_FAMILY_MSR TRUE + #undef MODEL_SPECIFIC_MSR + #define MODEL_SPECIFIC_MSR TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE + #undef GET_PATCHES + #define GET_PATCHES TRUE + #undef GET_PATCHES_EQUIVALENCE_TABLE + #define GET_PATCHES_EQUIVALENCE_TABLE TRUE +#endif + +#if AGESA_ENTRY_INIT_EARLY == TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef DISABLE_PSTATE + #define DISABLE_PSTATE TRUE + #undef PROC_IDD_MAX + #define PROC_IDD_MAX TRUE + #undef GET_TSC_RATE + #define GET_TSC_RATE TRUE + #undef GET_NB_FREQ + #define GET_NB_FREQ TRUE + #undef GET_NB_IDD_MAX + #define GET_NB_IDD_MAX TRUE + #undef IS_NBCOF_INIT_NEEDED + #define IS_NBCOF_INIT_NEEDED TRUE + #undef AP_INITIAL_LAUNCH + #define AP_INITIAL_LAUNCH TRUE + #undef GET_AP_MAILBOX_FROM_HW + #define GET_AP_MAILBOX_FROM_HW TRUE + #undef SET_AP_CORE_NUMBER + #define SET_AP_CORE_NUMBER TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef TRANSFER_AP_CORE_NUMBER + #define TRANSFER_AP_CORE_NUMBER TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef SET_DOWN_CORE_REG + #define SET_DOWN_CORE_REG TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef USES_REGISTER_TABLES + #define USES_REGISTER_TABLES TRUE + #undef BASE_FAMILY_PCI + #define BASE_FAMILY_PCI TRUE + #undef MODEL_SPECIFIC_PCI + #define MODEL_SPECIFIC_PCI TRUE + #undef BASE_FAMILY_MSR + #define BASE_FAMILY_MSR TRUE + #undef MODEL_SPECIFIC_MSR + #define MODEL_SPECIFIC_MSR TRUE + #undef BRAND_STRING1 + #define BRAND_STRING1 TRUE + #undef BRAND_STRING2 + #define BRAND_STRING2 TRUE + #undef BASE_FAMILY_HT_PCI + #define BASE_FAMILY_HT_PCI TRUE + #undef MODEL_SPECIFIC_HT_PCI + #define MODEL_SPECIFIC_HT_PCI TRUE + #undef BASE_FAMILY_WORKAROUNDS + #define BASE_FAMILY_WORKAROUNDS TRUE + #undef GET_PATCHES + #define GET_PATCHES TRUE + #undef GET_PATCHES_EQUIVALENCE_TABLE + #define GET_PATCHES_EQUIVALENCE_TABLE TRUE + #undef GET_SYSTEM_PM_TABLE + #define GET_SYSTEM_PM_TABLE TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_POST == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef GET_PSTATE_POWER + #define GET_PSTATE_POWER TRUE + #undef GET_PSTATE_FREQ + #define GET_PSTATE_FREQ TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PROC_IDD_MAX + #define PROC_IDD_MAX TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef GET_PSTATE_REGISTER_INFO + #define GET_PSTATE_REGISTER_INFO TRUE + #undef GET_PSTATE_MAX_STATE + #define GET_PSTATE_MAX_STATE TRUE + #undef SET_PSTATE_LEVELING_REG + #define SET_PSTATE_LEVELING_REG TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef SAVE_FEATURES + #define SAVE_FEATURES TRUE + #undef WRITE_FEATURES + #define WRITE_FEATURES TRUE + #undef GET_CFOH_REG + #define GET_CFOH_REG TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_ENV == TRUE +#endif + +#if AGESA_ENTRY_INIT_MID == TRUE +#endif + +#if AGESA_ENTRY_INIT_LATE == TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef GET_PSTATE_FREQ + #define GET_PSTATE_FREQ TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PSTATE_TRANSITION_LATENCY + #define PSTATE_TRANSITION_LATENCY TRUE + #undef GET_WHEA_INIT + #define GET_WHEA_INIT TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef GET_TSC_RATE + #define GET_TSC_RATE TRUE + #undef BRAND_STRING1 + #define BRAND_STRING1 TRUE + #undef BRAND_STRING2 + #define BRAND_STRING2 TRUE +#endif + +#if AGESA_ENTRY_INIT_S3SAVE == TRUE +#endif + +#if AGESA_ENTRY_INIT_RESUME == TRUE + #undef GET_CFOH_REG + #define GET_CFOH_REG TRUE +#endif + +#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE +#endif + +#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE +#endif + +/* + * Initialize PCI MMIO mask to 0 + */ +#define FAMILY_MMIO_BASE_MASK (0ull) + + +/* + * Initialize all families to disabled + */ +#define OPT_F12_TABLE + +#define OPT_F12_ID_TABLE + + +/* + * Install family specific support + */ + +#if (OPTION_FAMILY12H == TRUE) + #include "OptionFamily12hInstall.h" +#endif + +/* + * Process PCI MMIO mask + */ + +// If size is 0, but base is not, break the build. +#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0) + #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 +#endif + +// If base is 0, but size is not, break the build. +#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0) + #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater +#endif + +#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0) + // Both are non-zero, begin further processing. + + // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB. + #if (CFG_PCI_MMIO_BASE < 0x800000) + #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater + #endif + + // Break the build if the address is too high for the enabled families. + #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0) + #error BLDCFG: Invalid PCI MMIO base address for the installed CPU families + #endif + + // If the size parameter is not valid, break the build. + #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16) + #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256) + #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 + #endif + #endif + + #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1) + // If the base is not aligned according to size, break the build. + #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0) + #error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size + #endif + #undef PCI_MMIO_ALIGNMENT +#endif + +/* + * Process sockets / modules + */ +#ifndef ADVCFG_PLATFORM_SOCKETS + #error BLDOPT Set Family supported sockets. +#endif +#ifndef ADVCFG_PLATFORM_MODULES + #error BLDOPT Set Family supported modules. +#endif + +CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration = +{ + ADVCFG_PLATFORM_SOCKETS, + ADVCFG_PLATFORM_MODULES +}; + +/* + * Instantiate global data needed for processor identification + */ +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] = +{ + OPT_F12_TABLE +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable = +{ + (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &CpuSupportedFamiliesArray[0] +}; + + +CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] = +{ + OPT_F12_ID_TABLE +}; + +CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable = +{ + (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)), + CpuSupportedFamilyIdArray +}; diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionCpuFeaturesInstall.h new file mode 100644 index 0000000000..ba4b42b8fb --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionCpuFeaturesInstall.h @@ -0,0 +1,75 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of multiple CPU features. + * + * Aggregates enabled CPU features into a list for the dispatcher to process. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_CPU_FEATURES_INSTALL_H_ +#define _OPTION_CPU_FEATURES_INSTALL_H_ + +#include "OptionHwC1eInstall.h" +#include "OptionMsgBasedC1eInstall.h" +#include "OptionSwC1eInstall.h" +#include "OptionL3FeaturesInstall.h" +#include "OptionCpuCoreLevelingInstall.h" +#include "OptionIoCstateInstall.h" +#include "OptionC6Install.h" +#include "OptionCpbInstall.h" +#include "OptionCpuCacheFlushOnHaltInstall.h" +#include "OptionLowPwrPstateInstall.h" +#include "OptionPreserveMailboxInstall.h" + +CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] = +{ + OPTION_HW_C1E_FEAT + OPTION_MSG_BASED_C1E_FEAT + OPTION_SW_C1E_FEAT + OPTION_L3_FEAT + OPTION_CPU_CORE_LEVELING_FEAT + OPTION_IO_CSTATE_FEAT + OPTION_C6_STATE_FEAT + OPTION_CPB_FEAT + OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT + OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT // this function should be run before creating ACPI objects and after Pstate initialization + OPTION_PRESERVE_MAILBOX_FEAT + NULL +}; + + +#endif // _OPTION_CPU_FEATURES_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionDmiInstall.h new file mode 100644 index 0000000000..ead4fcec6a --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionDmiInstall.h @@ -0,0 +1,206 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: DMI + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_DMI_INSTALL_H_ +#define _OPTION_DMI_INSTALL_H_ + +#include "cpuLateInit.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#if AGESA_ENTRY_INIT_LATE == TRUE + #ifndef OPTION_DMI + #error BLDOPT: Option not defined: "OPTION_DMI" + #endif + #if OPTION_DMI == TRUE + OPTION_DMI_FEATURE GetDmiInfoMain; + OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer; + #define USER_DMI_OPTION &GetDmiInfoMain + #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer + + // This additional check keeps AP launch routines from being unnecessarily included + // in single socket systems. + #if OPTION_MULTISOCKET == TRUE + #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, + #else + #define CPU_DMI_AP_GET_TYPE4_TYPE7 + #endif + + // Family 10 + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + extern PROC_FAMILY_TABLE ProcFamily10DmiTable; + #define FAM10_DMI_SUPPORT FAM10_ENABLED, + #define FAM10_DMI_TABLE &ProcFamily10DmiTable, + #else + #define FAM10_DMI_SUPPORT + #define FAM10_DMI_TABLE + #endif + #else + #define FAM10_DMI_SUPPORT + #define FAM10_DMI_TABLE + #endif + + // Family 12 + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + extern PROC_FAMILY_TABLE ProcFamily12DmiTable; + #define FAM12_DMI_SUPPORT FAM12_ENABLED, + #define FAM12_DMI_TABLE &ProcFamily12DmiTable, + #else + #define FAM12_DMI_SUPPORT + #define FAM12_DMI_TABLE + #endif + #else + #define FAM12_DMI_SUPPORT + #define FAM12_DMI_TABLE + #endif + + // Family 14 + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + extern PROC_FAMILY_TABLE ProcFamily14DmiTable; + #define FAM14_DMI_SUPPORT FAM14_ENABLED, + #define FAM14_DMI_TABLE &ProcFamily14DmiTable, + #else + #define FAM14_DMI_SUPPORT + #define FAM14_DMI_TABLE + #endif + #else + #define FAM14_DMI_SUPPORT + #define FAM14_DMI_TABLE + #endif + + // Family 15 + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if OPTION_FAMILY15H_OR == TRUE + extern PROC_FAMILY_TABLE ProcFamily15OrDmiTable; + #define FAM15_OR_DMI_SUPPORT FAM15_OR_ENABLED, + #define FAM15_OR_DMI_TABLE &ProcFamily15OrDmiTable, + #else + #define FAM15_OR_DMI_SUPPORT + #define FAM15_OR_DMI_TABLE + #endif + #define FAM15_TN_DMI_SUPPORT + #define FAM15_TN_DMI_TABLE + #else + #define FAM15_OR_DMI_SUPPORT + #define FAM15_OR_DMI_TABLE + #define FAM15_TN_DMI_SUPPORT + #define FAM15_TN_DMI_TABLE + #endif + #else + #define FAM15_OR_DMI_SUPPORT + #define FAM15_OR_DMI_TABLE + #define FAM15_TN_DMI_SUPPORT + #define FAM15_TN_DMI_TABLE + #endif + + #else + OPTION_DMI_FEATURE GetDmiInfoStub; + OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; + #define USER_DMI_OPTION GetDmiInfoStub + #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub + #define FAM10_DMI_SUPPORT + #define FAM10_DMI_TABLE + #define FAM12_DMI_SUPPORT + #define FAM12_DMI_TABLE + #define FAM14_DMI_SUPPORT + #define FAM14_DMI_TABLE + #define FAM15_OR_DMI_SUPPORT + #define FAM15_OR_DMI_TABLE + #define FAM15_TN_DMI_SUPPORT + #define FAM15_TN_DMI_TABLE + #define CPU_DMI_AP_GET_TYPE4_TYPE7 + #endif +#else + OPTION_DMI_FEATURE GetDmiInfoStub; + OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; + #define USER_DMI_OPTION GetDmiInfoStub + #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub + #define FAM10_DMI_SUPPORT + #define FAM10_DMI_TABLE + #define FAM12_DMI_SUPPORT + #define FAM12_DMI_TABLE + #define FAM14_DMI_SUPPORT + #define FAM14_DMI_TABLE + #define FAM15_OR_DMI_SUPPORT + #define FAM15_OR_DMI_TABLE + #define FAM15_TN_DMI_SUPPORT + #define FAM15_TN_DMI_TABLE + #define CPU_DMI_AP_GET_TYPE4_TYPE7 +#endif + +/// DMI supported families enum +typedef enum { + FAM10_DMI_SUPPORT ///< Conditionally define F10 support + FAM12_DMI_SUPPORT ///< Conditionally define F12 support + FAM14_DMI_SUPPORT ///< Conditionally define F14 support + FAM15_OR_DMI_SUPPORT ///< Conditionally define F15 OR support + FAM15_TN_DMI_SUPPORT ///< Conditionally define F15 TN support + NUM_DMI_FAMILIES ///< Number of installed families +} AGESA_DMI_SUPPORTED_FAM; + +/* Declare the Family List. An array of pointers to tables that each describe a family */ +CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = { + FAM10_DMI_TABLE + FAM12_DMI_TABLE + FAM14_DMI_TABLE + FAM15_OR_DMI_TABLE + FAM15_TN_DMI_TABLE + NULL +}; + +/* Declare the instance of the DMI option configuration structure */ +CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = { + DMI_STRUCT_VERSION, + USER_DMI_OPTION, + USER_DMI_RELEASE_BUFFER, + NUM_DMI_FAMILIES, + (VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl +}; + +#endif // _OPTION_DMI_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h new file mode 100644 index 0000000000..63cb0ff3cb --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h @@ -0,0 +1,696 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of family 12h support + * + * This file generates the defaults tables for family 12h processors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_FAMILY_12H_INSTALL_H_ +#define _OPTION_FAMILY_12H_INSTALL_H_ + + +#include "OptionFamily12hEarlySample.h" + +/* + * Common Family 12h routines + */ +extern F_CPU_DISABLE_PSTATE F12DisablePstate; +extern F_CPU_TRANSITION_PSTATE F12TransitionPstate; +extern F_CPU_GET_TSC_RATE F12GetTscRate; +extern F_CPU_GET_NB_FREQ F12GetCurrentNbFrequency; +extern F_CPU_GET_NB_PSTATE_INFO F12GetNbPstateInfo; +extern F_CPU_IS_NBCOF_INIT_NEEDED F12GetNbCofVidUpdate; +extern F_CPU_AP_INITIAL_LAUNCH F12LaunchApCore; +extern F_CPU_GET_IDD_MAX F12GetProcIddMax; +extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F12GetApMailboxFromHardware; +extern F_CPU_GET_AP_CORE_NUMBER F12GetApCoreNumber; +extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F12CpuAmdCoreIdPositionInInitialApicId; +extern F_CPU_SET_DOWN_CORE_REGISTER F12SetDownCoreRegister; +extern F_CPU_SET_WARM_RESET_FLAG F12SetAgesaWarmResetFlag; +extern F_CPU_GET_WARM_RESET_FLAG F12GetAgesaWarmResetFlag; +extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString1; +extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString2; +extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12CacheInfo; +extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12SysPmTable; +extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12WheaInitData; +//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray; +extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F12GetPlatformTypeSpecificInfo; +extern CONST REGISTER_TABLE ROMDATA F12PciRegisterTable; +extern CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable; +extern CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable; +extern F_CPU_NUMBER_OF_PHYSICAL_CORES F12GetNumberOfPhysicalCores; +extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable; +extern F_IS_NB_PSTATE_ENABLED F12IsNbPstateEnabled; +#if OPTION_EARLY_SAMPLES == TRUE + extern CONST REGISTER_TABLE ROMDATA F12EarlySampleMsrRegisterTable; +#endif + +/* + * Install family 12h model 0 support + */ + +#ifdef OPTION_FAMILY12H_LN + #if OPTION_FAMILY12H_LN == TRUE + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicroCodePatchesStruct; + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicrocodeEquivalenceTable; + + #if USES_REGISTER_TABLES == TRUE + CONST REGISTER_TABLE ROMDATA *F12LnRegisterTables[] = + { + #if BASE_FAMILY_PCI == TRUE + &F12PciRegisterTable, + #endif + #if BASE_FAMILY_PCI == TRUE + &F12PerCorePciRegisterTable, + #endif + #if BASE_FAMILY_MSR == TRUE + &F12MsrRegisterTable, + #if OPTION_EARLY_SAMPLES == TRUE + &F12EarlySampleMsrRegisterTable, + #endif + #endif + // the end. + NULL + }; + #endif + + #if USES_REGISTER_TABLES == TRUE + CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12LnTableEntryTypeDescriptors[] = + { + {MsrRegister, SetRegisterForMsrEntry}, + {PciRegister, SetRegisterForPciEntry}, + {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, + {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid}, + // End + {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} + }; + #endif + + CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12LnServices = + { + 0, + #if DISABLE_PSTATE == TRUE + F12DisablePstate, + #else + (PF_CPU_DISABLE_PSTATE) CommonAssert, + #endif + #if TRANSITION_PSTATE == TRUE + F12TransitionPstate, + #else + (PF_CPU_TRANSITION_PSTATE) CommonAssert, + #endif + #if PROC_IDD_MAX == TRUE + F12GetProcIddMax, + #else + (PF_CPU_GET_IDD_MAX) CommonAssert, + #endif + #if GET_TSC_RATE == TRUE + F12GetTscRate, + #else + (PF_CPU_GET_TSC_RATE) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + F12GetCurrentNbFrequency, + #else + (PF_CPU_GET_NB_FREQ) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, + #else + (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + F12GetNbPstateInfo, + #else + (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, + #endif + #if IS_NBCOF_INIT_NEEDED == TRUE + F12GetNbCofVidUpdate, + #else + (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, + #endif + #if GET_NB_IDD_MAX == TRUE + (PF_CPU_GET_NB_IDD_MAX) CommonAssert, + #else + (PF_CPU_GET_NB_IDD_MAX) CommonAssert, + #endif + #if AP_INITIAL_LAUNCH == TRUE + F12LaunchApCore, + #else + (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, + #endif + #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) + F12GetNumberOfPhysicalCores, + #else + (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, + #endif + #if GET_AP_MAILBOX_FROM_HW == TRUE + F12GetApMailboxFromHardware, + #else + (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, + #endif + #if SET_AP_CORE_NUMBER == TRUE + (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid, + #else + (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, + #endif + #if GET_AP_CORE_NUMBER == TRUE + F12GetApCoreNumber, + #else + (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, + #endif + #if TRANSFER_AP_CORE_NUMBER == TRUE + (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid, + #else + (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, + #endif + #if ID_POSITION_INITIAL_APICID == TRUE + F12CpuAmdCoreIdPositionInInitialApicId, + #else + (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, + #endif + #if SAVE_FEATURES == TRUE + (PF_CPU_SAVE_FEATURES) CommonVoid, + #else + (PF_CPU_SAVE_FEATURES) CommonAssert, + #endif + #if WRITE_FEATURES == TRUE + (PF_CPU_WRITE_FEATURES) CommonVoid, + #else + (PF_CPU_WRITE_FEATURES) CommonAssert, + #endif + #if SET_WARM_RESET_FLAG == TRUE + F12SetAgesaWarmResetFlag, + #else + (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, + #endif + #if GET_WARM_RESET_FLAG == TRUE + F12GetAgesaWarmResetFlag, + #else + (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, + #endif + #if BRAND_STRING1 == TRUE + GetF12BrandIdString1, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if BRAND_STRING2 == TRUE + GetF12BrandIdString2, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PATCHES == TRUE + GetF12LnMicroCodePatchesStruct, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE + GetF12LnMicrocodeEquivalenceTable, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_CACHE_INFO == TRUE + GetF12CacheInfo, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_SYSTEM_PM_TABLE == TRUE + GetF12SysPmTable, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_WHEA_INIT == TRUE + GetF12WheaInitData, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE + F12GetPlatformTypeSpecificInfo, + #else + (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, + #endif + #if IS_NB_PSTATE_ENABLED == TRUE + F12IsNbPstateEnabled, + #else + (PF_IS_NB_PSTATE_ENABLED) CommonAssert, + #endif + #if (BASE_FAMILY_HT_PCI == TRUE) + (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, + #else + (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, + #endif + #if (BASE_FAMILY_HT_PCI == TRUE) + (PF_SET_HT_PHY_REGISTER) CommonVoid, + #else + (PF_SET_HT_PHY_REGISTER) CommonAssert, + #endif + #if BASE_FAMILY_PCI == TRUE + (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, + #else + (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, + #endif + #if USES_REGISTER_TABLES == TRUE + (REGISTER_TABLE **) F12LnRegisterTables, + #else + NULL, + #endif + #if USES_REGISTER_TABLES == TRUE + (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12LnTableEntryTypeDescriptors, + #else + NULL, + #endif + #if MODEL_SPECIFIC_HT_PCI == TRUE + NULL, + #else + NULL, + #endif + NULL, + InitCacheDisabled, + #if AGESA_ENTRY_INIT_EARLY == TRUE + GetCommonEarlyInitOnCoreTable + #else + (PF_GET_EARLY_INIT_TABLE) CommonVoid + #endif + }; + + #define LN_SOCKETS 1 + #define LN_MODULES 1 + #define LN_RECOVERY_SOCKETS 1 + #define LN_RECOVERY_MODULES 1 + extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF12LnLogicalIdAndRev; + #define OPT_F12_LN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF12LnLogicalIdAndRev, + #ifndef ADVCFG_PLATFORM_SOCKETS + #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS + #else + #if ADVCFG_PLATFORM_SOCKETS < LN_SOCKETS + #undef ADVCFG_PLATFORM_SOCKETS + #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS + #endif + #endif + #ifndef ADVCFG_PLATFORM_MODULES + #define ADVCFG_PLATFORM_MODULES LN_MODULES + #else + #if ADVCFG_PLATFORM_MODULES < LN_MODULES + #undef ADVCFG_PLATFORM_MODULES + #define ADVCFG_PLATFORM_MODULES LN_MODULES + #endif + #endif + + #if GET_PATCHES == TRUE + #define F12_LN_UCODE_02 + #define F12_LN_UCODE_0E + #define F12_LN_UCODE_0F + + // If a patch is required for recovery mode to function properly, add a + // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in. + #if AGESA_ENTRY_INIT_EARLY == TRUE + extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000f; + #undef F12_LN_UCODE_0F + #define F12_LN_UCODE_0F &CpuF12MicrocodePatch0300000f, + #if OPTION_EARLY_SAMPLES == TRUE + extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000002; + extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000e; + #undef F12_LN_UCODE_02 + #define F12_LN_UCODE_02 &CpuF12MicrocodePatch03000002, + #undef F12_LN_UCODE_0E + #define F12_LN_UCODE_0E &CpuF12MicrocodePatch0300000e, + #endif + #endif + + CONST MICROCODE_PATCHES ROMDATA *CpuF12LnMicroCodePatchArray[] = + { + F12_LN_UCODE_0F + F12_LN_UCODE_0E + F12_LN_UCODE_02 + NULL + }; + + CONST UINT8 ROMDATA CpuF12LnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF12LnMicroCodePatchArray) / sizeof (CpuF12LnMicroCodePatchArray[0])) - 1); + #endif + + #if OPTION_EARLY_SAMPLES == TRUE + extern F_F12_ES_NB_PSTATE_INIT F12NbPstateInitEarlySampleHook; + extern F_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitEarlySampleHook; + + CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport = + { + #if AGESA_ENTRY_INIT_EARLY == TRUE + F12PowerPlaneInitEarlySampleHook, + #else + (PF_F12_ES_POWER_PLANE_INIT) CommonAssert, + #endif + #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) + F12NbPstateInitEarlySampleHook + #else + (PF_F12_ES_NB_PSTATE_INIT) CommonAssert + #endif + }; + #else + CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport = + { + #if AGESA_ENTRY_INIT_EARLY == TRUE + (PF_F12_ES_POWER_PLANE_INIT) CommonVoid, + #else + (PF_F12_ES_POWER_PLANE_INIT) CommonAssert, + #endif + #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) + (PF_F12_ES_NB_PSTATE_INIT) CommonVoid + #else + (PF_F12_ES_NB_PSTATE_INIT) CommonAssert + #endif + }; + #endif + + #define OPT_F12_LN_CPU {AMD_FAMILY_12_LN, &cpuF12LnServices}, + #else // OPTION_FAMILY12H_LN == TRUE + #define OPT_F12_LN_CPU + #define OPT_F12_LN_ID + #endif // OPTION_FAMILY12H_LN == TRUE +#else // defined (OPTION_FAMILY12H_LN) + #define OPT_F12_LN_CPU + #define OPT_F12_LN_ID +#endif // defined (OPTION_FAMILY12H_LN) + + +/* + * Install unknown family 12h support + */ + +#if USES_REGISTER_TABLES == TRUE + CONST REGISTER_TABLE ROMDATA *F12UnknownRegisterTables[] = + { + #if BASE_FAMILY_PCI == TRUE + &F12PciRegisterTable, + #endif + #if BASE_FAMILY_PCI == TRUE + &F12PerCorePciRegisterTable, + #endif + #if BASE_FAMILY_MSR == TRUE + &F12MsrRegisterTable, + #endif + // the end. + NULL + }; +#endif + +#if USES_REGISTER_TABLES == TRUE + CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12UnknownTableEntryTypeDescriptors[] = + { + {MsrRegister, SetRegisterForMsrEntry}, + {PciRegister, SetRegisterForPciEntry}, + {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, + {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid}, + // End + {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} + }; +#endif + +CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12UnknownServices = +{ + 0, + #if DISABLE_PSTATE == TRUE + F12DisablePstate, + #else + (PF_CPU_DISABLE_PSTATE) CommonAssert, + #endif + #if TRANSITION_PSTATE == TRUE + F12TransitionPstate, + #else + (PF_CPU_TRANSITION_PSTATE) CommonAssert, + #endif + #if PROC_IDD_MAX == TRUE + F12GetProcIddMax, + #else + (PF_CPU_GET_IDD_MAX) CommonAssert, + #endif + #if GET_TSC_RATE == TRUE + F12GetTscRate, + #else + (PF_CPU_GET_TSC_RATE) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + F12GetCurrentNbFrequency, + #else + (PF_CPU_GET_NB_FREQ) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, + #else + (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + F12GetNbPstateInfo, + #else + (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, + #endif + #if IS_NBCOF_INIT_NEEDED == TRUE + F12GetNbCofVidUpdate, + #else + (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, + #endif + #if GET_NB_IDD_MAX == TRUE + (PF_CPU_GET_NB_IDD_MAX) CommonAssert, + #else + (PF_CPU_GET_NB_IDD_MAX) CommonAssert, + #endif + #if AP_INITIAL_LAUNCH == TRUE + F12LaunchApCore, + #else + (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, + #endif + #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) + F12GetNumberOfPhysicalCores, + #else + (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, + #endif + #if GET_AP_MAILBOX_FROM_HW == TRUE + F12GetApMailboxFromHardware, + #else + (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, + #endif + #if SET_AP_CORE_NUMBER == TRUE + (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid, + #else + (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, + #endif + #if GET_AP_CORE_NUMBER == TRUE + F12GetApCoreNumber, + #else + (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, + #endif + #if TRANSFER_AP_CORE_NUMBER == TRUE + (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid, + #else + (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, + #endif + #if ID_POSITION_INITIAL_APICID == TRUE + F12CpuAmdCoreIdPositionInInitialApicId, + #else + (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, + #endif + #if SAVE_FEATURES == TRUE + (PF_CPU_SAVE_FEATURES) CommonVoid, + #else + (PF_CPU_SAVE_FEATURES) CommonAssert, + #endif + #if WRITE_FEATURES == TRUE + (PF_CPU_WRITE_FEATURES) CommonVoid, + #else + (PF_CPU_WRITE_FEATURES) CommonAssert, + #endif + #if SET_WARM_RESET_FLAG == TRUE + F12SetAgesaWarmResetFlag, + #else + (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, + #endif + #if GET_WARM_RESET_FLAG == TRUE + F12GetAgesaWarmResetFlag, + #else + (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, + #endif + #if BRAND_STRING1 == TRUE + GetF12BrandIdString1, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if BRAND_STRING2 == TRUE + GetF12BrandIdString2, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PATCHES == TRUE + GetEmptyArray, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE + GetEmptyArray, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_CACHE_INFO == TRUE + GetF12CacheInfo, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_SYSTEM_PM_TABLE == TRUE + GetF12SysPmTable, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_WHEA_INIT == TRUE + GetF12WheaInitData, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE + F12GetPlatformTypeSpecificInfo, + #else + (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, + #endif + #if IS_NB_PSTATE_ENABLED == TRUE + F12IsNbPstateEnabled, + #else + (PF_IS_NB_PSTATE_ENABLED) CommonAssert, + #endif + #if (BASE_FAMILY_HT_PCI == TRUE) + (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, + #else + (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonAssert, + #endif + #if (BASE_FAMILY_HT_PCI == TRUE) + (PF_SET_HT_PHY_REGISTER) CommonVoid, + #else + (PF_SET_HT_PHY_REGISTER) CommonAssert, + #endif + #if BASE_FAMILY_PCI == TRUE + (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, + #else + (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert, + #endif + #if USES_REGISTER_TABLES == TRUE + (REGISTER_TABLE **) F12UnknownRegisterTables, + #else + NULL, + #endif + #if USES_REGISTER_TABLES == TRUE + (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12UnknownTableEntryTypeDescriptors, + #else + NULL, + #endif + #if MODEL_SPECIFIC_HT_PCI == TRUE + NULL, + #else + NULL, + #endif + NULL, + InitCacheDisabled, + #if AGESA_ENTRY_INIT_EARLY == TRUE + GetCommonEarlyInitOnCoreTable + #else + (PF_GET_EARLY_INIT_TABLE) CommonVoid + #endif +}; + + // Family 12h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate. +#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull) + #undef FAMILY_MMIO_BASE_MASK + #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull) +#endif + +#undef OPT_F12_ID_TABLE +#define OPT_F12_ID_TABLE {0x12ul, {AMD_FAMILY_12, AMD_F12_UNKNOWN}, F12LogicalIdTable, (sizeof (F12LogicalIdTable) / sizeof (F12LogicalIdTable[0]))}, +#define OPT_F12_UNKNOWN_CPU {AMD_FAMILY_12, &cpuF12UnknownServices}, + +#undef OPT_F12_TABLE +#define OPT_F12_TABLE OPT_F12_LN_CPU OPT_F12_UNKNOWN_CPU + +#if OPTION_FS1_SOCKET_SUPPORT == TRUE + extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFs1; + extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFs1; + #define F12_FS1_BRANDSTRING1 &F12LnBrandIdString1ArrayFs1, + #define F12_FS1_BRANDSTRING2 &F12LnBrandIdString2ArrayFs1, +#else + #define F12_FS1_BRANDSTRING1 + #define F12_FS1_BRANDSTRING2 +#endif +#if OPTION_FM1_SOCKET_SUPPORT == TRUE + extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFm1; + extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFm1; + #define F12_FM1_BRANDSTRING1 &F12LnBrandIdString1ArrayFm1, + #define F12_FM1_BRANDSTRING2 &F12LnBrandIdString2ArrayFm1, +#else + #define F12_FM1_BRANDSTRING1 + #define F12_FM1_BRANDSTRING2 +#endif +#if OPTION_FP1_SOCKET_SUPPORT == TRUE + #define F12_FP1_BRANDSTRING1 NULL, + #define F12_FP1_BRANDSTRING2 NULL, +#else + #define F12_FP1_BRANDSTRING1 + #define F12_FP1_BRANDSTRING2 +#endif + +#if BRAND_STRING1 == TRUE + CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString1Tables[] = + { + F12_FS1_BRANDSTRING1 + F12_FM1_BRANDSTRING1 + F12_FP1_BRANDSTRING1 + }; + + CONST UINT8 F12BrandIdString1TableCount = (sizeof (F12BrandIdString1Tables) / sizeof (F12BrandIdString1Tables[0])); +#endif + +#if BRAND_STRING2 == TRUE + CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString2Tables[] = + { + F12_FS1_BRANDSTRING2 + F12_FM1_BRANDSTRING2 + F12_FP1_BRANDSTRING2 + }; + + CONST UINT8 F12BrandIdString2TableCount = (sizeof (F12BrandIdString2Tables) / sizeof (F12BrandIdString2Tables[0])); +#endif + +CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F12LogicalIdTable[] = +{ + OPT_F12_LN_ID +}; + +#endif // _OPTION_FAMILY_12H_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionFchInstall.h new file mode 100644 index 0000000000..f1799f6507 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionFchInstall.h @@ -0,0 +1,928 @@ +/********************************************************************************* +; +* Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;*********************************************************************************/ + +#ifndef _OPTION_FCH_INSTALL_H_ +#define _OPTION_FCH_INSTALL_H_ + +#include "AmdFch.h" + +#ifndef FCH_SUPPORT + #define FCH_SUPPORT FALSE +#endif + + +/* ACPI block register offset definitions */ +#define PM1_STATUS_OFFSET 0x00 +#define PM1_ENABLE_OFFSET 0x02 +#define PM_CONTROL_OFFSET 0x04 +#define PM_TIMER_OFFSET 0x08 +#define CPU_CONTROL_OFFSET 0x10 +#define EVENT_STATUS_OFFSET 0x20 +#define EVENT_ENABLE_OFFSET 0x24 + + +#if FCH_SUPPORT == TRUE + /* + * FCH subfunctions + */ + #ifdef AGESA_ENTRY_INIT_RESET + #if AGESA_ENTRY_INIT_RESET == TRUE + extern FCH_TASK_ENTRY FchInitResetHwAcpiP; + extern FCH_TASK_ENTRY FchInitResetHwAcpi; + extern FCH_TASK_ENTRY FchInitResetAb; + extern FCH_TASK_ENTRY FchInitResetSpi; + extern FCH_TASK_ENTRY FchInitResetGec; + extern FCH_TASK_ENTRY FchInitResetSata; + extern FCH_TASK_ENTRY FchInitResetLpc; + extern FCH_TASK_ENTRY FchInitResetPcib; + extern FCH_TASK_ENTRY FchInitResetPcie; + extern FCH_TASK_ENTRY FchInitResetGpp; + extern FCH_TASK_ENTRY FchInitResetUsb; + extern FCH_TASK_ENTRY FchInitResetEhci; + extern FCH_TASK_ENTRY FchInitResetOhci; + extern FCH_TASK_ENTRY FchInitResetXhci; + extern FCH_TASK_ENTRY FchInitResetImc; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_ENV + #if AGESA_ENTRY_INIT_ENV == TRUE + extern FCH_TASK_ENTRY FchInitEnvUsbXhci; + extern FCH_TASK_ENTRY FchInitEnvUsbOhci; + extern FCH_TASK_ENTRY FchInitEnvUsbEhci; + extern FCH_TASK_ENTRY FchInitEnvUsb; + extern FCH_TASK_ENTRY FchInitEnvAb; + extern FCH_TASK_ENTRY FchInitEnvGpp; + extern FCH_TASK_ENTRY FchInitEnvPcie; + extern FCH_TASK_ENTRY FchInitEnvPcib; + extern FCH_TASK_ENTRY FchInitEnvHwAcpiP; + extern FCH_TASK_ENTRY FchInitEnvHwAcpi; + extern FCH_TASK_ENTRY FchInitEnvAbSpecial; + extern FCH_TASK_ENTRY FchInitEnvSpi; + extern FCH_TASK_ENTRY FchInitEnvGec; + extern FCH_TASK_ENTRY FchInitEnvSata; + extern FCH_TASK_ENTRY FchInitEnvIde; + extern FCH_TASK_ENTRY FchInitEnvSd; + extern FCH_TASK_ENTRY FchInitEnvIr; + extern FCH_TASK_ENTRY FchInitEnvAzalia; + extern FCH_TASK_ENTRY FchInitEnvHwm; + extern FCH_TASK_ENTRY FchInitEnvImc; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_MID + #if AGESA_ENTRY_INIT_MID == TRUE + extern FCH_TASK_ENTRY FchInitMidHwm; + extern FCH_TASK_ENTRY FchInitMidAzalia; + extern FCH_TASK_ENTRY FchInitMidGec; + extern FCH_TASK_ENTRY FchInitMidSata; + extern FCH_TASK_ENTRY FchInitMidIde; + extern FCH_TASK_ENTRY FchInitMidAb; + extern FCH_TASK_ENTRY FchInitMidUsb; + extern FCH_TASK_ENTRY FchInitMidUsbEhci; + extern FCH_TASK_ENTRY FchInitMidUsbOhci; + extern FCH_TASK_ENTRY FchInitMidUsbXhci; + extern FCH_TASK_ENTRY FchInitMidImc; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_LATE + #if AGESA_ENTRY_INIT_LATE == TRUE + extern FCH_TASK_ENTRY FchInitLateHwAcpi; + extern FCH_TASK_ENTRY FchInitLateSpi; + extern FCH_TASK_ENTRY FchInitLateGec; + extern FCH_TASK_ENTRY FchInitLateSata; + extern FCH_TASK_ENTRY FchInitLateIde; + extern FCH_TASK_ENTRY FchInitLatePcib; + extern FCH_TASK_ENTRY FchInitLateAb; + extern FCH_TASK_ENTRY FchInitLatePcie; + extern FCH_TASK_ENTRY FchInitLateGpp; + extern FCH_TASK_ENTRY FchInitLateUsb; + extern FCH_TASK_ENTRY FchInitLateUsbEhci; + extern FCH_TASK_ENTRY FchInitLateUsbOhci; + extern FCH_TASK_ENTRY FchInitLateUsbXhci; + extern FCH_TASK_ENTRY FchInitLateImc; + extern FCH_TASK_ENTRY FchInitLateAzalia; + extern FCH_TASK_ENTRY FchInitLateHwm; + #endif + #endif + + extern FCH_TASK_ENTRY FchTaskDummy; + /* FCH Interface entries */ + extern FCH_INIT CommonFchInitStub; + + /* FCH Interface entries */ + #ifdef AGESA_ENTRY_INIT_RESET + #if AGESA_ENTRY_INIT_RESET == TRUE + extern FCH_INIT FchInitReset; + extern FCH_INIT FchResetConstructor; + + #define FP_FCH_INIT_RESET &FchInitReset + #define FP_FCH_INIT_RESET_CONSTRUCT &FchResetConstructor + #else + #define FP_FCH_INIT_RESET &CommonFchInitStub + #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_ENV + #if AGESA_ENTRY_INIT_ENV == TRUE + extern FCH_INIT FchInitEnv; + extern FCH_INIT FchEnvConstructor; + + #define FP_FCH_INIT_ENV &FchInitEnv + #define FP_FCH_INIT_ENV_CONSTRUCT &FchEnvConstructor + #else + #define FP_FCH_INIT_ENV &CommonFchInitStub + #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_MID + #if AGESA_ENTRY_INIT_MID == TRUE + extern FCH_INIT FchInitMid; + extern FCH_INIT FchMidConstructor; + + #define FP_FCH_INIT_MID &FchInitMid + #define FP_FCH_INIT_MID_CONSTRUCT &FchMidConstructor + #else + #define FP_FCH_INIT_MID &CommonFchInitStub + #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_LATE + #if AGESA_ENTRY_INIT_LATE == TRUE + extern FCH_INIT FchInitLate; + extern FCH_INIT FchLateConstructor; + + #define FP_FCH_INIT_LATE &FchInitLate + #define FP_FCH_INIT_LATE_CONSTRUCT &FchLateConstructor + #else + #define FP_FCH_INIT_LATE &CommonFchInitStub + #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub + #endif + #endif + + /* FCH subcomponent build options */ + #undef FCH_NO_HWACPI_SUPPORT + #undef FCH_NO_AB_SUPPORT + #undef FCH_NO_SPI_SUPPORT + #undef FCH_NO_GEC_SUPPORT + #undef FCH_NO_SATA_SUPPORT + #undef FCH_NO_IDE_SUPPORT + #undef FCH_NO_LPC_SUPPORT + #undef FCH_NO_PCIB_SUPPORT + #undef FCH_NO_PCIE_SUPPORT + #undef FCH_NO_GPP_SUPPORT + #undef FCH_NO_USB_SUPPORT + #undef FCH_NO_EHCI_SUPPORT + #undef FCH_NO_OHCI_SUPPORT + #undef FCH_NO_XHCI_SUPPORT + #undef FCH_NO_IMC_SUPPORT + #undef FCH_NO_SD_SUPPORT + #undef FCH_NO_IR_SUPPORT + #undef FCH_NO_AZALIA_SUPPORT + #undef FCH_NO_HWM_SUPPORT + + // Following are determined by silicon characteristics + #if (OPTION_FAMILY14H_KR == TRUE) + #define FCH_NO_GPP_SUPPORT TRUE + #define FCH_NO_PCIB_SUPPORT TRUE + #define FCH_NO_PCIE_SUPPORT TRUE + + #else + #if (OPTION_FAMILY15H_TN == TRUE) + //#define FCH_NO_GEC_SUPPORT TRUE + #else + #error FCH_SUPPORT: No chip type selected. + #endif + #endif + + + // + // Installable blocks depending on build switches + // + #ifndef FCH_NO_HWACPI_SUPPORT + #define BLOCK_HWACPI_SIZE sizeof (FCH_ACPI) + #define InstallFchInitResetHwAcpiP &FchInitResetHwAcpiP + #define InstallFchInitResetHwAcpi &FchInitResetHwAcpi + #define InstallFchInitEnvHwAcpiP &FchInitEnvHwAcpiP + #define InstallFchInitEnvHwAcpi &FchInitEnvHwAcpi + #define InstallFchInitMidHwAcpi &FchTaskDummy + #define InstallFchInitLateHwAcpi &FchInitLateHwAcpi + #else + #define BLOCK_HWACPI_SIZE 0 + #define InstallFchInitResetHwAcpiP &FchTaskDummy + #define InstallFchInitResetHwAcpi &FchTaskDummy + #define InstallFchInitEnvHwAcpi &FchTaskDummy + #define InstallFchInitMidHwAcpi &FchTaskDummy + #define InstallFchInitLateHwAcpi &FchTaskDummy + #endif + + #ifndef FCH_NO_AB_SUPPORT + #define BLOCK_AB_SIZE sizeof (FCH_AB) + #define InstallFchInitResetAb &FchInitResetAb + #define InstallFchInitEnvAb &FchInitEnvAb + #define InstallFchInitEnvAbS &FchInitEnvAbSpecial + #define InstallFchInitMidAb &FchInitMidAb + #define InstallFchInitLateAb &FchInitLateAb + #else + #define BLOCK_AB_SIZE 0 + #define InstallFchInitResetAb &FchTaskDummy + #define InstallFchInitEnvAb &FchTaskDummy + #define InstallFchInitEnvAbS &FchTaskDummy + #define InstallFchInitMidAb &FchTaskDummy + #define InstallFchInitLateAb &FchTaskDummy + #endif + + #ifndef FCH_NO_SPI_SUPPORT + #define BLOCK_SPI_SIZE sizeof (FCH_SPI) + #define InstallFchInitResetSpi &FchInitResetSpi + #define InstallFchInitEnvSpi &FchInitEnvSpi + #define InstallFchInitMidSpi &FchTaskDummy + #define InstallFchInitLateSpi &FchInitLateSpi + #else + #define BLOCK_SPI_SIZE 0 + #define InstallFchInitResetSpi &FchTaskDummy + #define InstallFchInitEnvSpi &FchTaskDummy + #define InstallFchInitMidSpi &FchTaskDummy + #define InstallFchInitLateSpi &FchTaskDummy + #endif + + #ifndef FCH_NO_GEC_SUPPORT + #define BLOCK_GEC_SIZE sizeof (FCH_GEC) + #define InstallFchInitResetGec &FchInitResetGec + #define InstallFchInitEnvGec &FchInitEnvGec + #define InstallFchInitMidGec &FchInitMidGec + #define InstallFchInitLateGec &FchInitLateGec + #else + #define BLOCK_GEC_SIZE 0 + #define InstallFchInitResetGec &FchTaskDummy + #define InstallFchInitEnvGec &FchTaskDummy + #define InstallFchInitMidGec &FchTaskDummy + #define InstallFchInitLateGec &FchTaskDummy + #endif + + #ifndef FCH_NO_SATA_SUPPORT + #define BLOCK_SATA_SIZE sizeof (FCH_SATA) + #define InstallFchInitResetSata &FchInitResetSata + #define InstallFchInitEnvSata &FchInitEnvSata + #define InstallFchInitMidSata &FchInitMidSata + #define InstallFchInitLateSata &FchInitLateSata + #else + #define BLOCK_SATA_SIZE 0 + #define InstallFchInitResetSata &FchTaskDummy + #define InstallFchInitEnvSata &FchTaskDummy + #define InstallFchInitMidSata &FchTaskDummy + #define InstallFchInitLateSata &FchTaskDummy + #endif + + #ifndef FCH_NO_IDE_SUPPORT + #define BLOCK_IDE_SIZE sizeof (FCH_IDE) + #define InstallFchInitResetIde &FchTaskDummy + #define InstallFchInitEnvIde &FchInitEnvIde + #define InstallFchInitMidIde &FchInitMidIde + #define InstallFchInitLateIde &FchInitLateIde + #else + #define BLOCK_IDE_SIZE 0 + #define InstallFchInitResetIde &FchTaskDummy + #define InstallFchInitEnvIde &FchTaskDummy + #define InstallFchInitMidIde &FchTaskDummy + #define InstallFchInitLateIde &FchTaskDummy + #endif + + #ifndef FCH_NO_LPC_SUPPORT + #define BLOCK_LPC_SIZE sizeof (FCH_LPC) + #define InstallFchInitResetLpc &FchInitResetLpc + #define InstallFchInitEnvLpc &FchTaskDummy + #define InstallFchInitMidLpc &FchTaskDummy + #define InstallFchInitLateLpc &FchTaskDummy + #else + #define BLOCK_LPC_SIZE 0 + #define InstallFchInitResetLpc &FchTaskDummy + #define InstallFchInitEnvLpc &FchTaskDummy + #define InstallFchInitMidLpc &FchTaskDummy + #define InstallFchInitLateLpc &FchTaskDummy + #endif + + #ifndef FCH_NO_PCIB_SUPPORT + #define BLOCK_PCIB_SIZE sizeof (FCH_PCIB) + #define InstallFchInitResetPcib &FchInitResetPcib + #define InstallFchInitEnvPcib &FchInitEnvPcib + #define InstallFchInitMidPcib &FchTaskDummy + #define InstallFchInitLatePcib &FchInitLatePcib + #else + #define BLOCK_PCIB_SIZE 0 + #define InstallFchInitResetPcib &FchTaskDummy + #define InstallFchInitEnvPcib &FchTaskDummy + #define InstallFchInitMidPcib &FchTaskDummy + #define InstallFchInitLatePcib &FchTaskDummy + #endif + + #ifndef FCH_NO_PCIE_SUPPORT + #define InstallFchInitResetPcie &FchInitResetPcie + #define InstallFchInitEnvPcie &FchInitEnvPcie + #define InstallFchInitMidPcie &FchTaskDummy + #define InstallFchInitLatePcie &FchInitLatePcie + #else + #define InstallFchInitResetPcie &FchTaskDummy + #define InstallFchInitEnvPcie &FchTaskDummy + #define InstallFchInitMidPcie &FchTaskDummy + #define InstallFchInitLatePcie &FchTaskDummy + #endif + + #ifndef FCH_NO_GPP_SUPPORT + #define BLOCK_GPP_SIZE sizeof (FCH_GPP) + #define InstallFchInitResetGpp &FchInitResetGpp + #define InstallFchInitEnvGpp &FchInitEnvGpp + #define InstallFchInitMidGpp &FchTaskDummy + #define InstallFchInitLateGpp &FchInitLateGpp + #else + #define BLOCK_GPP_SIZE 0 + #define InstallFchInitResetGpp &FchTaskDummy + #define InstallFchInitEnvGpp &FchTaskDummy + #define InstallFchInitMidGpp &FchTaskDummy + #define InstallFchInitLateGpp &FchTaskDummy + #endif + + #ifndef FCH_NO_USB_SUPPORT + #define BLOCK_USB_SIZE sizeof (FCH_USB) + #define InstallFchInitResetUsb &FchInitResetUsb + #define InstallFchInitEnvUsb &FchInitEnvUsb + #define InstallFchInitMidUsb &FchInitMidUsb + #define InstallFchInitLateUsb &FchInitLateUsb + #else + #define BLOCK_USB_SIZE 0 + #define InstallFchInitResetUsb &FchTaskDummy + #define InstallFchInitEnvUsb &FchTaskDummy + #define InstallFchInitMidUsb &FchTaskDummy + #define InstallFchInitLateUsb &FchTaskDummy + #endif + + #ifndef FCH_NO_EHCI_SUPPORT + #define InstallFchInitResetUsbEhci &FchInitResetEhci + #define InstallFchInitEnvUsbEhci &FchInitEnvUsbEhci + #define InstallFchInitMidUsbEhci &FchInitMidUsbEhci + #define InstallFchInitLateUsbEhci &FchInitLateUsbEhci + #else + #define InstallFchInitResetUsbEhci &FchTaskDummy + #define InstallFchInitEnvUsbEhci &FchTaskDummy + #define InstallFchInitMidUsbEhci &FchTaskDummy + #define InstallFchInitLateUsbEhci &FchTaskDummy + #endif + + #ifndef FCH_NO_OHCI_SUPPORT + #define InstallFchInitResetUsbOhci &FchInitResetOhci + #define InstallFchInitEnvUsbOhci &FchInitEnvUsbOhci + #define InstallFchInitMidUsbOhci &FchInitMidUsbOhci + #define InstallFchInitLateUsbOhci &FchInitLateUsbOhci + #else + #define InstallFchInitResetUsbOhci &FchTaskDummy + #define InstallFchInitEnvUsbOhci &FchTaskDummy + #define InstallFchInitMidUsbOhci &FchTaskDummy + #define InstallFchInitLateUsbOhci &FchTaskDummy + #endif + + #ifndef FCH_NO_XHCI_SUPPORT + #define InstallFchInitResetUsbXhci &FchInitResetXhci + #define InstallFchInitEnvUsbXhci &FchInitEnvUsbXhci + #define InstallFchInitMidUsbXhci &FchInitMidUsbXhci + #define InstallFchInitLateUsbXhci &FchInitLateUsbXhci + #else + #define InstallFchInitResetUsbXhci &FchTaskDummy + #define InstallFchInitEnvUsbXhci &FchTaskDummy + #define InstallFchInitMidUsbXhci &FchTaskDummy + #define InstallFchInitLateUsbXhci &FchTaskDummy + #endif + + #ifndef FCH_NO_IMC_SUPPORT + #define BLOCK_IMC_SIZE sizeof (FCH_IMC) + #define InstallFchInitResetImc &FchInitResetImc + #define InstallFchInitEnvImc &FchInitEnvImc + #define InstallFchInitMidImc &FchInitMidImc + #define InstallFchInitLateImc &FchInitLateImc + #else + #define BLOCK_IMC_SIZE 0 + #define InstallFchInitResetImc &FchTaskDummy + #define InstallFchInitEnvImc &FchTaskDummy + #define InstallFchInitMidImc &FchTaskDummy + #define InstallFchInitLateImc &FchTaskDummy + #endif + + + #ifndef FCH_NO_SD_SUPPORT + #define BLOCK_SD_SIZE sizeof (FCH_SD) + #define InstallFchInitResetSd &FchTaskDummy + #define InstallFchInitEnvSd &FchInitEnvSd + #define InstallFchInitMidSd &FchTaskDummy + #define InstallFchInitLateSd &FchTaskDummy + #else + #define BLOCK_SD_SIZE 0 + #define InstallFchInitResetSd &FchTaskDummy + #define InstallFchInitEnvSd &FchTaskDummy + #define InstallFchInitMidSd &FchTaskDummy + #define InstallFchInitLateSd &FchTaskDummy + #endif + + #ifndef FCH_NO_IR_SUPPORT + #define BLOCK_IR_SIZE sizeof (FCH_IR) + #define InstallFchInitResetIr &FchTaskDummy + #define InstallFchInitEnvIr &FchInitEnvIr + #define InstallFchInitMidIr &FchTaskDummy + #define InstallFchInitLateIr &FchTaskDummy + #else + #define BLOCK_IR_SIZE 0 + #define InstallFchInitResetIr &FchTaskDummy + #define InstallFchInitEnvIr &FchTaskDummy + #define InstallFchInitMidIr &FchTaskDummy + #define InstallFchInitLateIr &FchTaskDummy + #endif + + #ifndef FCH_NO_AZALIA_SUPPORT + #define BLOCK_AZALIA_SIZE sizeof (FCH_AZALIA) + #define InstallFchInitResetAzalia &FchTaskDummy + #define InstallFchInitEnvAzalia &FchInitEnvAzalia + #define InstallFchInitMidAzalia &FchInitMidAzalia + #define InstallFchInitLateAzalia &FchInitLateAzalia + #else + #define BLOCK_AZALIA_SIZE 0 + #define InstallFchInitResetAzalia &FchTaskDummy + #define InstallFchInitEnvAzalia &FchTaskDummy + #define InstallFchInitMidAzalia &FchTaskDummy + #define InstallFchInitLateAzalia &FchTaskDummy + #endif + + #ifndef FCH_NO_HWM_SUPPORT + #define BLOCK_HWM_SIZE sizeof (FCH_HWM) + #define InstallFchInitResetHwm &FchTaskDummy + #define InstallFchInitEnvHwm &FchInitEnvHwm + #define InstallFchInitMidHwm &FchInitMidHwm + #define InstallFchInitLateHwm &FchInitLateHwm + #else + #define InstallFchInitResetHwm &FchTaskDummy + #define InstallFchInitEnvHwm &FchTaskDummy + #define InstallFchInitMidHwm &FchTaskDummy + #define InstallFchInitLateHwm &FchTaskDummy + #endif + + + #define BLOCK_SMBUS_SIZE sizeof (FCH_SMBUS) + #define BLOCK_HPET_SIZE sizeof (FCH_HPET) + #define BLOCK_GCPU_SIZE sizeof (FCH_GCPU) + #define BLOCK_SDB_SIZE sizeof (FCH_SERIALDB) + #define BLOCK_MISC_SIZE sizeof (FCH_MISC) + + + // Optionally declare OEM hooks after each phase + #ifndef FCH_INIT_RESET_HOOK + #define InstallFchInitResetHook FchTaskDummy + #else + #define InstallFchInitResetHook OemFchInitResetHook + #endif + + + // + // Define FCH build time options and configurations + // + #ifdef BLDCFG_SMBUS0_BASE_ADDRESS + #define CFG_SMBUS0_BASE_ADDRESS BLDCFG_SMBUS0_BASE_ADDRESS + #else + #define CFG_SMBUS0_BASE_ADDRESS DFLT_SMBUS0_BASE_ADDRESS + #endif + + #ifdef BLDCFG_SMBUS1_BASE_ADDRESS + #define CFG_SMBUS1_BASE_ADDRESS BLDCFG_SMBUS1_BASE_ADDRESS + #else + #define CFG_SMBUS1_BASE_ADDRESS DFLT_SMBUS1_BASE_ADDRESS + #endif + + #ifdef BLDCFG_SIO_PME_BASE_ADDRESS + #define CFG_SIO_PME_BASE_ADDRESS BLDCFG_SIO_PME_BASE_ADDRESS + #else + #define CFG_SIO_PME_BASE_ADDRESS DFLT_SIO_PME_BASE_ADDRESS + #endif + + #ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS + #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS + #else + #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS + #endif + #ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS + #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS + #else + #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS + #endif + #ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS + #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS + #else + #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS DFLT_ACPI_PM_TMR_BLOCK_ADDRESS + #endif + #ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS + #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS + #else + #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS + #endif + #ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS + #define CFG_ACPI_GPE0_BLOCK_ADDRESS BLDCFG_ACPI_GPE0_BLOCK_ADDRESS + #else + #define CFG_ACPI_GPE0_BLOCK_ADDRESS DFLT_ACPI_GPE0_BLOCK_ADDRESS + #endif + + + #ifdef BLDCFG_WATCHDOG_TIMER_BASE + #define CFG_WATCHDOG_TIMER_BASE BLDCFG_WATCHDOG_TIMER_BASE + #else + #define CFG_WATCHDOG_TIMER_BASE DFLT_WATCHDOG_TIMER_BASE_ADDRESS + #endif + + #ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS + #define CFG_ACPI_PMA_CNTBLK_ADDRESS BLDCFG_ACPI_PMA_BLK_ADDRESS + #else + #define CFG_ACPI_PMA_CNTBLK_ADDRESS DFLT_ACPI_PMA_CNT_BLK_ADDRESS + #endif + + #ifdef BLDCFG_SMI_CMD_PORT_ADDRESS + #define CFG_SMI_CMD_PORT_ADDRESS BLDCFG_SMI_CMD_PORT_ADDRESS + #else + #define CFG_SMI_CMD_PORT_ADDRESS DFLT_SMI_CMD_PORT + #endif + + #ifdef BLDCFG_ROM_BASE_ADDRESS + #define CFG_SPI_ROM_BASE_ADDRESS BLDCFG_ROM_BASE_ADDRESS + #else + #define CFG_SPI_ROM_BASE_ADDRESS DFLT_SPI_BASE_ADDRESS + #endif + + #ifdef BLDCFG_GEC_SHADOW_ROM_BASE + #define CFG_GEC_SHADOW_ROM_BASE BLDCFG_GEC_SHADOW_ROM_BASE + #else + #define CFG_GEC_SHADOW_ROM_BASE DFLT_GEC_BASE_ADDRESS + #endif + + #ifdef BLDCFG_HPET_BASE_ADDRESS + #define CFG_HPET_BASE_ADDRESS BLDCFG_HPET_BASE_ADDRESS + #else + #define CFG_HPET_BASE_ADDRESS DFLT_HPET_BASE_ADDRESS + #endif + + #ifdef BLDCFG_AZALIA_SSID + #define CFG_AZALIA_SSID BLDCFG_AZALIA_SSID + #else + #define CFG_AZALIA_SSID DFLT_AZALIA_SSID + #endif + + #ifdef BLDCFG_SMBUS_SSID + #define CFG_SMBUS_SSID BLDCFG_SMBUS_SSID + #else + #define CFG_SMBUS_SSID DFLT_SMBUS_SSID + #endif + + #ifdef BLDCFG_IDE_SSID + #define CFG_IDE_SSID BLDCFG_IDE_SSID + #else + #define CFG_IDE_SSID DFLT_IDE_SSID + #endif + + #ifdef BLDCFG_SATA_AHCI_SSID + #define CFG_SATA_AHCI_SSID BLDCFG_SATA_AHCI_SSID + #else + #define CFG_SATA_AHCI_SSID DFLT_SATA_AHCI_SSID + #endif + + #ifdef BLDCFG_SATA_IDE_SSID + #define CFG_SATA_IDE_SSID BLDCFG_SATA_IDE_SSID + #else + #define CFG_SATA_IDE_SSID DFLT_SATA_IDE_SSID + #endif + + #ifdef BLDCFG_SATA_RAID5_SSID + #define CFG_SATA_RAID5_SSID BLDCFG_SATA_RAID5_SSID + #else + #define CFG_SATA_RAID5_SSID DFLT_SATA_RAID5_SSID + #endif + + #ifdef BLDCFG_SATA_RAID_SSID + #define CFG_SATA_RAID_SSID BLDCFG_SATA_RAID_SSID + #else + #define CFG_SATA_RAID_SSID DFLT_SATA_RAID_SSID + #endif + + #ifdef BLDCFG_EHCI_SSID + #define CFG_EHCI_SSID BLDCFG_EHCI_SSID + #else + #define CFG_EHCI_SSID DFLT_EHCI_SSID + #endif + + #ifdef BLDCFG_OHCI_SSID + #define CFG_OHCI_SSID BLDCFG_OHCI_SSID + #else + #define CFG_OHCI_SSID DFLT_OHCI_SSID + #endif + + #ifdef BLDCFG_LPC_SSID + #define CFG_LPC_SSID BLDCFG_LPC_SSID + #else + #define CFG_LPC_SSID DFLT_LPC_SSID + #endif + + #ifdef BLDCFG_FCH_GPP_LINK_CONFIG + #define CFG_FCH_GPP_LINK_CONFIG BLDCFG_FCH_GPP_LINK_CONFIG + #else + #define CFG_FCH_GPP_LINK_CONFIG DFLT_FCH_GPP_LINK_CONFIG + #endif + + #ifdef BLDCFG_FCH_GPP_PORT0_PRESENT + #define CFG_FCH_GPP_PORT0_PRESENT BLDCFG_FCH_GPP_PORT0_PRESENT + #else + #define CFG_FCH_GPP_PORT0_PRESENT DFLT_FCH_GPP_PORT0_PRESENT + #endif + + #ifdef BLDCFG_FCH_GPP_PORT1_PRESENT + #define CFG_FCH_GPP_PORT1_PRESENT BLDCFG_FCH_GPP_PORT1_PRESENT + #else + #define CFG_FCH_GPP_PORT1_PRESENT DFLT_FCH_GPP_PORT1_PRESENT + #endif + + #ifdef BLDCFG_FCH_GPP_PORT2_PRESENT + #define CFG_FCH_GPP_PORT2_PRESENT BLDCFG_FCH_GPP_PORT2_PRESENT + #else + #define CFG_FCH_GPP_PORT2_PRESENT DFLT_FCH_GPP_PORT2_PRESENT + #endif + + #ifdef BLDCFG_FCH_GPP_PORT3_PRESENT + #define CFG_FCH_GPP_PORT3_PRESENT BLDCFG_FCH_GPP_PORT3_PRESENT + #else + #define CFG_FCH_GPP_PORT3_PRESENT DFLT_FCH_GPP_PORT3_PRESENT + #endif + + #ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG + #define CFG_FCH_GPP_PORT0_HOTPLUG BLDCFG_FCH_GPP_PORT0_HOTPLUG + #else + #define CFG_FCH_GPP_PORT0_HOTPLUG DFLT_FCH_GPP_PORT0_HOTPLUG + #endif + + #ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG + #define CFG_FCH_GPP_PORT1_HOTPLUG BLDCFG_FCH_GPP_PORT1_HOTPLUG + #else + #define CFG_FCH_GPP_PORT1_HOTPLUG DFLT_FCH_GPP_PORT1_HOTPLUG + #endif + + #ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG + #define CFG_FCH_GPP_PORT2_HOTPLUG BLDCFG_FCH_GPP_PORT2_HOTPLUG + #else + #define CFG_FCH_GPP_PORT2_HOTPLUG DFLT_FCH_GPP_PORT2_HOTPLUG + #endif + + #ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG + #define CFG_FCH_GPP_PORT3_HOTPLUG BLDCFG_FCH_GPP_PORT3_HOTPLUG + #else + #define CFG_FCH_GPP_PORT3_HOTPLUG DFLT_FCH_GPP_PORT3_HOTPLUG + #endif + + + #ifdef AGESA_ENTRY_INIT_RESET + #if AGESA_ENTRY_INIT_RESET == TRUE + // + // Define task list for InitReset phase + // + FCH_TASK_ENTRY ROMDATA *FchInitResetTaskTable[] = { + InstallFchInitResetHwAcpiP, + InstallFchInitResetAb, + InstallFchInitResetSpi, + InstallFchInitResetGec, + InstallFchInitResetHwAcpi, + InstallFchInitResetSata, + InstallFchInitResetLpc, + InstallFchInitResetPcib, + InstallFchInitResetPcie, + InstallFchInitResetGpp, + InstallFchInitResetUsb, + InstallFchInitResetUsbEhci, + InstallFchInitResetUsbOhci, + InstallFchInitResetUsbXhci, + InstallFchInitResetImc, + NULL + }; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_ENV + #if AGESA_ENTRY_INIT_ENV == TRUE + // + // Define task list for InitEnv phase + // + FCH_TASK_ENTRY ROMDATA *FchInitEnvTaskTable[] = { + InstallFchInitEnvHwAcpiP, + InstallFchInitEnvPcib, + InstallFchInitEnvPcie, + InstallFchInitEnvIr, + InstallFchInitEnvHwAcpi, + InstallFchInitEnvSpi, + InstallFchInitEnvSd, + InstallFchInitEnvImc, + InstallFchInitEnvUsb, + InstallFchInitEnvUsbEhci, + InstallFchInitEnvUsbOhci, + InstallFchInitEnvUsbXhci, + InstallFchInitEnvSata, + InstallFchInitEnvIde, + InstallFchInitEnvGec, + InstallFchInitEnvAzalia, + InstallFchInitEnvAb, + InstallFchInitEnvGpp, + InstallFchInitEnvAbS, + InstallFchInitEnvHwm, + NULL + }; + #endif + #endif + + + #ifdef AGESA_ENTRY_INIT_MID + #if AGESA_ENTRY_INIT_MID == TRUE + // + // Define task list for InitMid phase + // + FCH_TASK_ENTRY ROMDATA *FchInitMidTaskTable[] = { + InstallFchInitMidImc, + InstallFchInitMidUsb, + InstallFchInitMidUsbEhci, + InstallFchInitMidUsbOhci, + InstallFchInitMidUsbXhci, + InstallFchInitMidSata, + InstallFchInitMidIde, + InstallFchInitMidGec, + InstallFchInitMidAzalia, + InstallFchInitMidHwm, + NULL + }; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_LATE + #if AGESA_ENTRY_INIT_LATE == TRUE + // + // Define task list for InitLate phase + // + FCH_TASK_ENTRY ROMDATA *FchInitLateTaskTable[] = { + InstallFchInitLatePcie, + InstallFchInitLatePcib, + InstallFchInitLateSpi, + InstallFchInitLateUsb, + InstallFchInitLateUsbEhci, + InstallFchInitLateUsbOhci, + InstallFchInitLateUsbXhci, + InstallFchInitLateSata, + InstallFchInitLateIde, + InstallFchInitLateGec, + InstallFchInitLateAzalia, + InstallFchInitLateImc, + InstallFchInitLateHwm, + InstallFchInitLateGpp, + InstallFchInitLateHwAcpi, + NULL + }; + #endif + #endif + + + #ifdef AGESA_ENTRY_INIT_ENV + #if AGESA_ENTRY_INIT_ENV == TRUE + // + // Define task list for S3 resume before PCI phase + // + FCH_TASK_ENTRY ROMDATA *FchInitS3EarlyTaskTable[] = { + InstallFchInitEnvPcie, + InstallFchInitEnvPcib, + InstallFchInitEnvIr, + InstallFchInitEnvHwAcpi, + InstallFchInitEnvSpi, + InstallFchInitEnvSd, + InstallFchInitEnvUsb, + InstallFchInitEnvSata, + InstallFchInitEnvIde, + InstallFchInitEnvGec, + InstallFchInitEnvAzalia, + InstallFchInitEnvAb, + InstallFchInitEnvGpp, + InstallFchInitEnvAbS, + NULL + }; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_LATE + #if AGESA_ENTRY_INIT_LATE == TRUE + // + // Define task list for S3 resume after PCI phase + // + FCH_TASK_ENTRY ROMDATA *FchInitS3LateTaskTable[] = { + InstallFchInitLatePcie, + InstallFchInitLatePcib, + InstallFchInitLateSpi, + InstallFchInitLateUsb, + InstallFchInitLateUsbEhci, + InstallFchInitLateUsbOhci, + InstallFchInitLateUsbXhci, + InstallFchInitMidSata, + InstallFchInitMidIde, + InstallFchInitMidGec, + InstallFchInitMidAzalia, + InstallFchInitLateSata, + InstallFchInitLateIde, + InstallFchInitLateHwAcpi, + InstallFchInitEnvHwm, + InstallFchInitLateHwm, + NULL + }; + #endif + #endif + +#else // FCH_SUPPORT == FALSE + /* FCH Interface entries */ + extern FCH_INIT CommonFchInitStub; + + #define FP_FCH_INIT_RESET &CommonFchInitStub + #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub + #define FP_FCH_INIT_ENV &CommonFchInitStub + #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub + #define FP_FCH_INIT_MID &CommonFchInitStub + #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub + #define FP_FCH_INIT_LATE &CommonFchInitStub + #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub + + #define CFG_SMBUS0_BASE_ADDRESS 0 + #define CFG_SMBUS1_BASE_ADDRESS 0 + #define CFG_SIO_PME_BASE_ADDRESS 0 + #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0 + #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0 + #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS 0 + #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0 + #define CFG_ACPI_GPE0_BLOCK_ADDRESS 0 + #define CFG_SPI_ROM_BASE_ADDRESS 0 + #define CFG_WATCHDOG_TIMER_BASE 0 + #define CFG_HPET_BASE_ADDRESS 0 + #define CFG_SMI_CMD_PORT_ADDRESS 0 + #define CFG_ACPI_PMA_CNTBLK_ADDRESS 0 + #define CFG_GEC_SHADOW_ROM_BASE 0 + #define CFG_AZALIA_SSID 0 + #define CFG_SMBUS_SSID 0 + #define CFG_IDE_SSID 0 + #define CFG_SATA_AHCI_SSID 0 + #define CFG_SATA_IDE_SSID 0 + #define CFG_SATA_RAID5_SSID 0 + #define CFG_SATA_RAID_SSID 0 + #define CFG_EHCI_SSID 0 + #define CFG_OHCI_SSID 0 + #define CFG_LPC_SSID 0 + #define CFG_FCH_GPP_LINK_CONFIG 0 + #define CFG_FCH_GPP_PORT0_PRESENT 0 + #define CFG_FCH_GPP_PORT1_PRESENT 0 + #define CFG_FCH_GPP_PORT2_PRESENT 0 + #define CFG_FCH_GPP_PORT3_PRESENT 0 + #define CFG_FCH_GPP_PORT0_HOTPLUG 0 + #define CFG_FCH_GPP_PORT1_HOTPLUG 0 + #define CFG_FCH_GPP_PORT2_HOTPLUG 0 + #define CFG_FCH_GPP_PORT3_HOTPLUG 0 + +#endif + + +CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = { + FP_FCH_INIT_RESET, + FP_FCH_INIT_RESET_CONSTRUCT, + FP_FCH_INIT_ENV, + FP_FCH_INIT_ENV_CONSTRUCT, + FP_FCH_INIT_MID, + FP_FCH_INIT_MID_CONSTRUCT, + FP_FCH_INIT_LATE, + FP_FCH_INIT_LATE_CONSTRUCT, +}; + +#endif // _OPTION_FCH_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionGfxRecoveryInstall.h new file mode 100644 index 0000000000..c031f326c1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionGfxRecoveryInstall.h @@ -0,0 +1,53 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: GfxRecovery + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_ +#define _OPTION_GFX_RECOVERY_INSTALL_H_ + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ + + +#endif // _OPTION_GFX_RECOVERY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionGnbInstall.h new file mode 100644 index 0000000000..bcd9700293 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionGnbInstall.h @@ -0,0 +1,592 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: GNB + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 49877 $ @e \$Date: 2011-03-30 13:15:18 +0800 (Wed, 30 Mar 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_GNB_INSTALL_H_ +#define _OPTION_GNB_INSTALL_H_ + +#include "S3SaveState.h" +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ + +//--------------------------------------------------------------------------------------------------- +// Family installation +//--------------------------------------------------------------------------------------------------- + + +#define GNB_TYPE_KR FALSE +#define GNB_TYPE_TN FALSE +#define GNB_TYPE_LN FALSE +#define GNB_TYPE_ON FALSE + +#if (OPTION_FAMILY14H_ON == TRUE) + #undef GNB_TYPE_ON + #define GNB_TYPE_ON TRUE +#endif + +#if (OPTION_FAMILY12H_LN == TRUE) + #undef GNB_TYPE_LN + #define GNB_TYPE_LN TRUE +#endif + +#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) +//--------------------------------------------------------------------------------------------------- +// Service installation +//--------------------------------------------------------------------------------------------------- + + #include "Gnb.h" + #include "GnbPcie.h" + + #define SERVICES_POINTER NULL + GNB_SERVICE *ServiceTable = SERVICES_POINTER; + +//--------------------------------------------------------------------------------------------------- +// BUILD options +//--------------------------------------------------------------------------------------------------- + + #ifndef CFG_IGFX_AS_PCIE_EP + #define CFG_IGFX_AS_PCIE_EP TRUE + #endif + + #ifndef CFG_LCLK_DEEP_SLEEP_EN + #define CFG_LCLK_DEEP_SLEEP_EN TRUE + #endif + + #ifndef CFG_LCLK_DPM_EN + #define CFG_LCLK_DPM_EN TRUE + #endif + + #ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY + #define CFG_GMC_POWER_GATE_STUTTER_ONLY FALSE + #endif + + #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE + #if (GNB_TYPE_ON == TRUE) + #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE + #else + #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE + #endif + #endif + + #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE + #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE + #endif + + #ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT + #define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE + #endif + + #ifndef CFG_GNB_LOAD_REAL_FUSE + #define CFG_GNB_LOAD_REAL_FUSE TRUE + #endif + + #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING + #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) + #endif + + #ifndef CFG_GNB_PCIE_LINK_L0_POOLING + #define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000) + #endif + + #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME + #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) + #endif + + #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME + #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) + #endif + + #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM + #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM + #else + #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard + #endif + + #ifndef CFG_GNB_FORCE_CABLESAFE_OFF + #define CFG_GNB_FORCE_CABLESAFE_OFF FALSE + #endif + + #ifndef CFG_ORB_CLOCK_GATING_ENABLE + #define CFG_ORB_CLOCK_GATING_ENABLE TRUE + #endif + + #ifndef CFG_GNB_PCIE_POWERGATING_FLAGS + #define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0 + #endif + + #ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE + #define CFG_IOC_LCLK_CLOCK_GATING_ENABLE FALSE + #endif + + #ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE + #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE + #endif + + #ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE + #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE + #endif + + #ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE + #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE + #endif + + #ifndef CFG_GNB_ALTVDDNB_SUPPORT + #define CFG_GNB_ALTVDDNB_SUPPORT TRUE + #endif + + GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = { + CFG_IGFX_AS_PCIE_EP, + CFG_LCLK_DEEP_SLEEP_EN, + CFG_LCLK_DPM_EN, + CFG_GMC_POWER_GATE_STUTTER_ONLY, + CFG_SMU_SCLK_CLOCK_GATING_ENABLE, + CFG_PCIE_ASPM_BLACK_LIST_ENABLE, + CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT, + CFG_GNB_LOAD_REAL_FUSE, + CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING, + CFG_GNB_PCIE_LINK_L0_POOLING, + CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME, + CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME, + CFG_GNB_PCIE_TRAINING_ALGORITHM, + CFG_GNB_FORCE_CABLESAFE_OFF, + CFG_ORB_CLOCK_GATING_ENABLE, + CFG_GNB_PCIE_POWERGATING_FLAGS, + CFG_IOC_LCLK_CLOCK_GATING_ENABLE, + CFG_IOC_SCLK_CLOCK_GATING_ENABLE, + CFG_IOMMU_L1_CLOCK_GATING_ENABLE, + CFG_IOMMU_L2_CLOCK_GATING_ENABLE, + CFG_GNB_ALTVDDNB_SUPPORT + }; + + //--------------------------------------------------------------------------------------------------- + // Module entries + //--------------------------------------------------------------------------------------------------- + + #if (AGESA_ENTRY_INIT_EARLY == TRUE) + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_EARLY_INIT + #define OPTION_NB_EARLY_INIT TRUE + #endif + #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE NbInitAtEarly; + #define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly}, + #else + #define OPTION_NBINITATEARLY_ENTRY + #endif + #define OPTION_GNBEARLYINTERFACETN_ENTRY + //--------------------------------------------------------------------------------------------------- + // SMU init + #ifndef OPTION_SMU + #define OPTION_SMU TRUE + #endif + #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE) + OPTION_GNB_FEATURE F12NbSmuInitFeature; + #define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature}, + #else + #define OPTION_F12NBSMUINITFEATURE_ENTRY + #endif + #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE F14NbSmuInitFeature; + #define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature}, + #else + #define OPTION_F14NBSMUINITFEATURE_ENTRY + #endif + #define OPTION_KRNBSMUINITFEATURE_ENTRY + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_CONFIG_INIT + #define OPTION_PCIE_CONFIG_INIT TRUE + #endif + #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE PcieConfigurationInit; + #define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit}, + #else + #define OPTION_PCIECONFIGURATIONINIT_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_EARLY_INIT + #define OPTION_PCIE_EARLY_INIT TRUE + #endif + #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE PcieInitAtEarly; + #define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly}, + #else + #define OPTION_PCIEINITATEARLY_ENTRY + #endif + #define OPTION_PCIEEARLYINTERFACETN_ENTRY + //--------------------------------------------------------------------------------------------------- + OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { + OPTION_NBINITATEARLY_ENTRY + OPTION_GNBEARLYINTERFACETN_ENTRY + OPTION_F12NBSMUINITFEATURE_ENTRY + OPTION_F14NBSMUINITFEATURE_ENTRY + OPTION_KRNBSMUINITFEATURE_ENTRY + OPTION_PCIECONFIGURATIONINIT_ENTRY + OPTION_PCIEINITATEARLY_ENTRY + OPTION_PCIEEARLYINTERFACETN_ENTRY + {0, NULL} + }; + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_EARLIER_INIT + #define OPTION_NB_EARLIER_INIT TRUE + #endif + #define OPTION_GNBEARLIERINTERFACETN_ENTRY + + OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = { + OPTION_GNBEARLIERINTERFACETN_ENTRY + {0, NULL} + }; + #endif + + #if (AGESA_ENTRY_INIT_POST == TRUE) + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_CONFIG_POST_INIT + #define OPTION_GFX_CONFIG_POST_INIT TRUE + #endif + #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE GfxConfigPostInterface; + #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface}, + #else + #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_POST_INIT + #define OPTION_GFX_POST_INIT TRUE + #endif + #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE GfxInitAtPost; + #define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost}, + #else + #define OPTION_GFXINITATPOST_ENTRY + #endif + #define OPTION_GFXPOSTINTERFACETN_ENTRY + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_POST_INIT + #define OPTION_NB_POST_INIT TRUE + #endif + #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE NbInitAtPost; + #define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost}, + #else + #define OPTION_NBINITATPOST_ENTRY + #endif + #define OPTION_GNBPOSTINTERFACETN_ENTRY + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_POST_EALRY_INIT + #define OPTION_PCIE_POST_EALRY_INIT TRUE + #endif + #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE PcieInitAtPostEarly; + #define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly}, + #else + #define OPTION_PCIEINITATPOSTEARLY_ENTRY + #endif + #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_POST_INIT + #define OPTION_PCIE_POST_INIT TRUE + #endif + #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE PcieInitAtPost; + #define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost}, + #else + #define OPTION_PCIEINITATPOST_ENTRY + #endif + #define OPTION_PCIEPOSTINTERFACETN_ENTRY + + //--------------------------------------------------------------------------------------------------- + OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { + OPTION_PCIEINITATPOSTEARLY_ENTRY + OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY + OPTION_GFXCONFIGPOSTINTERFACE_ENTRY + OPTION_GFXINITATPOST_ENTRY + OPTION_GFXPOSTINTERFACETN_ENTRY + {0, NULL} + }; + + OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { + OPTION_NBINITATPOST_ENTRY + OPTION_GNBPOSTINTERFACETN_ENTRY + OPTION_PCIEINITATPOST_ENTRY + OPTION_PCIEPOSTINTERFACETN_ENTRY + {0, NULL} + }; + #endif + + #if (AGESA_ENTRY_INIT_ENV == TRUE) + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_FUSE_TABLE_INIT + #define OPTION_FUSE_TABLE_INIT TRUE + #endif + #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE NbFuseTableFeature; + #define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature}, + #else + #define OPTION_NBFUSETABLEFEATURE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_ENV_INIT + #define OPTION_NB_ENV_INIT TRUE + #endif + #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE NbInitAtEnv; + #define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv}, + #else + #define OPTION_NBINITATENVT_ENTRY + #endif + #define OPTION_GNBENVINTERFACETN_ENTRY + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_CONFIG_ENV_INIT + #define OPTION_GFX_CONFIG_ENV_INIT TRUE + #endif + #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE GfxConfigEnvInterface; + #define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface}, + #else + #define OPTION_GFXCONFIGENVINTERFACE_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_ENV_INIT + #define OPTION_GFX_ENV_INIT TRUE + #endif + #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE GfxInitAtEnvPost; + #define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost}, + #else + #define OPTION_GFXINITATENVPOST_ENTRY + #endif + #define OPTION_GFXENVINTERFACETN_ENTRY + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_POWER_GATE + #define OPTION_POWER_GATE TRUE + #endif + #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) + OPTION_GNB_FEATURE F12NbPowerGateFeature; + #define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature}, + #else + #define OPTION_F12NBPOWERGATEFEATURE_ENTRY + #endif + #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE F14NbPowerGateFeature; + #define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature}, + #else + #define OPTION_F14NBPOWERGATEFEATURE_ENTRY + #endif + #define OPTION_KRNBPOWERGATEFEATURE_ENTRY + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_ENV_INIT + #define OPTION_PCIE_ENV_INIT TRUE + #endif + #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE PcieInitAtEnv; + #define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv}, + #else + #define OPTION_PCIEINITATENV_ENTRY + #endif + #define OPTION_PCIEENVINTERFACETN_ENTRY + + //--------------------------------------------------------------------------------------------------- + + OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = { + OPTION_NBFUSETABLEFEATURE_ENTRY + OPTION_NBINITATENVT_ENTRY + OPTION_GNBENVINTERFACETN_ENTRY + OPTION_PCIEINITATENV_ENTRY + OPTION_PCIEENVINTERFACETN_ENTRY + OPTION_GFXCONFIGENVINTERFACE_ENTRY + OPTION_GFXINITATENVPOST_ENTRY + OPTION_GFXENVINTERFACETN_ENTRY + OPTION_F12NBPOWERGATEFEATURE_ENTRY + OPTION_F14NBPOWERGATEFEATURE_ENTRY + OPTION_KRNBPOWERGATEFEATURE_ENTRY + {0, NULL} + }; + #endif + + #if (AGESA_ENTRY_INIT_MID == TRUE) + //--------------------------------------------------------------------------------------------------- + #ifndef OPTOIN_GNB_CABLESAFE + #define OPTOIN_GNB_CABLESAFE TRUE + #endif + #if (OPTOIN_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE) + OPTION_GNB_FEATURE GnbCableSafeEntry; + #define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry}, + #else + #define OPTION_GNBCABLESAFEENTRY_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTOIN_NB_LCLK_NCLK_RATIO + #define OPTOIN_NB_LCLK_NCLK_RATIO TRUE + #endif + #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature; + #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature}, + #else + #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY + #endif + #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_LCLK_DPM_INIT + #define OPTION_NB_LCLK_DPM_INIT TRUE + #endif + #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE NbLclkDpmFeature; + #define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature}, + #else + #define OPTION_NBLCLKDPMFEATURE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_POWER_GATE + #define OPTION_PCIE_POWER_GATE TRUE + #endif + #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) + OPTION_GNB_FEATURE PciePowerGateFeature; + #define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature}, + #else + #define OPTION_PCIEPOWERGATEFEATURE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_MID_INIT + #define OPTION_GFX_MID_INIT TRUE + #endif + #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE GfxInitAtMidPost; + #define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost}, + #else + #define OPTION_GFXINITATMIDPOST_ENTRY + #endif + #define OPTION_GFXMIDINTERFACETN_ENTRY + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT + #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE + #endif + #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry; + #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry}, + #else + #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY + #endif + #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIe_MID_INIT + #define OPTION_PCIe_MID_INIT TRUE + #endif + #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE PcieInitAtMid; + #define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid}, + #else + #define OPTION_PCIEINITATMID_ENTRY + #endif + #define OPTION_PCIEMIDINTERFACETN_ENTRY + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_MID_INIT + #define OPTION_NB_MID_INIT TRUE + #endif + #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE NbInitAtLatePost; + #define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost}, + #else + #define OPTION_NBINITATLATEPOST_ENTRY + #endif + #define OPTION_GNBMIDINTERFACETN_ENTRY + + //--------------------------------------------------------------------------------------------------- + OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = { + OPTION_GFXINITATMIDPOST_ENTRY + OPTION_GFXMIDINTERFACETN_ENTRY + OPTION_GFXINTEGRATEDINFOTABLE_ENTRY + OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY + OPTION_GNBCABLESAFEENTRY_ENTRY + OPTION_PCIEINITATMID_ENTRY + OPTION_PCIEMIDINTERFACETN_ENTRY + OPTION_NBINITATLATEPOST_ENTRY + OPTION_GNBMIDINTERFACETN_ENTRY + OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY + OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY + OPTION_NBLCLKDPMFEATURE_ENTRY + OPTION_PCIEPOWERGATEFEATURE_ENTRY + {0, NULL} + }; + #endif + + #if (AGESA_ENTRY_INIT_LATE == TRUE) + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_ALIB + #define OPTION_ALIB FALSE + #endif + #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE PcieAlibFeature; + #define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature}, + #else + #define OPTION_PCIEALIBFEATURE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_IOMMU_ACPI_IVRS + #define OPTION_IOMMU_ACPI_IVRS TRUE + #endif + #define OPTIONIOMMUACPIIVRSLATE_ENTRY + //--------------------------------------------------------------------------------------------------- + OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = { + OPTION_PCIEALIBFEATURE_ENTRY + OPTIONIOMMUACPIIVRSLATE_ENTRY + {0, NULL} + }; + #endif + + #if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script; + S3_DISPATCH_FUNCTION PcieLateRestoreS3Script; + S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script; + #define GNB_S3_DISPATCH_FUNCTION_TABLE \ + {NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \ + {NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \ + {PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script}, + #endif + + +#endif +#endif // _OPTION_GNB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionHtInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionHtInstall.h new file mode 100644 index 0000000000..eb4e44b5af --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionHtInstall.h @@ -0,0 +1,304 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Ht + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_HT_INSTALL_H_ +#define _OPTION_HT_INSTALL_H_ + +#include "Topology.h" +#include "htFeat.h" +#include "htInterface.h" +#include "htNb.h" +#include "htTopologies.h" +/* + * Advanced Option only, hardware socket naming is the preferred method. + */ +#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP + #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP) +#else + #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL) +#endif + +/* + * OPTION_IS_RECOVERY_HT is true if Basic API is being used. + */ +#ifndef OPTION_IS_RECOVERY_HT + #define OPTION_IS_RECOVERY_HT TRUE +#endif + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition. + */ + +#ifndef OPTION_MULTISOCKET + #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" +#endif + +/* + * Based on user level options, set Ht internal options. + * For now, Family 10h support will assume single module. For multi module, + * this will have to be changed to not set non-coherent only. + */ +#define OPTION_HT_NON_COHERENT_ONLY FALSE + +#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE)) +/* Fusion Families do not need a non-coherent only option. */ +#else + // Process Family 10h and 15h by socket, applying the MultiSocket option where it is allowable. + #if OPTION_G34_SOCKET_SUPPORT == FALSE + // Hydra has coherent support, other Family 10h should follow MultiSocket support. + #if OPTION_MULTISOCKET == FALSE + #undef OPTION_HT_NON_COHERENT_ONLY + #define OPTION_HT_NON_COHERENT_ONLY TRUE + #endif + #endif +#endif + +/* + * Macros will generate the correct item reference based on options + */ +#if AGESA_ENTRY_INIT_EARLY == TRUE + // Select the interface and features + #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE)) + #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL + #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone + #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly + #else + // Family 10h and 15h Models 00h-0Fh + #if OPTION_HT_NON_COHERENT_ONLY == FALSE + #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault + #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault + #else + #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL + #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly + #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly + #endif + #endif + // Select Northbridge components + #if OPTION_FAMILY10H == TRUE + #if OPTION_HT_NON_COHERENT_ONLY == TRUE + #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly, + #else + #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault, + #endif + #else + #define INTERNAL_HT_OPTION_FAM10_NB + #endif + #if OPTION_FAMILY12H == TRUE + #define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb, + #else + #define INTERNAL_HT_OPTION_FAM12_NB + #endif + #if OPTION_FAMILY14H == TRUE + #define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb, + #else + #define INTERNAL_HT_OPTION_FAM14_NB + #endif + #if OPTION_FAMILY15H == TRUE + #if OPTION_HT_NON_COHERENT_ONLY == TRUE + #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly, + #else + #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault, + #endif + #else + #define INTERNAL_HT_OPTION_FAM15_NB + #endif + + #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS, + #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS + #undef INTERNAL_ONLY_NB_LIST_ITEM + #define INTERNAL_ONLY_NB_LIST_ITEM + #endif + + /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item + * is ok to have a comma because the final item (NULL) is added below. + */ + #define INTERNAL_HT_OPTION_SUPPORTED_NBS \ + INTERNAL_ONLY_NB_LIST_ITEM \ + INTERNAL_HT_OPTION_FAM10_NB \ + INTERNAL_HT_OPTION_FAM15_NB \ + INTERNAL_HT_OPTION_FAM12_NB \ + INTERNAL_HT_OPTION_FAM14_NB + +#else + // Not Init Early + #define INTERNAL_HT_OPTION_FEATURES NULL + #define INTERNAL_HT_OPTION_INTERFACE NULL + #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL + #define HT_OPTIONS_PLATFORM NULL + #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL +#endif + +#ifdef AGESA_ENTRY_INIT_EARLY + #if AGESA_ENTRY_INIT_EARLY == TRUE + + extern HT_FEATURES HtFeaturesDefault; + extern HT_FEATURES HtFeaturesNonCoherentOnly; + extern HT_FEATURES HtFeaturesNone; + extern HT_INTERFACE HtInterfaceDefault; + extern HT_INTERFACE HtInterfaceNonCoherentOnly; + extern HT_INTERFACE HtInterfaceMapsOnly; + extern HT_INTERFACE HtInterfaceNone; + extern NORTHBRIDGE HtFam10NbDefault; + extern NORTHBRIDGE HtFam10RevDNbDefault; + extern NORTHBRIDGE HtFam10NbNonCoherentOnly; + extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly; + extern NORTHBRIDGE HtFam12Nb; + extern NORTHBRIDGE HtFam14Nb; + extern NORTHBRIDGE HtFam10NbNone; + extern NORTHBRIDGE HtFam15NbDefault; + extern NORTHBRIDGE HtFam15NbNonCoherentOnly; + + CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = { + INTERNAL_HT_OPTION_SUPPORTED_NBS + NULL + }; + + STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform = + { + CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM, + (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST, + (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST, + (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST, + (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST, + (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST, + (IGNORE_LINK *)CFG_IGNORE_LINK_LIST, + (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST, + (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST, + (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP + }; + #ifndef HT_OPTIONS_PLATFORM + #define HT_OPTIONS_PLATFORM &HtOptionsPlatform + #endif + + /** + * A list of all the supported topologies. + * + */ + #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES + CONST UINT8 *CONST ROMDATA AmdTopolist[] = + { + amdHtTopologySingleNode, + amdHtTopologyDualNode, + amdHtTopologyThreeLine, + amdHtTopologyTriangle, + amdHtTopologyFourLine, + amdHtTopologyFourStar, + amdHtTopologyFourDegenerate, + amdHtTopologyFourSquare, + amdHtTopologyFourKite, + amdHtTopologyFourFully, + amdHtTopologyFiveFully, + amdHtTopologyFiveTwistedLadder, + amdHtTopologySixFully, + amdHtTopologySixDoubloonLower, + amdHtTopologySixDoubloonUpper, + amdHtTopologySixTwistedLadder, + amdHtTopologySevenFully, + amdHtTopologySevenTwistedLadder, + amdHtTopologyEightFully, + amdHtTopologyEightDoubloon, + amdHtTopologyEightTwistedLadder, + amdHtTopologyEightStraightLadder, + amdHtTopologySixTwinTriangles, + amdHtTopologyEightTwinFullyFourWays, + NULL + }; + #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist + #endif + + /** + * Declare the instance of the Ht option configuration structure + */ + CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = { + OPTION_IS_RECOVERY_HT, + CFG_SET_HTCRC_SYNC_FLOOD, + CFG_USE_UNIT_ID_CLUMPING, + HT_OPTIONS_PLATFORM, + INTERNAL_HT_OPTION_INTERFACE, + INTERNAL_HT_OPTION_FEATURES, + &HtInstalledFamilyNorthbridgeList, + INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES + }; + + #endif +#endif + +#ifndef OPTION_HT_INIIT_RESET_ENTRY + + #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset + #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor + + #if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) + #undef OPTION_HT_INIIT_RESET_ENTRY + #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY + #define OPTION_HT_INIIT_RESET_ENTRY NULL + #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL + #endif + + #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE)) + #undef OPTION_HT_INIIT_RESET_ENTRY + #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY + #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset + #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor + #endif + +#endif + +#ifdef AGESA_ENTRY_INIT_RESET + #if AGESA_ENTRY_INIT_RESET == TRUE + + CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = { + (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST, + 0 // Unused by options + }; + + CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = { + OPTION_HT_INIIT_RESET_ENTRY, + OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY + }; + #endif + +#endif + +#endif // _OPTION_HT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionHwC1eInstall.h new file mode 100644 index 0000000000..e30f0488ff --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionHwC1eInstall.h @@ -0,0 +1,80 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: HW C1e + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_HW_C1E_INSTALL_H_ +#define _OPTION_HW_C1E_INSTALL_H_ + +#include "cpuHwC1e.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_HW_C1E_FEAT +#define F10_HW_C1E_SUPPORT +#if AGESA_ENTRY_INIT_EARLY == TRUE + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e; + #undef OPTION_HW_C1E_FEAT + #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e, + extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e; + #undef F10_HW_C1E_SUPPORT + #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e}, + #endif + #endif + #endif + CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] = + { + F10_HW_C1E_SUPPORT + {0, NULL} + }; + CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable = + { + (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &HwC1eFamilyServiceArray[0] + }; +#endif + +#endif // _OPTION_HW_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h new file mode 100644 index 0000000000..4778de358d --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h @@ -0,0 +1,414 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * IDS Option Install File + * + * This file generates the defaults tables for family 10h model 5 processors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 47940 $ @e \$Date: 2011-03-02 14:25:35 +0800 (Wed, 02 Mar 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#ifndef _OPTION_IDS_INSTALL_H_ +#define _OPTION_IDS_INSTALL_H_ +#include "Ids.h" +#include "IdsHt.h" +#include "IdsLib.h" +#ifdef __IDS_EXTENDED__ + #include OPTION_IDS_EXT_INSTALL_FILE +#endif + +#define IDS_LATE_RUN_AP_TASK + +#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid +#if (IDSOPT_IDS_ENABLED == TRUE) + #if (IDSOPT_CONTROL_ENABLED == TRUE) + // Check for all families which include HT Features. + #if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE) + #undef M_HTIDS_PORT_OVERRIDE_HOOK + #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride + #endif + #endif +#endif // OPTION_IDS_LEVEL +CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK; + +#if (IDSOPT_IDS_ENABLED == TRUE) + #if (AGESA_ENTRY_INIT_LATE == TRUE) + #undef IDS_LATE_RUN_AP_TASK + #define IDS_LATE_RUN_AP_TASK + #endif +#endif // OPTION_IDS_LEVEL + +#if (IDSOPT_TRACING_ENABLED == TRUE) + #if (AGESA_ENTRY_INIT_POST == TRUE) + #include + CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { + { (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, + { (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, + { (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} + }; + #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE) + #include + CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { + { (UINTN) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"}, + { (UINTN) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"}, + { (UINTN) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"} + }; + #else + CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { + { (UINTN) CommonReturnFalse, "DefRet()"}, + { (UINTN) CommonReturnFalse, "DefRet()"}, + { (UINTN) CommonReturnFalse, "DefRet()"} + }; + #endif +#endif + + +///Ids Feat Options +#if (IDSOPT_IDS_ENABLED == TRUE) + #if (IDSOPT_CONTROL_ENABLED == TRUE) + + #ifndef OPTION_IDS_EXTEND_FEATS + #define OPTION_IDS_EXTEND_FEATS + #endif + + #define OPTION_IDS_FEAT_ECCCTRL\ + OPTION_IDS_FEAT_ECCCTRL_F10 \ + OPTION_IDS_FEAT_ECCCTRL_F12 \ + OPTION_IDS_FEAT_ECCCTRL_F15_OR + + #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\ + OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \ + OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 + + #define OPTION_IDS_FEAT_CPB_CTRL\ + OPTION_IDS_FEAT_CPB_CTRL_F12 + + #define OPTION_IDS_FEAT_HTC_CTRL\ + OPTION_IDS_FEAT_HTC_CTRL_F15 + + #define OPTION_IDS_FEAT_MEMORY_MAPPING\ + OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \ + OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR + #define OPTION_IDS_FEAT_HT_ASSIST\ + OPTION_IDS_FEAT_HT_ASSIST_F10HY \ + OPTION_IDS_FEAT_HT_ASSIST_F15_OR + + #define OPTION_IDS_FEAT_ECCSYMBOLSIZE\ + OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \ + OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR + +/*---------------------------------------------------------------------------- + * Family 10 feat blocks + * + *---------------------------------------------------------------------------- + */ + #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 + #define OPTION_IDS_FEAT_ECCCTRL_F10 + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE +//Ecc symbol size + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10; + #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 + #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10, + +//ECC scrub control + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10; + #undef OPTION_IDS_FEAT_ECCCTRL_F10 + #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10, + #endif + #endif + + //Misc Features + #define OPTION_IDS_FEAT_HT_ASSIST_F10HY + #ifdef OPTION_FAMILY10H_HY + #if OPTION_FAMILY10H_HY == TRUE + #undef OPTION_IDS_FEAT_HT_ASSIST_F10HY + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy; + + #define OPTION_IDS_FEAT_HT_ASSIST_F10HY \ + &IdsFeatHtAssistBlockPlatformCfgF10Hy, + #endif + #endif +/*---------------------------------------------------------------------------- + * Family 12 feat blocks + * + *---------------------------------------------------------------------------- + */ + #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 + #define OPTION_IDS_FEAT_ECCCTRL_F12 + #define OPTION_IDS_FEAT_CPB_CTRL_F12 + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12; + #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 + #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12, + + //ECC scrub control + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12; + #undef OPTION_IDS_FEAT_ECCCTRL_F12 + #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12, + + #undef OPTION_IDS_FEAT_CPB_CTRL_F12 + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12; + #define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12, + + #endif + #endif + +/*---------------------------------------------------------------------------- + * Family 14 feat blocks + * + *---------------------------------------------------------------------------- + */ + #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14; + #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 + #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14, + #endif + #endif + +/*---------------------------------------------------------------------------- + * Family 15 OR feat blocks + * + *---------------------------------------------------------------------------- + */ + #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR + #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR + #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR + #define OPTION_IDS_FEAT_ECCCTRL_F15_OR + #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR + #ifdef OPTION_FAMILY15H_OR + #if OPTION_FAMILY15H_OR == TRUE + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Or; + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15Or; + #undef OPTION_IDS_FEAT_HTC_CTRL_F15_OR + #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR\ + &IdsFeatHtcControlBlockF15Or,\ + &IdsFeatHtcControlLateBlockF15Or, + + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Or; + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Or; + #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR + #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR\ + &IdsFeatMemoryMappingPostBeforeBlockF15Or,\ + &IdsFeatMemoryMappingChIntlvBlockF15Or, + + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15Or; + #undef OPTION_IDS_FEAT_HT_ASSIST_F15_OR + #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR\ + &IdsFeatHtAssistBlockPlatformCfgF15Or, + + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15Or; + #undef OPTION_IDS_FEAT_ECCCTRL_F15_OR + #define OPTION_IDS_FEAT_ECCCTRL_F15_OR &IdsFeatEccCtrlBlockF15Or, + + extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15Or; + #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR + #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR &IdsFeatEccSymbolSizeBlockF15Or, + + #endif + #endif + + + + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock = + { + IDS_FEAT_UCODE_UPDATE, + IDS_ALL_CORES, + IDS_UCODE, + IDS_FAMILY_ALL, + IdsSubUCode + }; + + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock = + { + IDS_FEAT_POWER_POLICY, + IDS_ALL_CORES, + IDS_PLATFORMCFG_OVERRIDE, + IDS_FAMILY_ALL, + IdsSubPowerPolicyOverride + }; + + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock = + { + IDS_FEAT_TARGET_PSTATE, + IDS_BSP_ONLY, + IDS_INIT_LATE_AFTER, + IDS_FAMILY_ALL, + IdsSubTargetPstate + }; + + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock = + { + IDS_FEAT_POSTPSTATE, + IDS_ALL_CORES, + IDS_CPU_Early_Override, + IDS_FAMILY_ALL, + IdsSubPostPState + }; + + //Dram controller Features + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock = + { + IDS_FEAT_DCT_ALLMEMCLK, + IDS_BSP_ONLY, + IDS_ALL_MEMORY_CLOCK, + IDS_FAMILY_ALL, + IdsSubAllMemClkEn + }; + + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock = + { + IDS_FEAT_DCT_GANGMODE, + IDS_BSP_ONLY, + IDS_GANGING_MODE, + IDS_FAMILY_ALL, + IdsSubGangingMode + }; + + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock = + { + IDS_FEAT_DCT_BURSTLENGTH, + IDS_BSP_ONLY, + IDS_BURST_LENGTH32, + AMD_FAMILY_10, + IdsSubBurstLength32 + }; + + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock = + { + IDS_FEAT_DCT_POWERDOWN, + IDS_BSP_ONLY, + IDS_INIT_POST_BEFORE, + IDS_FAMILY_ALL, + IdsSubPowerDownCtrl + }; + + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock = + { + IDS_FEAT_DCT_DLLSHUTDOWN, + IDS_BSP_ONLY, + IDS_DLL_SHUT_DOWN, + IDS_FAMILY_ALL, + IdsSubDllShutDownSR + }; + + + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock = + { + IDS_FEAT_DCT_POWERDOWN, + IDS_BSP_ONLY, + IDS_POWERDOWN_MODE, + IDS_FAMILY_ALL, + IdsSubPowerDownMode + }; + + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock = + { + IDS_FEAT_HDTOUT, + IDS_BSP_ONLY, + IDS_INIT_EARLY_BEFORE, + IDS_FAMILY_ALL, + IdsSubHdtOut + }; + + CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock = + { + IDS_FEAT_HT_SETTING, + IDS_BSP_ONLY, + IDS_HT_CONTROL, + IDS_FAMILY_ALL, + IdsSubHtLinkControl + }; + + CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = + { + &IdsFeatUcodeBlock, + &IdsFeatPowerPolicyBlock, + + &IdsFeatTargetPstateBlock, + + &IdsFeatPostPstateBlock, + + OPTION_IDS_FEAT_ECCSYMBOLSIZE + + OPTION_IDS_FEAT_ECCCTRL + + &IdsFeatDctAllMemClkBlock, + + &IdsFeatDctGangModeBlock, + + &IdsFeatDctBurstLengthBlock, + + &IdsFeatDctPowerDownCtrlBlock, + + &IdsFeatDctPowerDownModeBlock, + + &IdsFeatDctPowerDownModeBlock, + + OPTION_IDS_FEAT_HT_ASSIST + + &IdsFeatHdtOutBlock, + + &IdsFeatHtSettingBlock, + + OPTION_IDS_FEAT_GNB_PLATFORMCFG + + OPTION_IDS_FEAT_CPB_CTRL + + OPTION_IDS_FEAT_HTC_CTRL + + OPTION_IDS_FEAT_MEMORY_MAPPING + + OPTION_IDS_EXTEND_FEATS + + NULL + }; + #else + CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = + { + NULL + }; + #endif//IDSOPT_CONTROL_ENABLED +#else + CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = + { + NULL + }; +#endif// IDSOPT_IDS_ENABLED + + +#endif diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionIoCstateInstall.h new file mode 100644 index 0000000000..3402809b3f --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionIoCstateInstall.h @@ -0,0 +1,132 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: IO C-state + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_IO_CSTATE_INSTALL_H_ +#define _OPTION_IO_CSTATE_INSTALL_H_ + +#include "cpuIoCstate.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ + +#define OPTION_IO_CSTATE_FEAT +#define F10_IO_CSTATE_SUPPORT +#define F12_IO_CSTATE_SUPPORT +#define F14_IO_CSTATE_SUPPORT +#define F15_OR_IO_CSTATE_SUPPORT + +#if OPTION_IO_CSTATE == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if OPTION_FAMILY10H_PH == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; + #undef OPTION_IO_CSTATE_FEAT + #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, + extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport; + #undef F10_IO_CSTATE_SUPPORT + #define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport}, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + #if OPTION_FAMILY12H_LN == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; + #undef OPTION_IO_CSTATE_FEAT + #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, + extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport; + #undef F12_IO_CSTATE_SUPPORT + #define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport}, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + #if OPTION_FAMILY14H_ON == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; + #undef OPTION_IO_CSTATE_FEAT + #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, + extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport; + #undef F14_IO_CSTATE_SUPPORT + #define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14, &F14IoCstateSupport}, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if OPTION_FAMILY15H_OR == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; + #undef OPTION_IO_CSTATE_FEAT + #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, + extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport; + #undef F15_OR_IO_CSTATE_SUPPORT + #define F15_OR_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrIoCstateSupport}, + #endif + #endif + #endif + + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] = +{ + F10_IO_CSTATE_SUPPORT + F12_IO_CSTATE_SUPPORT + F14_IO_CSTATE_SUPPORT + F15_OR_IO_CSTATE_SUPPORT + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable = +{ + (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &IoCstateFamilyServiceArray[0] +}; + +#endif // _OPTION_IO_CSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionL3FeaturesInstall.h new file mode 100644 index 0000000000..7f3ac0769f --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionL3FeaturesInstall.h @@ -0,0 +1,104 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: L3 Dependent Features + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_L3_FEATURES_INSTALL_H_ +#define _OPTION_L3_FEATURES_INSTALL_H_ + +#include "cpuL3Features.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_L3_FEAT +#define F10_L3_FEAT_SUPPORT +#define F15_L3_FEAT_SUPPORT +#define L3_FEAT_AP_DISABLE_CACHE +#define L3_FEAT_AP_ENABLE_CACHE + +#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE) + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if OPTION_FAMILY10H_HY == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features; + #undef OPTION_L3_FEAT + #define OPTION_L3_FEAT &CpuL3Features, + extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features; + #undef F10_L3_FEAT_SUPPORT + #define F10_L3_FEAT_SUPPORT {AMD_FAMILY_10_HY, &F10L3Features}, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features; + #undef OPTION_L3_FEAT + #define OPTION_L3_FEAT &CpuL3Features, + extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features; + #undef F15_L3_FEAT_SUPPORT + #define F15_L3_FEAT_SUPPORT {AMD_FAMILY_15, &F15OrL3Features}, + #endif + #endif + + #undef L3_FEAT_AP_DISABLE_CACHE + #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, + #undef L3_FEAT_AP_ENABLE_CACHE + #define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches}, + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] = +{ + F10_L3_FEAT_SUPPORT + F15_L3_FEAT_SUPPORT + {0, NULL} +}; +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable = +{ + (sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &L3FeatureFamilyServiceArray[0] +}; + +#endif // _OPTION_L3_FEATURES_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionLowPwrPstateInstall.h new file mode 100644 index 0000000000..3f9a3def52 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionLowPwrPstateInstall.h @@ -0,0 +1,86 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Low Power Pstate for PROCHOT_L Throttling. + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_ +#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_ + +#include "cpuLowPwrPstate.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT +#define F15_LOW_PWR_PSTATE_SUPPORT + +#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + // Family 15h + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if OPTION_FAMILY15H_OR == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate; + #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT + #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate, + extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport; + #undef F15_LOW_PWR_PSTATE_SUPPORT + #define F15_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrLowPwrPstateSupport}, + #endif + #endif + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] = +{ + F15_LOW_PWR_PSTATE_SUPPORT + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable = +{ + (sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &LowPwrPstateFamilyServiceArray[0] +}; + +#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionMemoryInstall.h new file mode 100644 index 0000000000..0fd8232ead --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionMemoryInstall.h @@ -0,0 +1,4202 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Memory + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 49545 $ @e \$Date: 2011-03-25 05:58:58 +0800 (Fri, 25 Mar 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_MEMORY_INSTALL_H_ +#define _OPTION_MEMORY_INSTALL_H_ + +#ifndef RUN_BROKEN_AGESA_TESTS + #define RUN_BROKEN_AGESA_TESTS 0 +#endif + +/*------------------------------------------------------------------------------- + * This option file is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ + +/*---------------------------------------------------------------------------------- + * FEATURE BLOCK FUNCTIONS + * + * This section defines function names that depend upon options that are selected + * in the platform solution install file. + */ +BOOLEAN MemFDefRet ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + return FALSE; +} + +BOOLEAN MemMDefRet ( + IN MEM_MAIN_DATA_BLOCK *MMPtr + ) +{ + return TRUE; +} + +BOOLEAN MemMDefRetFalse ( + IN MEM_MAIN_DATA_BLOCK *MMPtr + ) +{ + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN MemNIdentifyDimmConstructorRetDef ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + return FALSE; +} +/*---------------------------------------------------------------------------------- + * TABLE FEATURE BLOCK FUNCTIONS + * + * This section defines function names that depend upon options that are selected + * in the platform solution install file. + */ +UINT8 MemFTableDefRet ( + IN OUT MEM_TABLE_ALIAS **MTPtr + ) +{ + return 0; +} +/*---------------------------------------------------------------------------------- + * FEATURE S3 BLOCK FUNCTIONS + * + * This section defines function names that depend upon options that are selected + * in the platform solution install file. + */ +BOOLEAN MemFS3DefConstructorRet ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + return TRUE; +} + +#if (OPTION_MEMCTLR_DR == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr; + #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr + #else + #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + #if (OPTION_MEMCTLR_Ni == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet + #endif + #if (OPTION_MEMCTLR_DA == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet + #endif + #if (OPTION_MEMCTLR_PH == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet + #endif + #if (OPTION_MEMCTLR_RB == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet + #endif + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA; + #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb; + #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh; + #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh + #else + #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef + #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef + #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_OR == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr; + #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr + #else + #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_HY == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy; + #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy + #else + #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_C32 == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32 + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32; + #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32 + #else + #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_LN == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockLN; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemS3ResumeConstructNBBlockLN + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorLN; + #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorLN + #else + #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_ON == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON; + #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON + #else + #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef + #endif +#endif + +/*---------------------------------------------------------------------------------- + * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS + * + *---------------------------------------------------------------------------------- +*/ +#define MEM_NB_SUPPORT_DR +#define MEM_NB_SUPPORT_RB +#define MEM_NB_SUPPORT_DA +#define MEM_NB_SUPPORT_Ni +#define MEM_NB_SUPPORT_PH +#define MEM_NB_SUPPORT_HY +#define MEM_NB_SUPPORT_LN +#define MEM_NB_SUPPORT_OR +#define MEM_NB_SUPPORT_C32 +#define MEM_NB_SUPPORT_ON +#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 } + +#if (AGESA_ENTRY_INIT_POST == TRUE) + /*---------------------------------------------------------------------------------- + * FLOW CONTROL FUNCTION + * + * This section selects the function that controls the memory initialization sequence + * based upon the number of processor families that the BIOS will support. + */ + + extern MEM_FLOW_CFG MemMFlowDef; + #if (OPTION_MEMCTLR_DR == TRUE) + extern MEM_FLOW_CFG MemMFlowDr; + #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_DA == TRUE) + extern MEM_FLOW_CFG MemMFlowDA; + #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_HY == TRUE) + extern MEM_FLOW_CFG MemMFlowHy; + #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_OR == TRUE) + extern MEM_FLOW_CFG MemMFlowOr; + #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_LN == TRUE) + extern MEM_FLOW_CFG MemMFlowLN; + #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_C32 == TRUE) + extern MEM_FLOW_CFG MemMFlowC32; + #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_ON == TRUE) + extern MEM_FLOW_CFG MemMFlowON; + #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_Ni == TRUE) + extern MEM_FLOW_CFG MemMFlowDA; + #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_RB == TRUE) + extern MEM_FLOW_CFG MemMFlowRb; + #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_PH == TRUE) + extern MEM_FLOW_CFG MemMFlowPh; + #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef, + #endif + + MEM_FLOW_CFG* memFlowControlInstalled[] = { + MEM_MAIN_FLOW_CONTROL_PTR_Dr + MEM_MAIN_FLOW_CONTROL_PTR_DA + MEM_MAIN_FLOW_CONTROL_PTR_RB + MEM_MAIN_FLOW_CONTROL_PTR_PH + MEM_MAIN_FLOW_CONTROL_PTR_Hy + MEM_MAIN_FLOW_CONTROL_PTR_OR + MEM_MAIN_FLOW_CONTROL_PTR_LN + MEM_MAIN_FLOW_CONTROL_PTR_C32 + MEM_MAIN_FLOW_CONTROL_PTR_ON + MEM_MAIN_FLOW_CONTROL_PTR_Ni + NULL + }; + + #if (OPTION_ONLINE_SPARE == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare; + #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMOnlineSpare + extern OPTION_MEM_FEATURE_NB MemFOnlineSpare; + #define MEM_FEATURE_ONLINE_SPARE MemFOnlineSpare + #else + #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMDefRet + #define MEM_FEATURE_ONLINE_SPARE MemFDefRet + #endif + + #if (OPTION_MEM_RESTORE == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMContextSave; + extern OPTION_MEM_FEATURE_MAIN MemMContextRestore; + #define MEM_MAIN_FEATURE_MEM_SAVE MemMContextSave + #define MEM_MAIN_FEATURE_MEM_RESTORE MemMContextRestore + #else + #define MEM_MAIN_FEATURE_MEM_SAVE MemMDefRet + #define MEM_MAIN_FEATURE_MEM_RESTORE MemMDefRetFalse + #endif + + #if (OPTION_BANK_INTERLEAVE == TRUE) + extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks; + #define MEM_FEATURE_BANK_INTERLEAVE MemFInterleaveBanks + extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks; + #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks + #else + #define MEM_FEATURE_BANK_INTERLEAVE MemFDefRet + #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet + #endif + + #if (OPTION_NODE_INTERLEAVE == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes; + #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMInterleaveNodes + extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes; + extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes; + #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFCheckInterleaveNodes + #define MEM_FEATURE_NODE_INTERLEAVE MemFInterleaveNodes + #else + #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFDefRet + #define MEM_FEATURE_NODE_INTERLEAVE MemFDefRet + #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMDefRet + #endif + + #if (OPTION_DCT_INTERLEAVE == TRUE) + extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels; + #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFInterleaveChannels + #else + #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFDefRet + #endif + + #if (OPTION_ECC == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMEcc; + #define MEM_MAIN_FEATURE_ECC MemMEcc + extern OPTION_MEM_FEATURE_NB MemFCheckECC; + extern OPTION_MEM_FEATURE_NB MemFInitECC; + #define MEM_FEATURE_CK_ECC MemFCheckECC + #define MEM_FEATURE_ECC MemFInitECC + #define MEM_FEATURE_ECCX8 MemMDefRet + #else + #define MEM_MAIN_FEATURE_ECC MemMDefRet + #define MEM_FEATURE_CK_ECC MemFDefRet + #define MEM_FEATURE_ECC MemFDefRet + #define MEM_FEATURE_ECCX8 MemMDefRet + #endif + + extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr; + #define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr + + #if (OPTION_DMI == TRUE) + #if (OPTION_DDR3 == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3; + #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3 + #else + extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2; + #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2 + #endif + #else + #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet + #endif + + #if (OPTION_DDR3 == TRUE) + extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal; + extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3; + extern OPTION_MEM_FEATURE_NB MemFLvDdr3; + #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal + #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3 + #define MEM_FEATURE_LVDDR3 MemFLvDdr3 + #else + #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet + #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet + #define MEM_FEATURE_LVDDR3 MemFDefRet + #endif + + extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion; + #define MEM_FEATURE_REGION_INTERLEAVE MemFInterleaveRegion + + extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc; + #define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc + + extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #if (OPTION_PARALLEL_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining + #else + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + #endif + + #if (OPTION_DIMM_EXCLUDE == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM; + #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMRASExcludeDIMM + extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM; + #define MEM_FEATURE_DIMM_EXCLUDE MemFRASExcludeDIMM + #else + #define MEM_FEATURE_DIMM_EXCLUDE MemFDefRet + #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMDefRet + #endif + + /*---------------------------------------------------------------------------------- + * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS + * + *---------------------------------------------------------------------------------- + */ + #if OPTION_DDR2 == TRUE + extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2; + #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2, + #if (OPTION_HW_DRAM_INIT == TRUE) + extern MEM_TECH_FEAT MemTDramInitHw; + #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw + #else + #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef + #endif + #if (OPTION_SW_DRAM_INIT == TRUE) + #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef + #else + #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef + #endif + #else + #define MEM_TECH_CONSTRUCTOR_DDR2 + #endif + #if OPTION_DDR3 == TRUE + extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3; + #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3, + #if (OPTION_HW_DRAM_INIT == TRUE) + extern MEM_TECH_FEAT MemTDramInitHw; + #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw + #else + #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef + #endif + #if (OPTION_SW_DRAM_INIT == TRUE) + #define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3 + #else + #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef + #endif + #else + #define MEM_TECH_CONSTRUCTOR_DDR3 + #endif + + /*--------------------------------------------------------------------------------------------------- + * FEATURE BLOCKS + * + * This section instantiates a feature block structure for each memory controller installed + * by the platform solution install file. + *--------------------------------------------------------------------------------------------------- + */ + + /*--------------------------------------------------------------------------------------------------- + * DEERHOUND FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_DR == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING +// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + extern OPTION_MEM_FEATURE_NB MemFStandardTraining; + #define MEM_FEATURE_TRAINING MemFStandardTraining + + MEM_FEAT_BLOCK_NB MemFeatBlockDr = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MEM_FEATURE_ONLINE_SPARE, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MEM_FEATURE_NODE_INTERLEAVE_CHECK, + MEM_FEATURE_NODE_INTERLEAVE, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MemFDefRet, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MemFDefRet, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_DR + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR; + extern MEM_INITIALIZER MemNInitDefaultsDR; + + + #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, + #endif // OPTION_MEMCTRL_DR + + /*--------------------------------------------------------------------------------------------------- + * DASHOUND FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING +// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + extern OPTION_MEM_FEATURE_NB MemFStandardTraining; + #define MEM_FEATURE_TRAINING MemFStandardTraining + + #if (OPTION_MEMCTLR_Ni == TRUE) + MEM_FEAT_BLOCK_NB MemFeatBlockNi = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MemFDefRet, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_Ni + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi; + extern MEM_INITIALIZER MemNInitDefaultsNi; + + #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA }, + #endif + + #if (OPTION_MEMCTLR_PH == TRUE) + MEM_FEAT_BLOCK_NB MemFeatBlockPh = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MemFDefRet, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_PH + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh; + extern MEM_INITIALIZER MemNInitDefaultsPh; + + #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, + #endif + + #if (OPTION_MEMCTLR_RB == TRUE) + MEM_FEAT_BLOCK_NB MemFeatBlockRb = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MemFDefRet, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_RB + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb; + extern MEM_INITIALIZER MemNInitDefaultsRb; + + #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, + #endif + + #if (OPTION_MEMCTLR_DA == TRUE) + MEM_FEAT_BLOCK_NB MemFeatBlockDA = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MemFDefRet, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_DA + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA; + extern MEM_INITIALIZER MemNInitDefaultsDA; + + #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, + #endif + #endif // OPTION_MEMCTRL_DA + + /*--------------------------------------------------------------------------------------------------- + * HYDRA FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_HY == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING +// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + extern OPTION_MEM_FEATURE_NB MemFStandardTraining; + #define MEM_FEATURE_TRAINING MemFStandardTraining + + MEM_FEAT_BLOCK_NB MemFeatBlockHy = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MEM_FEATURE_ONLINE_SPARE, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MEM_FEATURE_NODE_INTERLEAVE_CHECK, + MEM_FEATURE_NODE_INTERLEAVE, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MemFDefRet, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MEM_FEATURE_ONDIMMTHERMAL, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_HY + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY; + extern MEM_INITIALIZER MemNInitDefaultsHY; + #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, + #endif // OPTION_MEMCTRL_HY + /*--------------------------------------------------------------------------------------------------- + * LLANO FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_LN == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #if (OPTION_EARLY_SAMPLES == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportLN; + #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportLN + #else + #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet + #endif + + #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb; + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb + #else + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + #endif + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING +// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + extern OPTION_MEM_FEATURE_NB MemFStandardTraining; + #define MEM_FEATURE_TRAINING MemFStandardTraining + + MEM_FEAT_BLOCK_NB MemFeatBlockLn = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MemFDefRet, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MEM_FEATURE_ONDIMMTHERMAL, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MEM_EARLY_SAMPLE_SUPPORT, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + #undef MEM_NB_SUPPORT_LN + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockLN; + extern MEM_INITIALIZER MemNInitDefaultsLN; + #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockLN, MemNInitDefaultsLN, &MemFeatBlockLn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN }, + + #endif // OPTION_MEMCTRL_LN + + /*--------------------------------------------------------------------------------------------------- + * ONTARIO FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_ON == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb; + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb + #else + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + #endif + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + extern OPTION_MEM_FEATURE_NB MemFStandardTraining; + #define MEM_FEATURE_TRAINING MemFStandardTraining + + #if (OPTION_EARLY_SAMPLES == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON; + #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportON + #else + #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet + #endif + + MEM_FEAT_BLOCK_NB MemFeatBlockOn = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MemFDefRet, + MemFDefRet, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MEM_FEATURE_ONDIMMTHERMAL, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MEM_EARLY_SAMPLE_SUPPORT, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_ON + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON; + extern MEM_INITIALIZER MemNInitDefaultsON; + #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, + + #endif // OPTION_MEMCTRL_ON + + /*--------------------------------------------------------------------------------------------------- + * OROCHI FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_OR == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_MAIN_FEATURE_LVDDR3 + extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre; + #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #if (OPTION_G34_SOCKET_SUPPORT || OPTION_C32_SOCKET_SUPPORT) + #undef MEM_FEATURE_REGION_INTERLEAVE + #define MEM_FEATURE_REGION_INTERLEAVE MemFDefRet + #endif + + #if (OPTION_EARLY_SAMPLES == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr; + #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportOr + #else + #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet + #endif + + #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb; + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemNInitCPGUnb + #else + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + #endif + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING +// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + extern OPTION_MEM_FEATURE_NB MemFStandardTraining; + #define MEM_FEATURE_TRAINING MemFStandardTraining + + MEM_FEAT_BLOCK_NB MemFeatBlockOr = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MEM_FEATURE_ONLINE_SPARE, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MEM_FEATURE_NODE_INTERLEAVE_CHECK, + MEM_FEATURE_NODE_INTERLEAVE, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MEM_FEATURE_ONDIMMTHERMAL, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MEM_EARLY_SAMPLE_SUPPORT, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_OR + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR; + extern MEM_INITIALIZER MemNInitDefaultsOR; + #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, + #endif // OPTION_MEMCTRL_OR + + /*--------------------------------------------------------------------------------------------------- + * C32 FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_C32 == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING +// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + extern OPTION_MEM_FEATURE_NB MemFStandardTraining; + #define MEM_FEATURE_TRAINING MemFStandardTraining + + MEM_FEAT_BLOCK_NB MemFeatBlockC32 = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MEM_FEATURE_ONLINE_SPARE, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MEM_FEATURE_NODE_INTERLEAVE_CHECK, + MEM_FEATURE_NODE_INTERLEAVE, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MemFDefRet, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MEM_FEATURE_ONDIMMTHERMAL, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_C32 + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32; + extern MEM_INITIALIZER MemNInitDefaultsC32; + #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, + #endif // OPTION_MEMCTRL_C32 + + /*--------------------------------------------------------------------------------------------------- + * MAIN FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + MEM_FEAT_BLOCK_MAIN MemFeatMain = { + MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION, + MEM_MAIN_FEATURE_TRAINING, + MEM_MAIN_FEATURE_DIMM_EXCLUDE, + MEM_MAIN_FEATURE_ONLINE_SPARE, + MEM_MAIN_FEATURE_NODE_INTERLEAVE, + MEM_MAIN_FEATURE_ECC, + MEM_MAIN_FEATURE_MEM_CLEAR, + MEM_MAIN_FEATURE_MEM_DMI, + MEM_MAIN_FEATURE_LVDDR3, + MEM_MAIN_FEATURE_UMAALLOC, + MEM_MAIN_FEATURE_MEM_SAVE, + MEM_MAIN_FEATURE_MEM_RESTORE + }; + + + /*--------------------------------------------------------------------------------------------------- + * Technology Training SPECIFIC CONFIGURATION + * + * + *--------------------------------------------------------------------------------------------------- + */ + #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0 + #if OPTION_MEMCTLR_DR + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; + #if OPTION_DDR2 + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Dr = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 + }; + extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; + #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb + extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr }, + #else + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #endif + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif +// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb +// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Dr = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + }; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB) + #if OPTION_DDR2 + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2DA = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2PH = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Rb = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Ni = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 + }; + extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; + #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb + extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; + #if (OPTION_MEMCTLR_DA) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if (OPTION_MEMCTLR_PH) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if (OPTION_MEMCTLR_RB) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + #if (OPTION_MEMCTLR_Ni) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #endif + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3DA = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ph = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Rb = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ni = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + }; +// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb +// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; + #if (OPTION_MEMCTLR_DA) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if (OPTION_MEMCTLR_PH) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if (OPTION_MEMCTLR_RB) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if (OPTION_MEMCTLR_Ni) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + #if OPTION_MEMCTLR_HY + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy; + #if OPTION_DDR2 + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Hy = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 + }; + extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; + #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb + extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy }, + #else + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #endif + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Hy = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + }; +// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb +// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + #if OPTION_MEMCTLR_C32 + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32; + #if OPTION_DDR2 + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2C32 = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 + }; + extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; + #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb + extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 }, + #else + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #endif + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3C32 = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + }; +// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb +// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + + #if OPTION_MEMCTLR_LN + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceLN; + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3 + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3LN = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + }; +// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb +// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceLN, &memTechTrainingFeatSequenceDDR3LN }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + + #if OPTION_MEMCTLR_OR + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr; + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #endif + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3OR = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + }; +// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb +// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + + #if OPTION_MEMCTLR_ON + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON; + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3 + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3ON = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + }; +// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb +// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 } + MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB + MEM_TECH_ENABLE_TRAINING_SEQUENCE_END + }; + + MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB + MEM_TECH_ENABLE_TRAINING_SEQUENCE_END + }; + /*--------------------------------------------------------------------------------------------------- + * NB TRAINING FLOW CONTROL + * + * + *--------------------------------------------------------------------------------------------------- + */ + OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control + NB_TRAIN_FLOW_DDR2, + NB_TRAIN_FLOW_DDR3, + }; + /*--------------------------------------------------------------------------------------------------- + * TECHNOLOGY BLOCK + * + * + *--------------------------------------------------------------------------------------------------- + */ + MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed + MEM_TECH_CONSTRUCTOR_DDR2 + MEM_TECH_CONSTRUCTOR_DDR3 + NULL + }; + /*--------------------------------------------------------------------------------------------------- + * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION + * + * + *--------------------------------------------------------------------------------------------------- + */ + #if OPTION_MEMCTLR_HY + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUHy3, + #else + #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsRHy3, + #else + #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsSHy3, + #else + #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { + PLAT_SP_HY_FF_UDIMM2 + PLAT_SP_HY_FF_RDIMM2 + PLAT_SP_HY_FF_SDIMM2 + PLAT_SP_HY_FF_UDIMM3 + PLAT_SP_HY_FF_RDIMM3 + PLAT_SP_HY_FF_SDIMM3 + }; + + #if OPTION_MEMCTLR_DR + #if OPTION_UDIMMS + #if OPTION_DDR2 + extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2; + #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDr2, + #else + #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDr3, + #else + #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2; + #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsRDr2, + #else + #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsRDr3, + #else + #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsSDr3, + #else + #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = { + PLAT_SP_DR_FF_UDIMM2 + PLAT_SP_DR_FF_RDIMM2 + PLAT_SP_DR_FF_SDIMM2 + PLAT_SP_DR_FF_UDIMM3 + PLAT_SP_DR_FF_RDIMM3 + PLAT_SP_DR_FF_SDIMM3 + }; + + #if (OPTION_MEMCTLR_DA == TRUE) + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDA3, + #else + #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, + #else + #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsSDA2, + #else + #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsSDA3, + #else + #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { + PLAT_SP_DA_FF_UDIMM2 + PLAT_SP_DA_FF_RDIMM2 + PLAT_SP_DA_FF_SDIMM2 + PLAT_SP_DA_FF_UDIMM3 + PLAT_SP_DA_FF_RDIMM3 + PLAT_SP_DA_FF_SDIMM3 + }; + + #if (OPTION_MEMCTLR_Ni == TRUE) + #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsSNi3, + #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUNi3, + #else + #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { + PLAT_SP_NI_FF_UDIMM2 + PLAT_SP_NI_FF_RDIMM2 + PLAT_SP_NI_FF_SDIMM2 + PLAT_SP_NI_FF_UDIMM3 + PLAT_SP_NI_FF_RDIMM3 + PLAT_SP_NI_FF_SDIMM3 + }; + + #if (OPTION_MEMCTLR_PH == TRUE) + #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsSPh3, + #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUPh3, + #else + #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { + PLAT_SP_PH_FF_UDIMM2 + PLAT_SP_PH_FF_RDIMM2 + PLAT_SP_PH_FF_SDIMM2 + PLAT_SP_PH_FF_UDIMM3 + PLAT_SP_PH_FF_RDIMM3 + PLAT_SP_PH_FF_SDIMM3 + }; + + #if (OPTION_MEMCTLR_RB == TRUE) + #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsSRb3, + #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsURb3, + #else + #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { + PLAT_SP_RB_FF_UDIMM2 + PLAT_SP_RB_FF_RDIMM2 + PLAT_SP_RB_FF_SDIMM2 + PLAT_SP_RB_FF_UDIMM3 + PLAT_SP_RB_FF_RDIMM3 + PLAT_SP_RB_FF_SDIMM3 + }; + + #if OPTION_MEMCTLR_LN + #if OPTION_UDIMMS + #if OPTION_DDR3 + #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsULN3, + #else + #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #if OPTION_DDR3 + #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsSLN3, + #else + #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[] = { + PLAT_SP_LN_FF_SDIMM3 + PLAT_SP_LN_FF_UDIMM3 + NULL + }; + + #if OPTION_MEMCTLR_C32 + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUC32_3, + #else + #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsRC32_3, + #else + #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { + PLAT_SP_C32_FF_UDIMM2 + PLAT_SP_C32_FF_RDIMM2 + PLAT_SP_C32_FF_SDIMM2 + PLAT_SP_C32_FF_UDIMM3 + PLAT_SP_C32_FF_RDIMM3 + PLAT_SP_C32_FF_SDIMM3 + }; + + #if OPTION_MEMCTLR_ON + #if OPTION_UDIMMS + #if OPTION_DDR3 + #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUON3, + #else + #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #if OPTION_DDR3 + #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsSON3, + #else + #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = { + PLAT_SP_ON_FF_SDIMM3 + PLAT_SP_ON_FF_UDIMM3 + NULL + }; + + /*--------------------------------------------------------------------------------------------------- + * PLATFORM-SPECIFIC CONFIGURATION + * + * + *--------------------------------------------------------------------------------------------------- + */ + + #if OPTION_MEMCTLR_DR + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_DR_UDIMM_DDR2 //MemAGetPsCfgUDr2 + #else + #define PSC_DR_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DR_UDIMM_DDR3 MemAGetPsCfgUDr3, + #else + #define PSC_DR_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_DR_RDIMM_DDR2 MemAGetPsCfgRDr2, + #else + #define PSC_DR_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DR_RDIMM_DDR3 MemAGetPsCfgRDr3, + #else + #define PSC_DR_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_DR_SODIMM_DDR2 //MemAGetPsCfgSDr2 + #else + #define PSC_DR_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DR_SODIMM_DDR3 //MemAGetPsCfgSDr3 + #else + #define PSC_DR_SODIMM_DDR3 + #endif + #endif + #endif + + #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) + #if OPTION_MEMCTLR_Ni + #define PSC_NI_UDIMM_DDR2 + #define PSC_NI_UDIMM_DDR3 MemAGetPsCfgUNi3, + #define PSC_NI_RDIMM_DDR2 + #define PSC_NI_RDIMM_DDR3 + #define PSC_NI_SODIMM_DDR2 + #define PSC_NI_SODIMM_DDR3 MemAGetPsCfgSNi3, + #endif + #if OPTION_MEMCTLR_PH + #define PSC_PH_UDIMM_DDR2 + #define PSC_PH_UDIMM_DDR3 MemAGetPsCfgUPh3, + #define PSC_PH_RDIMM_DDR2 + #define PSC_PH_RDIMM_DDR3 + #define PSC_PH_SODIMM_DDR2 + #define PSC_PH_SODIMM_DDR3 MemAGetPsCfgSPh3, + #endif + #if OPTION_MEMCTLR_RB + #define PSC_RB_UDIMM_DDR2 + #define PSC_RB_UDIMM_DDR3 MemAGetPsCfgURb3, + #define PSC_RB_RDIMM_DDR2 + #define PSC_RB_RDIMM_DDR3 + #define PSC_RB_SODIMM_DDR2 + #define PSC_RB_SODIMM_DDR3 MemAGetPsCfgSRb3, + #endif + #if OPTION_MEMCTLR_DA + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_DA_UDIMM_DDR2 //MemAGetPsCfgUDr2 + #else + #define PSC_DA_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DA_UDIMM_DDR3 MemAGetPsCfgUDA3, + #else + #define PSC_DA_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_DA_RDIMM_DDR2 + #else + #define PSC_DA_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DA_RDIMM_DDR3 + #else + #define PSC_DA_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_DA_SODIMM_DDR2 MemAGetPsCfgSDA2, + #else + #define PSC_DA_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DA_SODIMM_DDR3 MemAGetPsCfgSDA3, + #else + #define PSC_DA_SODIMM_DDR3 + #endif + #endif + #endif + #endif + + #if OPTION_MEMCTLR_HY + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_HY_UDIMM_DDR2 //MemAGetPsCfgUDr2, + #else + #define PSC_HY_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_HY_UDIMM_DDR3 MemAGetPsCfgUHy3, + #else + #define PSC_HY_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_HY_RDIMM_DDR2 + #else + #define PSC_HY_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_HY_RDIMM_DDR3 MemAGetPsCfgRHy3, + #else + #define PSC_HY_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_HY_SODIMM_DDR2 //MemAGetPsCfgSHy2, + #else + #define PSC_HY_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_HY_SODIMM_DDR3 //MemAGetPsCfgSHy3, + #else + #define PSC_HY_SODIMM_DDR3 + #endif + #endif + #endif + + #if OPTION_MEMCTLR_C32 + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_C32_UDIMM_DDR2 //MemAGetPsCfgUDr2, + #else + #define PSC_C32_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_C32_UDIMM_DDR3 MemAGetPsCfgUC32_3, + #else + #define PSC_C32_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_C32_RDIMM_DDR2 + #else + #define PSC_C32_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_C32_RDIMM_DDR3 MemAGetPsCfgRC32_3, + #else + #define PSC_C32_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_C32_SODIMM_DDR2 //MemAGetPsCfgSC32_2, + #else + #define PSC_C32_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_C32_SODIMM_DDR3 //MemAGetPsCfgSC32_3, + #else + #define PSC_C32_SODIMM_DDR3 + #endif + #endif + #endif + + #if OPTION_MEMCTLR_LN + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_LN_UDIMM_DDR2 //MemAGetPsCfgULN2, + #else + #define PSC_LN_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_LN_UDIMM_DDR3 MemAGetPsCfgULN3, + #else + #define PSC_LN_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_LN_RDIMM_DDR2 + #else + #define PSC_LN_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_LN_RDIMM_DDR3 //MemAGetPsCfgRLN3, + #else + #define PSC_LN_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_LN_SODIMM_DDR2 //MemAGetPsCfgSLN2, + #else + #define PSC_LN_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_LN_SODIMM_DDR3 MemAGetPsCfgSLN3, + #else + #define PSC_LN_SODIMM_DDR3 + #endif + #endif + #endif + + #if OPTION_MEMCTLR_OR + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_OR_UDIMM_DDR2 //MemAGetPsCfgUOr2, + #else + #define PSC_OR_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_OR_UDIMM_DDR3 //MemAGetPsCfgUOr3, + #else + #define PSC_OR_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_OR_RDIMM_DDR2 + #else + #define PSC_OR_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_OR_RDIMM_DDR3 //MemAGetPsCfgROr3, + #else + #define PSC_OR_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_OR_SODIMM_DDR2 //MemAGetPsCfgSOr2, + #else + #define PSC_OR_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_OR_SODIMM_DDR3 //MemAGetPsCfgSOr3, + #else + #define PSC_OR_SODIMM_DDR3 + #endif + #endif + #endif + + #if OPTION_MEMCTLR_ON + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_ON_UDIMM_DDR2 //MemAGetPsCfgUON2, + #else + #define PSC_ON_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_ON_UDIMM_DDR3 MemAGetPsCfgUON3, + #else + #define PSC_ON_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_ON_RDIMM_DDR2 + #else + #define PSC_ON_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_ON_RDIMM_DDR3 //MemAGetPsCfgRON3, + #else + #define PSC_ON_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_ON_SODIMM_DDR2 //MemAGetPsCfgSON2, + #else + #define PSC_ON_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_ON_SODIMM_DDR3 MemAGetPsCfgSON3, + #else + #define PSC_ON_SODIMM_DDR3 + #endif + #endif + #endif + + /*---------------------------------------------------------------------- + * DEFAULT PSCFG DEFINITIONS + * + *---------------------------------------------------------------------- + */ + + #ifndef PSC_DR_UDIMM_DDR2 + #define PSC_DR_UDIMM_DDR2 + #endif + #ifndef PSC_DR_RDIMM_DDR2 + #define PSC_DR_RDIMM_DDR2 + #endif + #ifndef PSC_DR_SODIMM_DDR2 + #define PSC_DR_SODIMM_DDR2 + #endif + #ifndef PSC_DR_UDIMM_DDR3 + #define PSC_DR_UDIMM_DDR3 + #endif + #ifndef PSC_DR_RDIMM_DDR3 + #define PSC_DR_RDIMM_DDR3 + #endif + #ifndef PSC_DR_SODIMM_DDR3 + #define PSC_DR_SODIMM_DDR3 + #endif + #ifndef PSC_RB_UDIMM_DDR2 + #define PSC_RB_UDIMM_DDR2 + #endif + #ifndef PSC_RB_RDIMM_DDR2 + #define PSC_RB_RDIMM_DDR2 + #endif + #ifndef PSC_RB_SODIMM_DDR2 + #define PSC_RB_SODIMM_DDR2 + #endif + #ifndef PSC_RB_UDIMM_DDR3 + #define PSC_RB_UDIMM_DDR3 + #endif + #ifndef PSC_RB_RDIMM_DDR3 + #define PSC_RB_RDIMM_DDR3 + #endif + #ifndef PSC_RB_SODIMM_DDR3 + #define PSC_RB_SODIMM_DDR3 + #endif + #ifndef PSC_DA_UDIMM_DDR2 + #define PSC_DA_UDIMM_DDR2 + #endif + #ifndef PSC_DA_RDIMM_DDR2 + #define PSC_DA_RDIMM_DDR2 + #endif + #ifndef PSC_DA_SODIMM_DDR2 + #define PSC_DA_SODIMM_DDR2 + #endif + #ifndef PSC_DA_UDIMM_DDR3 + #define PSC_DA_UDIMM_DDR3 + #endif + #ifndef PSC_DA_RDIMM_DDR3 + #define PSC_DA_RDIMM_DDR3 + #endif + #ifndef PSC_DA_SODIMM_DDR3 + #define PSC_DA_SODIMM_DDR3 + #endif + #ifndef PSC_NI_UDIMM_DDR2 + #define PSC_NI_UDIMM_DDR2 + #endif + #ifndef PSC_NI_RDIMM_DDR2 + #define PSC_NI_RDIMM_DDR2 + #endif + #ifndef PSC_NI_SODIMM_DDR2 + #define PSC_NI_SODIMM_DDR2 + #endif + #ifndef PSC_NI_UDIMM_DDR3 + #define PSC_NI_UDIMM_DDR3 + #endif + #ifndef PSC_NI_RDIMM_DDR3 + #define PSC_NI_RDIMM_DDR3 + #endif + #ifndef PSC_NI_SODIMM_DDR3 + #define PSC_NI_SODIMM_DDR3 + #endif + #ifndef PSC_PH_UDIMM_DDR2 + #define PSC_PH_UDIMM_DDR2 + #endif + #ifndef PSC_PH_RDIMM_DDR2 + #define PSC_PH_RDIMM_DDR2 + #endif + #ifndef PSC_PH_SODIMM_DDR2 + #define PSC_PH_SODIMM_DDR2 + #endif + #ifndef PSC_PH_UDIMM_DDR3 + #define PSC_PH_UDIMM_DDR3 + #endif + #ifndef PSC_PH_RDIMM_DDR3 + #define PSC_PH_RDIMM_DDR3 + #endif + #ifndef PSC_PH_SODIMM_DDR3 + #define PSC_PH_SODIMM_DDR3 + #endif + #ifndef PSC_HY_UDIMM_DDR2 + #define PSC_HY_UDIMM_DDR2 + #endif + #ifndef PSC_HY_RDIMM_DDR2 + #define PSC_HY_RDIMM_DDR2 + #endif + #ifndef PSC_HY_SODIMM_DDR2 + #define PSC_HY_SODIMM_DDR2 + #endif + #ifndef PSC_HY_UDIMM_DDR3 + #define PSC_HY_UDIMM_DDR3 + #endif + #ifndef PSC_HY_RDIMM_DDR3 + #define PSC_HY_RDIMM_DDR3 + #endif + #ifndef PSC_HY_SODIMM_DDR3 + #define PSC_HY_SODIMM_DDR3 + #endif + #ifndef PSC_LN_UDIMM_DDR2 + #define PSC_LN_UDIMM_DDR2 + #endif + #ifndef PSC_LN_RDIMM_DDR2 + #define PSC_LN_RDIMM_DDR2 + #endif + #ifndef PSC_LN_SODIMM_DDR2 + #define PSC_LN_SODIMM_DDR2 + #endif + #ifndef PSC_LN_UDIMM_DDR3 + #define PSC_LN_UDIMM_DDR3 + #endif + #ifndef PSC_LN_RDIMM_DDR3 + #define PSC_LN_RDIMM_DDR3 + #endif + #ifndef PSC_LN_SODIMM_DDR3 + #define PSC_LN_SODIMM_DDR3 + #endif + #ifndef PSC_OR_UDIMM_DDR2 + #define PSC_OR_UDIMM_DDR2 + #endif + #ifndef PSC_OR_RDIMM_DDR2 + #define PSC_OR_RDIMM_DDR2 + #endif + #ifndef PSC_OR_SODIMM_DDR2 + #define PSC_OR_SODIMM_DDR2 + #endif + #ifndef PSC_OR_UDIMM_DDR3 + #define PSC_OR_UDIMM_DDR3 + #endif + #ifndef PSC_OR_RDIMM_DDR3 + #define PSC_OR_RDIMM_DDR3 + #endif + #ifndef PSC_OR_SODIMM_DDR3 + #define PSC_OR_SODIMM_DDR3 + #endif + #ifndef PSC_C32_UDIMM_DDR3 + #define PSC_C32_UDIMM_DDR3 + #endif + #ifndef PSC_C32_RDIMM_DDR3 + #define PSC_C32_RDIMM_DDR3 + #endif + #ifndef PSC_ON_UDIMM_DDR2 + #define PSC_ON_UDIMM_DDR2 + #endif + #ifndef PSC_ON_RDIMM_DDR2 + #define PSC_ON_RDIMM_DDR2 + #endif + #ifndef PSC_ON_SODIMM_DDR2 + #define PSC_ON_SODIMM_DDR2 + #endif + #ifndef PSC_ON_UDIMM_DDR3 + #define PSC_ON_UDIMM_DDR3 + #endif + #ifndef PSC_ON_RDIMM_DDR3 + #define PSC_ON_RDIMM_DDR3 + #endif + #ifndef PSC_ON_SODIMM_DDR3 + #define PSC_ON_SODIMM_DDR3 + #endif + + MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { + PSC_DR_UDIMM_DDR2 + PSC_DR_RDIMM_DDR2 + PSC_DR_SODIMM_DDR2 + PSC_DR_UDIMM_DDR3 + PSC_DR_RDIMM_DDR3 + PSC_DR_SODIMM_DDR3 + PSC_RB_UDIMM_DDR3 + PSC_RB_SODIMM_DDR3 + PSC_DA_SODIMM_DDR2 + PSC_DA_UDIMM_DDR3 + PSC_DA_SODIMM_DDR3 + PSC_NI_UDIMM_DDR3 + PSC_NI_SODIMM_DDR3 + PSC_PH_UDIMM_DDR3 + PSC_PH_SODIMM_DDR3 + PSC_HY_UDIMM_DDR3 + PSC_HY_RDIMM_DDR3 + PSC_HY_SODIMM_DDR3 + PSC_LN_UDIMM_DDR3 + PSC_LN_RDIMM_DDR3 + PSC_LN_SODIMM_DDR3 + PSC_OR_UDIMM_DDR3 + PSC_OR_RDIMM_DDR3 + PSC_OR_SODIMM_DDR3 + PSC_C32_UDIMM_DDR3 + PSC_C32_RDIMM_DDR3 + PSC_ON_UDIMM_DDR3 + PSC_ON_RDIMM_DDR3 + PSC_ON_SODIMM_DDR3 + NULL + }; + CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*)); +/* SIZE_OF_PLATFORM is not defined when the preprocessor runs + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS + #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES + #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES + #endif +#endif + + /*--------------------------------------------------------------------------------------------------- + * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION + * + * + *--------------------------------------------------------------------------------------------------- + */ + #define MEM_PSC_FLOW_BLOCK_END NULL + #define PSC_TBL_END NULL + #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue + + #if OPTION_MEMCTLR_OR + #if OPTION_UDIMMS + #if OPTION_AM3_SOCKET_SUPPORT + extern PSC_TBL_ENTRY MaxFreqTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 &MaxFreqTblEntUAM3, + extern PSC_TBL_ENTRY DramTermTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &DramTermTblEntUAM3, + extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &OdtPat1DTblEntUAM3, + extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &OdtPat2DTblEntUAM3, + extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &OdtPat3DTblEntUAM3, + extern PSC_TBL_ENTRY SAOTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_SAO_AM3 &SAOTblEntUAM3, + extern PSC_TBL_ENTRY ClkDisMapEntUAM3; + #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3, + #endif + #if OPTION_C32_SOCKET_SUPPORT + extern PSC_TBL_ENTRY MaxFreqTblEntUC32; + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 &MaxFreqTblEntUC32, + extern PSC_TBL_ENTRY DramTermTblEntUC32; + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 &DramTermTblEntUC32, + extern PSC_TBL_ENTRY OdtPat1DTblEntUC32; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntUC32, + extern PSC_TBL_ENTRY OdtPat2DTblEntUC32; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntUC32, + extern PSC_TBL_ENTRY OdtPat3DTblEntUC32; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntUC32, + extern PSC_TBL_ENTRY SAOTblEntUC32; + #define PSC_TBL_OR_UDIMM3_SAO_C32 &SAOTblEntUC32, + extern PSC_TBL_ENTRY ClkDisMapEntUC32; + #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32, + extern PSC_TBL_ENTRY ClkDisMap3DEntUC32; + #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32, + #endif + #if OPTION_G34_SOCKET_SUPPORT + extern PSC_TBL_ENTRY MaxFreqTblEntUG34; + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 &MaxFreqTblEntUG34, + extern PSC_TBL_ENTRY DramTermTblEntUG34; + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 &DramTermTblEntUG34, + extern PSC_TBL_ENTRY OdtPat1DTblEntUG34; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntUG34, + extern PSC_TBL_ENTRY OdtPat2DTblEntUG34; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntUG34, + extern PSC_TBL_ENTRY OdtPat3DTblEntUG34; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntUG34, + extern PSC_TBL_ENTRY SAOTblEntUG34; + #define PSC_TBL_OR_UDIMM3_SAO_G34 &SAOTblEntUG34, + extern PSC_TBL_ENTRY ClkDisMapEntUG34; + #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34, + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_C32_SOCKET_SUPPORT + extern PSC_TBL_ENTRY MaxFreqTblEntRC32; + #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 &MaxFreqTblEntRC32, + extern PSC_TBL_ENTRY DramTermTblEntRC32; + #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 &DramTermTblEntRC32, + extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntRC32, + extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntRC32, + extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntRC32, + extern PSC_TBL_ENTRY SAOTblEntRC32; + #define PSC_TBL_OR_RDIMM3_SAO_C32 &SAOTblEntRC32, + extern PSC_TBL_ENTRY RC2IBTTblEntRC32; + #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 &RC2IBTTblEntRC32, + extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32; + #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 &RC10OpSpdTblEntRC32, + extern PSC_TBL_ENTRY ClkDisMapEntRC32; + #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32, + #endif + #if OPTION_G34_SOCKET_SUPPORT + extern PSC_TBL_ENTRY MaxFreqTblEntRG34; + #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 &MaxFreqTblEntRG34, + extern PSC_TBL_ENTRY DramTermTblEntRG34; + #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 &DramTermTblEntRG34, + extern PSC_TBL_ENTRY OdtPat1DTblEntRG34; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntRG34, + extern PSC_TBL_ENTRY OdtPat2DTblEntRG34; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntRG34, + extern PSC_TBL_ENTRY OdtPat3DTblEntRG34; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntRG34, + extern PSC_TBL_ENTRY SAOTblEntRG34; + #define PSC_TBL_OR_RDIMM3_SAO_G34 &SAOTblEntRG34, + extern PSC_TBL_ENTRY RC2IBTTblEntRG34; + #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 &RC2IBTTblEntRG34, + extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34; + #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 &RC10OpSpdTblEntRG34, + extern PSC_TBL_ENTRY ClkDisMapEntRG34; + #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34, + #endif + #endif + //#if OPTION_SODIMMS + //#endif + //#if OPTION_LRDIMMS + // #if OPTION_C32_SOCKET_SUPPORT + // extern PSC_TBL_ENTRY MaxFreqTblEntLRC32; + // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 &MaxFreqTblEntLRC32, + // extern PSC_TBL_ENTRY DramTermTblEntLRC32; + // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 &DramTermTblEntLRC32, + // extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; + // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntLRC32, + // extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; + // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntLRC32, + // extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; + // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntLRC32, + // extern PSC_TBL_ENTRY SAOTblEntRC32; + // #define PSC_TBL_OR_LRDIMM3_SAO_C32 &SAOTblEntLRC32, + // extern PSC_TBL_ENTRY IBTTblEntLRC32; + // #define PSC_TBL_OR_LRDIMM3_IBT_C32 &IBTTblEntLRC32, + // extern PSC_TBL_ENTRY ClkDisMapEntLRC32; + // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32, + // #endif + // #if OPTION_G34_SOCKET_SUPPORT + // extern PSC_TBL_ENTRY MaxFreqTblEntLRG34; + // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 &MaxFreqTblEntLRG34, + // extern PSC_TBL_ENTRY DramTermTblEntLRG34; + // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 &DramTermTblEntLRG34, + // extern PSC_TBL_ENTRY OdtPat1DTblEntRG34; + // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntLRG34, + // extern PSC_TBL_ENTRY OdtPat2DTblEntRG34; + // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntLRG34, + // extern PSC_TBL_ENTRY OdtPat3DTblEntRG34; + // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntLRG34, + // extern PSC_TBL_ENTRY SAOTblEntRG34; + // #define PSC_TBL_OR_LRDIMM3_SAO_G34 &SAOTblEntLRG34, + // extern PSC_TBL_ENTRY IBTTblEntLRG34; + // #define PSC_TBL_OR_LRDIMM3_IBT_G34 &IBTTblEntLRG34, + // extern PSC_TBL_ENTRY ClkDisMapEntLRG34; + // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34, + // #endif + //#endif + extern PSC_TBL_ENTRY MR0WrTblEntry; + #define PSC_TBL_OR_MR0_WR &MR0WrTblEntry, + extern PSC_TBL_ENTRY MR0CLTblEntry; + #define PSC_TBL_OR_MR0_CL &MR0CLTblEntry, + extern PSC_TBL_ENTRY OrDdr3CKETriEnt; + #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt, + extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt; + #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt, + extern PSC_TBL_ENTRY OrDdr3ODTTriEnt; + #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt, + extern PSC_TBL_ENTRY OrUDdr3CSTriEnt; + #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt, + extern PSC_TBL_ENTRY OrDdr3CSTriEnt; + #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt, + extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt; + #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt, + extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt; + #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt, + + #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3 + #define PSC_TBL_OR_UDIMM3_SAO_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_SAO_C32 + #define PSC_TBL_OR_UDIMM3_SAO_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_SAO_G34 + #define PSC_TBL_OR_UDIMM3_SAO_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 + #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 + #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 + #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 + #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 + #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 + #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3 + #define PSC_TBL_OR_RDIMM3_SAO_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_SAO_C32 + #define PSC_TBL_OR_RDIMM3_SAO_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_SAO_G34 + #define PSC_TBL_OR_RDIMM3_SAO_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3 + #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32 + #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34 + #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 + #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 + #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 + #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 + #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 + #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 + #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 + #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32 + #define PSC_TBL_OR_LRDIMM3_SAO_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34 + #define PSC_TBL_OR_LRDIMM3_SAO_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32 + #define PSC_TBL_OR_LRDIMM3_IBT_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34 + #define PSC_TBL_OR_LRDIMM3_IBT_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 + #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32 + #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 + #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34 + #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32 + #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34 + #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 + #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 + #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 + #endif + + PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = { + PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 + PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 + PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 + PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 + PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 + PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 + PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 + PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = { + PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 + PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 + PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 + PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 + PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 + PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 + PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 + PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = { + PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 + PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 + PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 + PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 + PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 + PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 + PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 + PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 + PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 + PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 + PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 + PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 + PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 + PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 + PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 + PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 + PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 + PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 + PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 + PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 + PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 + PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 + PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 + PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = { + PSC_TBL_OR_UDIMM3_SAO_AM3 + PSC_TBL_OR_UDIMM3_SAO_C32 + PSC_TBL_OR_UDIMM3_SAO_G34 + PSC_TBL_OR_RDIMM3_SAO_AM3 + PSC_TBL_OR_RDIMM3_SAO_C32 + PSC_TBL_OR_RDIMM3_SAO_G34 + PSC_TBL_OR_LRDIMM3_SAO_C32 + PSC_TBL_OR_LRDIMM3_SAO_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = { + PSC_TBL_OR_MR0_WR + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = { + PSC_TBL_OR_MR0_CL + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = { + PSC_TBL_OR_RDIMM3_RC2IBT_AM3 + PSC_TBL_OR_RDIMM3_RC2IBT_C32 + PSC_TBL_OR_RDIMM3_RC2IBT_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = { + PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 + PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 + PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = { + PSC_TBL_OR_LRDIMM3_IBT_C32 + PSC_TBL_OR_LRDIMM3_IBT_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = { + PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 + PSC_TBL_OR_UDIMM3_CLK_DIS_C32 + PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 + PSC_TBL_OR_UDIMM3_CLK_DIS_G34 + PSC_TBL_OR_RDIMM3_CLK_DIS_C32 + PSC_TBL_OR_RDIMM3_CLK_DIS_G34 + PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 + PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 + PSC_TBL_OR_CKE_TRI + PSC_TBL_OR_ODT_TRI_3D + PSC_TBL_OR_ODT_TRI + PSC_TBL_OR_LRDIMM3_ODT_TRI_3D + PSC_TBL_OR_LRDIMM3_ODT_TRI + PSC_TBL_OR_UDIMM3_CS_TRI + PSC_TBL_OR_CS_TRI + PSC_TBL_END + }; + + MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = { + (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR, + NULL, + NULL, + (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR + }; + + extern MEM_PSC_FLOW MemPGetMaxFreqSupported; + #define PSC_FLOW_OR_MAX_FREQ MemPGetMaxFreqSupported + extern MEM_PSC_FLOW MemPGetRttNomWr; + #define PSC_FLOW_OR_DRAM_TERM MemPGetRttNomWr + extern MEM_PSC_FLOW MemPGetODTPattern; + #define PSC_FLOW_OR_ODT_PATTERN MemPGetODTPattern + extern MEM_PSC_FLOW MemPGetSAO; + #define PSC_FLOW_OR_SAO MemPGetSAO + extern MEM_PSC_FLOW MemPGetMR0WrCL; + #define PSC_FLOW_OR_MR0_WRCL MemPGetMR0WrCL + #if OPTION_RDIMMS + extern MEM_PSC_FLOW MemPGetRC2IBT; + #define PSC_FLOW_OR_RC2_IBT MemPGetRC2IBT + extern MEM_PSC_FLOW MemPGetRC10OpSpd; + #define PSC_FLOW_OR_RC10_OPSPD MemPGetRC10OpSpd + #endif + //#if OPTION_LRDIMMS + //extern MEM_PSC_FLOW MemPGetLRIBT; + //#define PSC_FLOW_OR_LR_IBT MemPGetLRIBT + //extern MEM_PSC_FLOW MemPGetLRNPR; + //#define PSC_FLOW_OR_LR_NPR MemPGetLRNPR + //extern MEM_PSC_FLOW MemPGetLRNLR; + //#define PSC_FLOW_OR_LR_NLR MemPGetLRNLR + //#endif + #ifndef PSC_FLOW_OR_MAX_FREQ + #define PSC_FLOW_OR_MAX_FREQ MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_DRAM_TERM + #define PSC_FLOW_OR_DRAM_TERM MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_ODT_PATTERN + #define PSC_FLOW_OR_ODT_PATTERN MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_SAO + #define PSC_FLOW_OR_SAO MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_MR0_WRCL + #define PSC_FLOW_OR_MR0_WRCL MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_RC2_IBT + #define PSC_FLOW_OR_RC2_IBT MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_RC10_OPSPD + #define PSC_FLOW_OR_RC10_OPSPD MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_LR_IBT + #define PSC_FLOW_OR_LR_IBT MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_LR_NPR + #define PSC_FLOW_OR_LR_NPR MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_LR_NLR + #define PSC_FLOW_OR_LR_NLR MEM_PSC_FLOW_DEFTRUE + #endif + MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = { + &memPSCTblBlockOr, + PSC_FLOW_OR_MAX_FREQ, + PSC_FLOW_OR_DRAM_TERM, + PSC_FLOW_OR_ODT_PATTERN, + PSC_FLOW_OR_SAO, + PSC_FLOW_OR_MR0_WRCL, + PSC_FLOW_OR_RC2_IBT, + PSC_FLOW_OR_RC10_OPSPD, + PSC_FLOW_OR_LR_IBT, + PSC_FLOW_OR_LR_NPR, + PSC_FLOW_OR_LR_NLR + }; + #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR, + #else + #define MEM_PSC_FLOW_BLOCK_OR + #endif + + + MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { + MEM_PSC_FLOW_BLOCK_OR + MEM_PSC_FLOW_BLOCK_END + }; + + /*--------------------------------------------------------------------------------------------------- + * + * LRDIMM CONTROL + * + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_LRDIMMS == TRUE) + #if (OPTION_MEMCTLR_OR == TRUE) + extern MEM_TECH_FEAT MemTLrdimmConstructor3; + #define MEM_TECH_FEATURE_LRDIMM_INIT &MemTLrdimmConstructor3 + #else //#if (OPTION_MEMCTLR_OR == FALSE) + #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef + #endif + #else //#if (OPTION_LRDIMMS == FALSE) + #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef + #endif + MEM_TECH_LRDIMM memLrdimmSupported = { + MEM_TECH_LRDIMM_STRUCT_VERSION, + MEM_TECH_FEATURE_LRDIMM_INIT + }; +#else + /*--------------------------------------------------------------------------------------------------- + * MAIN FLOW CONTROL + * + * + *--------------------------------------------------------------------------------------------------- + */ + MEM_FLOW_CFG* memFlowControlInstalled[] = { + NULL + }; + /*--------------------------------------------------------------------------------------------------- + * NB TRAINING FLOW CONTROL + * + * + *--------------------------------------------------------------------------------------------------- + */ + OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control + NULL + }; + /*--------------------------------------------------------------------------------------------------- + * DEFAULT TECHNOLOGY BLOCK + * + * + *--------------------------------------------------------------------------------------------------- + */ + MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed + NULL + }; + + /*--------------------------------------------------------------------------------------------------- + * DEFAULT TECHNOLOGY MAP + * + * + *--------------------------------------------------------------------------------------------------- + */ + UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; + + /*--------------------------------------------------------------------------------------------------- + * DEFAULT MAIN FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + MEM_FEAT_BLOCK_MAIN MemFeatMain = { + 0 + }; + + /*--------------------------------------------------------------------------------------------------- + * DEFAULT NORTHBRIDGE SUPPORT LIST + * + * + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_DR == TRUE) + #undef MEM_NB_SUPPORT_DR + #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, + #endif + #if (OPTION_MEMCTLR_RB == TRUE) + #undef MEM_NB_SUPPORT_RB + #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, + #endif + #if (OPTION_MEMCTLR_DA == TRUE) + #undef MEM_NB_SUPPORT_DA + #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, + #endif + #if (OPTION_MEMCTLR_PH == TRUE) + #undef MEM_NB_SUPPORT_PH + #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, + #endif + #if (OPTION_MEMCTLR_HY == TRUE) + #undef MEM_NB_SUPPORT_HY + #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, + #endif + #if (OPTION_MEMCTLR_C32 == TRUE) + #undef MEM_NB_SUPPORT_C32 + #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, + #endif + #if (OPTION_MEMCTLR_LN == TRUE) + #undef MEM_NB_SUPPORT_LN + #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN }, + #endif + #if (OPTION_MEMCTLR_ON == TRUE) + #undef MEM_NB_SUPPORT_ON + #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, + #endif + #if (OPTION_MEMCTLR_OR == TRUE) + #undef MEM_NB_SUPPORT_OR + #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, + #endif + /*--------------------------------------------------------------------------------------------------- + * DEFAULT Technology Training + * + * + *--------------------------------------------------------------------------------------------------- + */ + #if OPTION_DDR2 + MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { + 0 + }; + MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { + { 0 } + }; + #endif + #if OPTION_DDR3 + MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { + 0 + }; + MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { + { 0 } + }; + #endif + /*--------------------------------------------------------------------------------------------------- + * DEFAULT Platform Specific list + * + * + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_DR == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_RB == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_DA == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_Ni == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_PH == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_LN == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_HY == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_OR == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_C32 == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_ON == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { + NULL + }; + #endif + /*---------------------------------------------------------------------- + * DEFAULT PSCFG DEFINITIONS + * + *---------------------------------------------------------------------- + */ + MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { + NULL + }; + + /*---------------------------------------------------------------------- + * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION + * + *---------------------------------------------------------------------- + */ + MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { + NULL + }; + + MEM_TECH_LRDIMM memLrdimmSupported = { + MEM_TECH_LRDIMM_STRUCT_VERSION, + NULL + }; +#endif + +/*--------------------------------------------------------------------------------------------------- + * NORTHBRIDGE SUPPORT LIST + * + * + *--------------------------------------------------------------------------------------------------- + */ +MEM_NB_SUPPORT memNBInstalled[] = { + MEM_NB_SUPPORT_RB + MEM_NB_SUPPORT_DA + MEM_NB_SUPPORT_Ni + MEM_NB_SUPPORT_PH + MEM_NB_SUPPORT_HY + MEM_NB_SUPPORT_LN + MEM_NB_SUPPORT_OR + MEM_NB_SUPPORT_C32 + MEM_NB_SUPPORT_ON + MEM_NB_SUPPORT_END +}; + +#endif // _OPTION_MEMORY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionMemoryRecoveryInstall.h new file mode 100644 index 0000000000..6d2a445b53 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionMemoryRecoveryInstall.h @@ -0,0 +1,599 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Memory + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 49896 $ @e \$Date: 2011-03-30 16:18:18 +0800 (Wed, 30 Mar 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_ +#define _OPTION_MEMORY_RECOVERY_INSTALL_H_ + +#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) + + #define MEM_REC_NB_SUPPORT_OR + + #if (OPTION_MEMCTLR_DR == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR; + #define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR, + #else + #define MEM_REC_NB_SUPPORT_DR + #endif + #if (OPTION_MEMCTLR_RB == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockRb; + #define MEM_REC_NB_SUPPORT_RB MemRecConstructNBBlockRb, + #else + #define MEM_REC_NB_SUPPORT_RB + #endif + #if (OPTION_MEMCTLR_DA == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA; + #define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA, + #else + #define MEM_REC_NB_SUPPORT_DA + #endif + #if (OPTION_MEMCTLR_NI == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockNi; + #define MEM_REC_NB_SUPPORT_NI MemRecConstructNBBlockNi, + #else + #define MEM_REC_NB_SUPPORT_NI + #endif + #if (OPTION_MEMCTLR_PH == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockPh; + #define MEM_REC_NB_SUPPORT_PH MemRecConstructNBBlockPh, + #else + #define MEM_REC_NB_SUPPORT_PH + #endif + #if (OPTION_MEMCTLR_HY == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY; + #define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY, + #else + #define MEM_REC_NB_SUPPORT_HY + #endif + #if (OPTION_MEMCTLR_C32 == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32; + #define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32, + #else + #define MEM_REC_NB_SUPPORT_C32 + #endif + #if (OPTION_MEMCTLR_LN == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN; + #define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN, + #else + #define MEM_REC_NB_SUPPORT_LN + #endif + #if (OPTION_MEMCTLR_ON == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON; + #define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON, + #else + #define MEM_REC_NB_SUPPORT_ON + #endif + + MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = { + MEM_REC_NB_SUPPORT_DR + MEM_REC_NB_SUPPORT_RB + MEM_REC_NB_SUPPORT_DA + MEM_REC_NB_SUPPORT_PH + MEM_REC_NB_SUPPORT_HY + MEM_REC_NB_SUPPORT_C32 + MEM_REC_NB_SUPPORT_LN + MEM_REC_NB_SUPPORT_OR + MEM_REC_NB_SUPPORT_ON + MEM_REC_NB_SUPPORT_NI + NULL + }; + + #define MEM_REC_TECH_CONSTRUCTOR_DDR2 + #if (OPTION_DDR3 == TRUE) + extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3; + #define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3, + #else + #define MEM_REC_TECH_CONSTRUCTOR_DDR3 + #endif + + MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { + MEM_REC_TECH_CONSTRUCTOR_DDR3 + MEM_REC_TECH_CONSTRUCTOR_DDR2 + NULL + }; + + #if OPTION_MEMCTLR_DR + #define PSC_REC_DR_UDIMM_DDR2 + #define PSC_REC_DR_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, + #define PSC_REC_DR_RDIMM_DDR2 + #define PSC_REC_DR_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, + #define PSC_REC_DR_SODIMM_DDR2 + #define PSC_REC_DR_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb, + #endif + #if ((OPTION_MEMCTLR_DA == TRUE) || (OPTION_MEMCTLR_Ni == TRUE) || (OPTION_MEMCTLR_PH == TRUE) || (OPTION_MEMCTLR_RB == TRUE)) + #define PSC_REC_DA_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, + #define PSC_REC_DA_SODIMM_DDR2 + #define PSC_REC_DA_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb, + #endif + #if OPTION_MEMCTLR_HY + #define PSC_REC_HY_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, + #define PSC_REC_HY_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, + #endif + #if OPTION_MEMCTLR_C32 + #define PSC_REC_C32_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, + #define PSC_REC_C32_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, + #endif + #if OPTION_MEMCTLR_OR + #define PSC_REC_OR_UDIMM_DDR3 //MemRecNGetPsCfgUDIMM3OR, + #define PSC_REC_OR_RDIMM_DDR3 //MemRecNGetPsCfgRDIMM3OR, + #endif + + #ifndef PSC_REC_DR_UDIMM_DDR2 + #define PSC_REC_DR_UDIMM_DDR2 + #endif + #ifndef PSC_REC_DR_UDIMM_DDR3 + #define PSC_REC_DR_UDIMM_DDR3 + #endif + #ifndef PSC_REC_DR_RDIMM_DDR2 + #define PSC_REC_DR_RDIMM_DDR2 + #endif + #ifndef PSC_REC_DR_RDIMM_DDR3 + #define PSC_REC_DR_RDIMM_DDR3 + #endif + #ifndef PSC_REC_DR_SODIMM_DDR2 + #define PSC_REC_DR_SODIMM_DDR2 + #endif + #ifndef PSC_REC_DR_SODIMM_DDR3 + #define PSC_REC_DR_SODIMM_DDR3 + #endif + #ifndef PSC_REC_DA_UDIMM_DDR3 + #define PSC_REC_DA_UDIMM_DDR3 + #endif + #ifndef PSC_REC_DA_SODIMM_DDR2 + #define PSC_REC_DA_SODIMM_DDR2 + #endif + #ifndef PSC_REC_DA_SODIMM_DDR3 + #define PSC_REC_DA_SODIMM_DDR3 + #endif + #ifndef PSC_REC_HY_UDIMM_DDR3 + #define PSC_REC_HY_UDIMM_DDR3 + #endif + #ifndef PSC_REC_HY_RDIMM_DDR3 + #define PSC_REC_HY_RDIMM_DDR3 + #endif + #ifndef PSC_REC_C32_UDIMM_DDR3 + #define PSC_REC_C32_UDIMM_DDR3 + #endif + #ifndef PSC_REC_C32_RDIMM_DDR3 + #define PSC_REC_C32_RDIMM_DDR3 + #endif + #ifndef PSC_REC_OR_UDIMM_DDR3 + #define PSC_REC_OR_UDIMM_DDR3 + #endif + #ifndef PSC_REC_OR_RDIMM_DDR3 + #define PSC_REC_OR_RDIMM_DDR3 + #endif + + MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = { + PSC_REC_DR_UDIMM_DDR2 + PSC_REC_DR_RDIMM_DDR2 + PSC_REC_DR_SODIMM_DDR2 + PSC_REC_DR_UDIMM_DDR3 + PSC_REC_DR_RDIMM_DDR3 + PSC_REC_DR_SODIMM_DDR3 + PSC_REC_DA_SODIMM_DDR2 + PSC_REC_DA_UDIMM_DDR3 + PSC_REC_DA_SODIMM_DDR3 + PSC_REC_HY_UDIMM_DDR3 + PSC_REC_HY_RDIMM_DDR3 + PSC_REC_C32_UDIMM_DDR3 + PSC_REC_C32_RDIMM_DDR3 + PSC_REC_OR_UDIMM_DDR3 + PSC_REC_OR_RDIMM_DDR3 + NULL + }; + + /*--------------------------------------------------------------------------------------------------- + * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION + * + * + *--------------------------------------------------------------------------------------------------- + */ + #define MEM_PSC_REC_FLOW_BLOCK_END NULL + #define PSC_REC_TBL_END NULL + #define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue + + #if OPTION_MEMCTLR_OR + #if OPTION_UDIMMS + #if OPTION_AM3_SOCKET_SUPPORT + extern PSC_TBL_ENTRY RecDramTermTblEntUAM3; + #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &RecDramTermTblEntUAM3, + extern PSC_TBL_ENTRY RecOdtPat1DTblEntUAM3; + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &RecOdtPat1DTblEntUAM3, + extern PSC_TBL_ENTRY RecOdtPat2DTblEntUAM3; + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &RecOdtPat2DTblEntUAM3, + extern PSC_TBL_ENTRY RecOdtPat3DTblEntUAM3; + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &RecOdtPat3DTblEntUAM3, + extern PSC_TBL_ENTRY RecSAOTblEntUAM3; + #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3 &RecSAOTblEntUAM3, + #endif + #if OPTION_C32_SOCKET_SUPPORT + extern PSC_TBL_ENTRY RecDramTermTblEntUC32; + #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 &RecDramTermTblEntUC32, + extern PSC_TBL_ENTRY RecOdtPat1DTblEntUC32; + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &RecOdtPat1DTblEntUC32, + extern PSC_TBL_ENTRY RecOdtPat2DTblEntUC32; + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &RecOdtPat2DTblEntUC32, + extern PSC_TBL_ENTRY RecOdtPat3DTblEntUC32; + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &RecOdtPat3DTblEntUC32, + extern PSC_TBL_ENTRY RecSAOTblEntUC32; + #define PSC_REC_TBL_OR_UDIMM3_SAO_C32 &RecSAOTblEntUC32, + #endif + #if OPTION_G34_SOCKET_SUPPORT + extern PSC_TBL_ENTRY RecDramTermTblEntUG34; + #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 &RecDramTermTblEntUG34, + extern PSC_TBL_ENTRY RecOdtPat1DTblEntUG34; + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &RecOdtPat1DTblEntUG34, + extern PSC_TBL_ENTRY RecOdtPat2DTblEntUG34; + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &RecOdtPat2DTblEntUG34, + extern PSC_TBL_ENTRY RecOdtPat3DTblEntUG34; + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &RecOdtPat3DTblEntUG34, + extern PSC_TBL_ENTRY RecSAOTblEntUG34; + #define PSC_REC_TBL_OR_UDIMM3_SAO_G34 &RecSAOTblEntUG34, + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_C32_SOCKET_SUPPORT + extern PSC_TBL_ENTRY RecDramTermTblEntRC32; + #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 &RecDramTermTblEntRC32, + extern PSC_TBL_ENTRY RecOdtPat1DTblEntRC32; + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &RecOdtPat1DTblEntRC32, + extern PSC_TBL_ENTRY RecOdtPat2DTblEntRC32; + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &RecOdtPat2DTblEntRC32, + extern PSC_TBL_ENTRY RecOdtPat3DTblEntRC32; + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &RecOdtPat3DTblEntRC32, + extern PSC_TBL_ENTRY RecSAOTblEntRC32; + #define PSC_REC_TBL_OR_RDIMM3_SAO_C32 &RecSAOTblEntRC32, + extern PSC_TBL_ENTRY RecRC2IBTTblEntRC32; + #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 &RecRC2IBTTblEntRC32, + #endif + #if OPTION_G34_SOCKET_SUPPORT + extern PSC_TBL_ENTRY RecDramTermTblEntRG34; + #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 &RecDramTermTblEntRG34, + extern PSC_TBL_ENTRY RecOdtPat1DTblEntRG34; + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &RecOdtPat1DTblEntRG34, + extern PSC_TBL_ENTRY RecOdtPat2DTblEntRG34; + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &RecOdtPat2DTblEntRG34, + extern PSC_TBL_ENTRY RecOdtPat3DTblEntRG34; + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &RecOdtPat3DTblEntRG34, + extern PSC_TBL_ENTRY RecSAOTblEntRG34; + #define PSC_REC_TBL_OR_RDIMM3_SAO_G34 &RecSAOTblEntRG34, + extern PSC_TBL_ENTRY RecRC2IBTTblEntRG34; + #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 &RecRC2IBTTblEntRG34, + #endif + #endif + //#if OPTION_SODIMMS + //#endif + //#if OPTION_LRDIMMS + //#endif + extern PSC_TBL_ENTRY RecMR0WrTblEntry; + #define PSC_REC_TBL_OR_MR0_WR &RecMR0WrTblEntry, + extern PSC_TBL_ENTRY RecMR0CLTblEntry; + #define PSC_REC_TBL_OR_MR0_CL &RecMR0CLTblEntry, + + #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 + #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 + #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 + #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 + #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_AM3 + #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_C32 + #define PSC_REC_TBL_OR_UDIMM3_SAO_C32 + #endif + #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_G34 + #define PSC_REC_TBL_OR_UDIMM3_SAO_G34 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3 + #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 + #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 + #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 + #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_AM3 + #define PSC_REC_TBL_OR_RDIMM3_SAO_AM3 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_C32 + #define PSC_REC_TBL_OR_RDIMM3_SAO_C32 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_G34 + #define PSC_REC_TBL_OR_RDIMM3_SAO_G34 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3 + #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 + #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 + #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3 + #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32 + #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32 + #endif + #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34 + #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34 + #endif + + PSC_TBL_ENTRY* memRecPSCTblDramTermArrayOR[] = { + PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 + PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 + PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 + PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3 + PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 + PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 + PSC_REC_TBL_END + }; + + PSC_TBL_ENTRY* memRecPSCTblODTPatArrayOR[] = { + PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 + PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 + PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 + PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 + PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 + PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 + PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 + PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 + PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 + PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 + PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 + PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 + PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 + PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 + PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 + PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 + PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 + PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 + PSC_REC_TBL_END + }; + + PSC_TBL_ENTRY* memRecPSCTblSAOArrayOR[] = { + PSC_REC_TBL_OR_UDIMM3_SAO_AM3 + PSC_REC_TBL_OR_UDIMM3_SAO_C32 + PSC_REC_TBL_OR_UDIMM3_SAO_G34 + PSC_REC_TBL_OR_RDIMM3_SAO_AM3 + PSC_REC_TBL_OR_RDIMM3_SAO_C32 + PSC_REC_TBL_OR_RDIMM3_SAO_G34 + PSC_REC_TBL_END + }; + + PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayOR[] = { + PSC_REC_TBL_OR_MR0_WR + PSC_REC_TBL_END + }; + + PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayOR[] = { + PSC_REC_TBL_OR_MR0_CL + PSC_REC_TBL_END + }; + + PSC_TBL_ENTRY* memRecPSCTblRC2IBTArrayOR[] = { + PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3 + PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 + PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 + PSC_REC_TBL_END + }; + + MEM_PSC_TABLE_BLOCK memRecPSCTblBlockOr = { + NULL, + (PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayOR, + (PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayOR, + (PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayOR, + (PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayOR, + (PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayOR, + (PSC_TBL_ENTRY **)&memRecPSCTblRC2IBTArrayOR, + NULL, + NULL, + NULL, + NULL, + NULL + }; + + extern MEM_PSC_FLOW MemPRecGetRttNomWr; + #define PSC_REC_FLOW_OR_DRAM_TERM MemPRecGetRttNomWr + extern MEM_PSC_FLOW MemPRecGetODTPattern; + #define PSC_REC_FLOW_OR_ODT_PATTERN MemPRecGetODTPattern + extern MEM_PSC_FLOW MemPRecGetSAO; + #define PSC_REC_FLOW_OR_SAO MemPRecGetSAO + extern MEM_PSC_FLOW MemPRecGetMR0WrCL; + #define PSC_REC_FLOW_OR_MR0_WRCL MemPRecGetMR0WrCL + #if OPTION_RDIMMS + extern MEM_PSC_FLOW MemPRecGetRC2IBT; + #define PSC_REC_FLOW_OR_RC2_IBT MemPRecGetRC2IBT + #endif + //#if OPTION_LRDIMMS + extern MEM_PSC_FLOW MemPRecGetLRIBT; + #define PSC_REC_FLOW_OR_LR_IBT MemPRecGetLRIBT + extern MEM_PSC_FLOW MemPRecGetLRNPR; + #define PSC_REC_FLOW_OR_LR_NPR MemPRecGetLRNPR + extern MEM_PSC_FLOW MemPRecGetLRNLR; + #define PSC_REC_FLOW_OR_LR_NLR MemPRecGetLRNLR + //#endif + #ifndef PSC_REC_FLOW_OR_DRAM_TERM + #define PSC_REC_FLOW_OR_DRAM_TERM MEM_REC_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_REC_FLOW_OR_ODT_PATTERN + #define PSC_REC_FLOW_OR_ODT_PATTERN MEM_REC_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_REC_FLOW_OR_SAO + #define PSC_REC_FLOW_OR_SAO MEM_REC_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_REC_FLOW_OR_MR0_WRCL + #define PSC_REC_FLOW_OR_MR0_WRCL MEM_REC_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_REC_FLOW_OR_RC2_IBT + #define PSC_REC_FLOW_OR_RC2_IBT MEM_REC_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_REC_FLOW_OR_LR_IBT + #define PSC_REC_FLOW_OR_LR_IBT MEM_REC_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_REC_FLOW_OR_LR_NPR + #define PSC_REC_FLOW_OR_LR_NPR MEM_REC_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_REC_FLOW_OR_LR_NLR + #define PSC_REC_FLOW_OR_LR_NLR MEM_REC_PSC_FLOW_DEFTRUE + #endif + MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowOR = { + &memRecPSCTblBlockOr, + NULL, + PSC_REC_FLOW_OR_DRAM_TERM, + PSC_REC_FLOW_OR_ODT_PATTERN, + PSC_REC_FLOW_OR_SAO, + PSC_REC_FLOW_OR_MR0_WRCL, + PSC_REC_FLOW_OR_RC2_IBT, + NULL, + PSC_REC_FLOW_OR_LR_IBT, + PSC_REC_FLOW_OR_LR_NPR, + PSC_REC_FLOW_OR_LR_NLR + }; + #define MEM_PSC_REC_FLOW_BLOCK_OR &memRecPlatSpecFlowOR, + #else + #define MEM_PSC_REC_FLOW_BLOCK_OR + #endif + + MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = { + MEM_PSC_REC_FLOW_BLOCK_OR + MEM_PSC_REC_FLOW_BLOCK_END + }; + +#else + /*--------------------------------------------------------------------------------------------------- + * DEFAULT TECHNOLOGY BLOCK + * + * + *--------------------------------------------------------------------------------------------------- + */ + MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { // Types of technology installed + NULL + }; + /*--------------------------------------------------------------------------------------------------- + * DEFAULT NORTHBRIDGE SUPPORT LIST + * + * + *--------------------------------------------------------------------------------------------------- + */ + MEM_NB_SUPPORT* MemRecNBInstalled[] = { + NULL + }; + /*---------------------------------------------------------------------- + * DEFAULT PSCFG DEFINITIONS + * + *---------------------------------------------------------------------- + */ + MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = { + NULL + }; + /*---------------------------------------------------------------------- + * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION + * + *---------------------------------------------------------------------- + */ + MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = { + NULL + }; +#endif +#endif // _OPTION_MEMORY_RECOVERY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionMsgBasedC1eInstall.h new file mode 100644 index 0000000000..7476e16358 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionMsgBasedC1eInstall.h @@ -0,0 +1,116 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Message-Based C1e + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_ +#define _OPTION_MSG_BASED_C1E_INSTALL_H_ + +#include "cpuMsgBasedC1e.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_MSG_BASED_C1E_FEAT +#define F10_MSG_BASED_C1E_SUPPORT +#define F15_MSG_BASED_C1E_SUPPORT +#if OPTION_MSG_BASED_C1E == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) + + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if OPTION_FAMILY10H_HY == TRUE + #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e; + #undef OPTION_MSG_BASED_C1E_FEAT + #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, + #endif + #endif + #endif + #endif + + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e; + #undef OPTION_MSG_BASED_C1E_FEAT + #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if OPTION_FAMILY10H_HY == TRUE + #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) + extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e; + #undef F10_MSG_BASED_C1E_SUPPORT + #define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e}, + #endif + #endif + #endif + #endif + + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) + extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e; + #undef F15_MSG_BASED_C1E_SUPPORT + #define F15_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15, &F15OrMsgBasedC1e}, + #endif + #endif + #endif + + CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] = + { + F10_MSG_BASED_C1E_SUPPORT + F15_MSG_BASED_C1E_SUPPORT + {0, NULL} + }; + CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable = + { + (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &MsgBasedC1eFamilyServiceArray[0] + }; + #endif +#endif +#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionMultiSocketInstall.h new file mode 100644 index 0000000000..3c87677fe9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionMultiSocketInstall.h @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Multiple Socket Support + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_MULTISOCKET_INSTALL_H_ +#define _OPTION_MULTISOCKET_INSTALL_H_ + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#ifndef OPTION_MULTISOCKET + #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" +#endif + +#if OPTION_MULTISOCKET == TRUE + OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti; + #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti + OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti; + #define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti + OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti; + #define GET_SYS_NB_COF GetSystemNbCofMulti + OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti; + #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti + OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti; + #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti + OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti; + #define GET_MIN_NB_COF GetMinNbCofMulti +#else + OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle; + #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle + OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle; + #define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle + OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle; + #define GET_SYS_NB_COF GetSystemNbCofSingle + OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle; + #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle + OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle; + #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle + OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle; + #define GET_MIN_NB_COF GetMinNbCofSingle +#endif + +/* Declare the instance of the DMI option configuration structure */ +OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = { + MULTISOCKET_STRUCT_VERSION, + GET_NUM_PM_STEPS, + CORE0_PM_TASK, + GET_SYS_NB_COF, + GET_SYS_NB_COF_UPDATE, + GET_EARLY_PM_ERRORS, + GET_MIN_NB_COF +}; + +#endif // _OPTION_MULTISOCKET_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionPreserveMailboxInstall.h new file mode 100644 index 0000000000..10ea6a74b1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionPreserveMailboxInstall.h @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Preserve Mailbox + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 50096 $ @e \$Date: 2011-04-02 06:17:10 +0800 (Sat, 02 Apr 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_ +#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_ + +#include "PreserveMailbox.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_PRESERVE_MAILBOX_FEAT +#define F10_PRESERVE_MAILBOX_SUPPORT +#define F15_PRESERVE_MAILBOX_SUPPORT + +#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) + #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE)) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox; + #undef OPTION_PRESERVE_MAILBOX_FEAT + #define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox, + #endif + #if OPTION_FAMILY10H == TRUE + CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F10PreserveMailboxRegisters [] = { + { + MAKE_SBDFO (0, 0, 0, 3, 0x168), + 0x00000FFF + }, + { + MAKE_SBDFO (0, 0, 0, 3, 0x170), + 0x00000FFF + }, + { + ILLEGAL_SBDFO, + 0 + } + }; + CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = { + 0, + TRUE, + (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F10PreserveMailboxRegisters + }; + #undef F10_PRESERVE_MAILBOX_SUPPORT + #define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices}, + #endif + #if OPTION_FAMILY15H == TRUE + CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F15PreserveMailboxRegisters [] = { + { + MAKE_SBDFO (0, 0, 0, 3, 0x168), + 0x00000FFF + }, + { + MAKE_SBDFO (0, 0, 0, 3, 0x170), + 0x00000FFF + }, + { + ILLEGAL_SBDFO, + 0 + } + }; + CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = { + 0, + TRUE, + (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F15PreserveMailboxRegisters + }; + #undef F15_PRESERVE_MAILBOX_SUPPORT + #define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices}, + #endif + CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] = + { + F10_PRESERVE_MAILBOX_SUPPORT + F15_PRESERVE_MAILBOX_SUPPORT + {0, NULL} + }; + CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable = + { + (sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &PreserveMailboxFamilyServiceArray[0] + }; +#endif + +#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionPstateInstall.h new file mode 100644 index 0000000000..7d6433db31 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionPstateInstall.h @@ -0,0 +1,254 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: PState + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_PSTATE_INSTALL_H_ +#define _OPTION_PSTATE_INSTALL_H_ + +#include "cpuPstateTables.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ + +#define F10_PSTATE_SERVICE_SUPPORT +#define F12_PSTATE_SERVICE_SUPPORT +#define F14_PSTATE_SERVICE_SUPPORT +#define F15_OR_PSTATE_SERVICE_SUPPORT +#define F15_TN_PSTATE_SERVICE_SUPPORT + + +#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) + // + //Define Pstate CPU Family service + // + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices; + #undef F10_PSTATE_SERVICE_SUPPORT + #define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices}, + #endif + #endif + + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices; + #undef F12_PSTATE_SERVICE_SUPPORT + #define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices}, + #endif + #endif + + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices; + #undef F14_PSTATE_SERVICE_SUPPORT + #define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices}, + #endif + #endif + + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #ifdef OPTION_FAMILY15H_OR + #if OPTION_FAMILY15H_OR == TRUE + extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices; + #undef F15_OR_PSTATE_SERVICE_SUPPORT + #define F15_OR_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_OR, &F15OrPstateServices}, + #endif + #endif + #ifdef OPTION_FAMILY15H_TN + #if OPTION_FAMILY15H_TN == TRUE + extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices; + #undef F15_TN_PSTATE_SERVICE_SUPPORT + #define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices}, + #endif + #endif + #endif + #endif + // + //Define ACPI Pstate objects. + // + #ifndef OPTION_ACPI_PSTATES + #error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES" + #endif + #if (OPTION_ACPI_PSTATES == TRUE) +// OPTION_SSDT_FEATURE GenerateSsdt; + #define USER_SSDT_MAIN GenerateSsdt + #ifndef OPTION_MULTISOCKET + #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" + #endif + +// OPTION_ACPI_FEATURE CreatePStateAcpiTables; + OPTION_PSTATE_GATHER PStateGatherMain; + #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)) + OPTION_PSTATE_LEVELING PStateLevelingMain; + #define USER_PSTATE_OPTION_LEVEL PStateLevelingMain + #else + OPTION_PSTATE_LEVELING PStateLevelingStub; + #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub + #endif + #if AGESA_ENTRY_INIT_LATE == TRUE + #define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables + #else +// OPTION_ACPI_FEATURE CreateAcpiTablesStub; + #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub + #endif + #if AGESA_ENTRY_INIT_POST == TRUE + #define USER_PSTATE_OPTION_GATHER PStateGatherMain + #else + OPTION_PSTATE_GATHER PStateGatherStub; + #define USER_PSTATE_OPTION_GATHER PStateGatherStub + #endif + #if CFG_ACPI_PSTATES_PPC == TRUE + #define USER_PSTATE_CFG_PPC TRUE + #else + #define USER_PSTATE_CFG_PPC FALSE + #endif + #if CFG_ACPI_PSTATES_PCT == TRUE + #define USER_PSTATE_CFG_PCT TRUE + #else + #define USER_PSTATE_CFG_PCT FALSE + #endif + #if CFG_ACPI_PSTATES_PSD == TRUE + #define USER_PSTATE_CFG_PSD TRUE + #else + #define USER_PSTATE_CFG_PSD FALSE + #endif + #if CFG_ACPI_PSTATES_PSS == TRUE + #define USER_PSTATE_CFG_PSS TRUE + #else + #define USER_PSTATE_CFG_PSS FALSE + #endif + #if CFG_ACPI_PSTATES_XPSS == TRUE + #define USER_PSTATE_CFG_XPSS TRUE + #else + #define USER_PSTATE_CFG_XPSS FALSE + #endif + + #if OPTION_IO_CSTATE == TRUE +// OPTION_ACPI_FEATURE CreateCStateAcpiTables; + #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables + #else + OPTION_ACPI_FEATURE CreateAcpiTablesStub; + #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub + #endif + #else + OPTION_SSDT_FEATURE GenerateSsdtStub; + OPTION_ACPI_FEATURE CreateAcpiTablesStub; + OPTION_PSTATE_GATHER PStateGatherStub; + OPTION_PSTATE_LEVELING PStateLevelingStub; + #define USER_SSDT_MAIN GenerateSsdtStub + #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub + #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub + #define USER_PSTATE_OPTION_GATHER PStateGatherStub + #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub + #define USER_PSTATE_CFG_PPC FALSE + #define USER_PSTATE_CFG_PCT FALSE + #define USER_PSTATE_CFG_PSD FALSE + #define USER_PSTATE_CFG_PSS FALSE + #define USER_PSTATE_CFG_XPSS FALSE + + // If ACPI Objects are disabled for PStates, we still need to check + // whether ACPI Objects are enabled for CStates + #if OPTION_IO_CSTATE == TRUE + OPTION_SSDT_FEATURE GenerateSsdt; + OPTION_PSTATE_GATHER PStateGatherMain; + OPTION_ACPI_FEATURE CreateCStateAcpiTables; + #undef USER_SSDT_MAIN + #define USER_SSDT_MAIN GenerateSsdt + #undef USER_PSTATE_OPTION_GATHER + #define USER_PSTATE_OPTION_GATHER PStateGatherMain + #undef USER_CSTATE_OPTION_MAIN + #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables + #endif + #endif +#else + OPTION_SSDT_FEATURE GenerateSsdtStub; + OPTION_ACPI_FEATURE CreateAcpiTablesStub; + OPTION_PSTATE_GATHER PStateGatherStub; + OPTION_PSTATE_LEVELING PStateLevelingStub; + #define USER_SSDT_MAIN GenerateSsdtStub + #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub + #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub + #define USER_PSTATE_OPTION_GATHER PStateGatherStub + #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub + #define USER_PSTATE_CFG_PPC FALSE + #define USER_PSTATE_CFG_PCT FALSE + #define USER_PSTATE_CFG_PSD FALSE + #define USER_PSTATE_CFG_PSS FALSE + #define USER_PSTATE_CFG_XPSS FALSE +#endif + +/* Declare the instance of the PSTATE option configuration structure */ +OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { + PSTATE_STRUCT_VERSION, + USER_PSTATE_OPTION_GATHER, + USER_PSTATE_OPTION_LEVEL +}; + +OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = { + PSTATE_STRUCT_VERSION, + USER_SSDT_MAIN, + USER_PSTATE_OPTION_MAIN, + USER_CSTATE_OPTION_MAIN, + USER_PSTATE_CFG_PPC, + USER_PSTATE_CFG_PCT, + USER_PSTATE_CFG_PSD, + USER_PSTATE_CFG_PSS, + USER_PSTATE_CFG_XPSS +}; + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] = +{ + F10_PSTATE_SERVICE_SUPPORT + F12_PSTATE_SERVICE_SUPPORT + F14_PSTATE_SERVICE_SUPPORT + F15_OR_PSTATE_SERVICE_SUPPORT + F15_TN_PSTATE_SERVICE_SUPPORT + {0, NULL} +}; +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable = +{ + (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &PstateCpuFamilyServiceArray[0] +}; +#endif // _OPTION_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionS3ScriptInstall.h new file mode 100644 index 0000000000..5b62bdf6dc --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionS3ScriptInstall.h @@ -0,0 +1,91 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: S3SCRIPT + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_S3SCRIPT_INSTALL_H_ +#define _OPTION_S3SCRIPT_INSTALL_H_ + +#include "S3SaveState.h" +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#ifndef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT FALSE //if not define assume PI not use script +#endif + +#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) + #if OPTION_S3SCRIPT == TRUE + #define P_S3_SCRIPT_INIT S3ScriptInitState + #endif +#endif + +#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + #if OPTION_S3SCRIPT == TRUE + #define P_S3_SCRIPT_RESTORE S3ScriptRestoreState + #endif +#endif + +#ifndef P_S3_SCRIPT_INIT + #define P_S3_SCRIPT_INIT S3ScriptInitStateStub +#endif + +#ifndef P_S3_SCRIPT_RESTORE + #define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub + #undef GNB_S3_DISPATCH_FUNCTION_TABLE +#endif + +#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE + #define GNB_S3_DISPATCH_FUNCTION_TABLE +#endif + +/* Declare the instance of the S3SCRIPT option configuration structure */ +S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = { + P_S3_SCRIPT_INIT, + P_S3_SCRIPT_RESTORE +}; + +S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = { + GNB_S3_DISPATCH_FUNCTION_TABLE + {0, NULL} +}; +#endif // _OPTION_S3SCRIPT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionSlitInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionSlitInstall.h new file mode 100644 index 0000000000..915e5302c4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionSlitInstall.h @@ -0,0 +1,79 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: SLIT + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_SLIT_INSTALL_H_ +#define _OPTION_SLIT_INSTALL_H_ + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#if AGESA_ENTRY_INIT_LATE == TRUE + #ifndef OPTION_SLIT + #error BLDOPT: Option not defined: "OPTION_SLIT" + #endif + #if OPTION_SLIT == TRUE + OPTION_SLIT_FEATURE GetAcpiSlitMain; + OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer; + #define USER_SLIT_OPTION GetAcpiSlitMain + #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer + #else + OPTION_SLIT_FEATURE GetAcpiSlitStub; + OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; + #define USER_SLIT_OPTION GetAcpiSlitStub + #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub + #endif +#else + OPTION_SLIT_FEATURE GetAcpiSlitStub; + OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; + #define USER_SLIT_OPTION GetAcpiSlitStub + #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub +#endif +/* Declare the instance of the SLIT option configuration structure */ +OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = { + SLIT_STRUCT_VERSION, + USER_SLIT_OPTION, + USER_SLIT_RELEASE_BUFFER +}; + +#endif // _OPTION_SLIT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionSratInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionSratInstall.h new file mode 100644 index 0000000000..273874753f --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionSratInstall.h @@ -0,0 +1,73 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: SRAT + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_SRAT_INSTALL_H_ +#define _OPTION_SRAT_INSTALL_H_ + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#if AGESA_ENTRY_INIT_LATE == TRUE + #ifndef OPTION_SRAT + #error BLDOPT: Option not defined: "OPTION_SRAT" + #endif + #if OPTION_SRAT == TRUE + OPTION_SRAT_FEATURE GetAcpiSratMain; + #define USER_SRAT_OPTION GetAcpiSratMain + #else + OPTION_SRAT_FEATURE GetAcpiSratStub; + #define USER_SRAT_OPTION GetAcpiSratStub + #endif +#else + OPTION_SRAT_FEATURE GetAcpiSratStub; + #define USER_SRAT_OPTION GetAcpiSratStub +#endif + +/* Declare the instance of the WHEA option configuration structure */ +OPTION_SRAT_CONFIGURATION OptionSratConfiguration = { + SRAT_STRUCT_VERSION, + USER_SRAT_OPTION +}; + +#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionSwC1eInstall.h new file mode 100644 index 0000000000..34886eee14 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionSwC1eInstall.h @@ -0,0 +1,80 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: SW C1e + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_SW_C1E_INSTALL_H_ +#define _OPTION_SW_C1E_INSTALL_H_ + +#include "cpuSwC1e.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_SW_C1E_FEAT +#define F10_SW_C1E_SUPPORT +#if AGESA_ENTRY_INIT_EARLY == TRUE + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e; + #undef OPTION_SW_C1E_FEAT + #define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e, + extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e; + #undef F10_SW_C1E_SUPPORT + #define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e}, + #endif + #endif + #endif + CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] = + { + F10_SW_C1E_SUPPORT + {0, NULL} + }; + CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable = + { + (sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &SwC1eFamilyServiceArray[0] + }; +#endif + +#endif // _OPTION_SW_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionWheaInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionWheaInstall.h new file mode 100644 index 0000000000..5facece353 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/OptionWheaInstall.h @@ -0,0 +1,74 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: WHEA + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _OPTION_WHEA_INSTALL_H_ +#define _OPTION_WHEA_INSTALL_H_ + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#if AGESA_ENTRY_INIT_LATE == TRUE + #ifndef OPTION_WHEA + #error BLDOPT: Option not defined: "OPTION_WHEA" + #endif + #if OPTION_WHEA == TRUE + OPTION_WHEA_FEATURE GetAcpiWheaMain; + #define USER_WHEA_OPTION GetAcpiWheaMain + #else + OPTION_WHEA_FEATURE GetAcpiWheaStub; + #define USER_WHEA_OPTION GetAcpiWheaStub + #endif + +#else + OPTION_WHEA_FEATURE GetAcpiWheaStub; + #define USER_WHEA_OPTION GetAcpiWheaStub +#endif + +/* Declare the instance of the WHEA option configuration structure */ +OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = { + WHEA_STRUCT_VERSION, + USER_WHEA_OPTION +}; + +#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h new file mode 100644 index 0000000000..1fe116a6c7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h @@ -0,0 +1,2588 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build options for a combination of package type, processor, and features. + * + * This file generates the defaults tables for the all platform solution + * combinations. The documented build options are imported from a user + * controlled file for processing. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef RUN_BROKEN_AGESA_TESTS + #define RUN_BROKEN_AGESA_TESTS 0 +#endif + +/***************************************************************************** + * + * Start processing the user options: First, set default settings + * + ****************************************************************************/ + + +VOLATILE AMD_MODULE_HEADER mCpuModuleID = { + //ModuleHeaderSignature + // Remove 'DOM$' as temp solution before update BinUtil.exe , + Int32FromChar ('0', '0', '0', '0'), + //ModuleIdentifier[8] + AGESA_ID, + //ModuleVersion[12] + AGESA_VERSION_STRING, + //ModuleDispatcher + NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher), + //NextBlock + NULL +}; + + +/* Process solution defined socket / family installations + * + * As part of the release package for each image, define the options below to select the + * AGESA processor support included in that image. + */ + +/* Default sockets to off */ +#define OPTION_G34_SOCKET_SUPPORT FALSE +#define OPTION_C32_SOCKET_SUPPORT FALSE +#define OPTION_S1G3_SOCKET_SUPPORT FALSE +#define OPTION_S1G4_SOCKET_SUPPORT FALSE +#define OPTION_ASB2_SOCKET_SUPPORT FALSE +#define OPTION_FS1_SOCKET_SUPPORT FALSE +#define OPTION_FM1_SOCKET_SUPPORT FALSE +#define OPTION_FP1_SOCKET_SUPPORT FALSE +#define OPTION_FT1_SOCKET_SUPPORT FALSE +#define OPTION_AM3_SOCKET_SUPPORT FALSE + +/* Default families to off */ +#define OPTION_FAMILY10H FALSE +#define OPTION_FAMILY12H FALSE +#define OPTION_FAMILY14H FALSE +#define OPTION_FAMILY15H FALSE + + +/* Enable the appropriate socket support */ +#ifdef INSTALL_G34_SOCKET_SUPPORT + #if INSTALL_G34_SOCKET_SUPPORT == TRUE + #undef OPTION_G34_SOCKET_SUPPORT + #define OPTION_G34_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_C32_SOCKET_SUPPORT + #if INSTALL_C32_SOCKET_SUPPORT == TRUE + #undef OPTION_C32_SOCKET_SUPPORT + #define OPTION_C32_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_S1G3_SOCKET_SUPPORT + #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE + #undef OPTION_S1G3_SOCKET_SUPPORT + #define OPTION_S1G3_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_S1G4_SOCKET_SUPPORT + #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE + #undef OPTION_S1G4_SOCKET_SUPPORT + #define OPTION_S1G4_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_ASB2_SOCKET_SUPPORT + #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE + #undef OPTION_ASB2_SOCKET_SUPPORT + #define OPTION_ASB2_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_FS1_SOCKET_SUPPORT + #if INSTALL_FS1_SOCKET_SUPPORT == TRUE + #undef OPTION_FS1_SOCKET_SUPPORT + #define OPTION_FS1_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_FM1_SOCKET_SUPPORT + #if INSTALL_FM1_SOCKET_SUPPORT == TRUE + #undef OPTION_FM1_SOCKET_SUPPORT + #define OPTION_FM1_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_FP1_SOCKET_SUPPORT + #if INSTALL_FP1_SOCKET_SUPPORT == TRUE + #undef OPTION_FP1_SOCKET_SUPPORT + #define OPTION_FP1_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_FT1_SOCKET_SUPPORT + #if INSTALL_FT1_SOCKET_SUPPORT == TRUE + #undef OPTION_FT1_SOCKET_SUPPORT + #define OPTION_FT1_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_AM3_SOCKET_SUPPORT + #if INSTALL_AM3_SOCKET_SUPPORT == TRUE + #undef OPTION_AM3_SOCKET_SUPPORT + #define OPTION_AM3_SOCKET_SUPPORT TRUE + #endif +#endif + + +/* Enable the appropriate family support */ +// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3 +#ifdef INSTALL_FAMILY_10_SUPPORT + #if INSTALL_FAMILY_10_SUPPORT == TRUE + #undef OPTION_FAMILY10H + #define OPTION_FAMILY10H TRUE + #endif +#endif + +// F12 is supported in FP1, FS1, & FM1 +#ifdef INSTALL_FAMILY_12_SUPPORT + #if INSTALL_FAMILY_12_SUPPORT == TRUE + #undef OPTION_FAMILY12H + #define OPTION_FAMILY12H TRUE + #endif +#endif + +// F14 is supported in FT1 +#ifdef INSTALL_FAMILY_14_SUPPORT + #if INSTALL_FAMILY_14_SUPPORT == TRUE + #undef OPTION_FAMILY14H + #define OPTION_FAMILY14H TRUE + #endif +#endif + +// F15 is supported in G34, C32, & AM3 +#ifdef INSTALL_FAMILY_15_SUPPORT + #if INSTALL_FAMILY_15_SUPPORT == TRUE + #undef OPTION_FAMILY15H + #define OPTION_FAMILY15H TRUE + #endif +#endif + + +/* Turn off families not required by socket designations */ +#if (OPTION_FAMILY10H == TRUE) + #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) + #undef OPTION_FAMILY10H + #define OPTION_FAMILY10H FALSE + #endif +#endif + +#if (OPTION_FAMILY12H == TRUE) + #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE) + #undef OPTION_FAMILY12H + #define OPTION_FAMILY12H FALSE + #endif +#endif + +#if (OPTION_FAMILY14H == TRUE) + #if (OPTION_FT1_SOCKET_SUPPORT == FALSE) + #undef OPTION_FAMILY14H + #define OPTION_FAMILY14H FALSE + #endif +#endif + +#if (OPTION_FAMILY15H == TRUE) + #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) + #undef OPTION_FAMILY15H + #define OPTION_FAMILY15H FALSE + #endif +#endif + + +/* Check for invalid combinations of socket/family */ +#if (OPTION_G34_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) + #error No G34 supported families included in the build + #endif +#endif + +#if (OPTION_C32_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) + #error No C32 supported families included in the build + #endif +#endif + +#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) + #error No S1G3 supported families included in the build + #endif +#endif + +#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) + #error No S1G4 supported families included in the build + #endif +#endif + +#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) + #error No ASB2 supported families included in the build + #endif +#endif + +#if (OPTION_FS1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == FALSE) + #error No FS1 supported families included in the build + #endif +#endif + +#if (OPTION_FM1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == FALSE) + #error No FM1 supported families included in the build + #endif +#endif + +#if (OPTION_FP1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == FALSE) + #error No FP1 supported families included in the build + #endif +#endif + +#if (OPTION_FT1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY14H == FALSE) + #error No FT1 supported families included in the build + #endif +#endif + +#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) + #error No AM3 supported families included in the build + #endif +#endif + + +/* Process AGESA private data + * + * Turn on appropriate CPU models and memory controllers, + * as well as some other memory controls. + */ + +/* Default all models to off */ +#define OPTION_FAMILY10H_BL FALSE +#define OPTION_FAMILY10H_DA FALSE +#define OPTION_FAMILY10H_HY FALSE +#define OPTION_FAMILY10H_PH FALSE +#define OPTION_FAMILY10H_RB FALSE +#define OPTION_FAMILY12H_LN FALSE +#define OPTION_FAMILY14H_ON FALSE +#define OPTION_FAMILY15H_OR FALSE + +/* Default all memory controllers to off */ +#define OPTION_MEMCTLR_DR FALSE +#define OPTION_MEMCTLR_HY FALSE +#define OPTION_MEMCTLR_OR FALSE +#define OPTION_MEMCTLR_C32 FALSE +#define OPTION_MEMCTLR_DA FALSE +#define OPTION_MEMCTLR_LN FALSE +#define OPTION_MEMCTLR_ON FALSE +#define OPTION_MEMCTLR_Ni FALSE +#define OPTION_MEMCTLR_PH FALSE +#define OPTION_MEMCTLR_RB FALSE + +/* Default all memory controls to off */ +#define OPTION_HW_WRITE_LEV_TRAINING FALSE +#define OPTION_SW_WRITE_LEV_TRAINING FALSE +#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE +#define OPTION_HW_DQS_REC_EN_TRAINING FALSE +#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE +#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE +#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE +#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE +#define OPTION_MAX_RD_LAT_TRAINING FALSE +#define OPTION_HW_DRAM_INIT FALSE +#define OPTION_SW_DRAM_INIT FALSE +#define OPTION_S3_MEM_SUPPORT FALSE +#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE +#define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE + +/* Defaults for public user options */ +#define OPTION_UDIMMS FALSE +#define OPTION_RDIMMS FALSE +#define OPTION_SODIMMS FALSE +#define OPTION_LRDIMMS FALSE +#define OPTION_DDR2 FALSE +#define OPTION_DDR3 FALSE +#define OPTION_ECC FALSE +#define OPTION_BANK_INTERLEAVE FALSE +#define OPTION_DCT_INTERLEAVE FALSE +#define OPTION_NODE_INTERLEAVE FALSE +#define OPTION_PARALLEL_TRAINING FALSE +#define OPTION_ONLINE_SPARE FALSE +#define OPTION_MEM_RESTORE FALSE +#define OPTION_DIMM_EXCLUDE FALSE + +/* Default all CPU controls to off */ +#define OPTION_MULTISOCKET FALSE +#define OPTION_SRAT FALSE +#define OPTION_SLIT FALSE +#define OPTION_HT_ASSIST FALSE +#define OPTION_ATM_MODE FALSE +#define OPTION_CPU_CORELEVLING FALSE +#define OPTION_MSG_BASED_C1E FALSE +#define OPTION_CPU_CFOH FALSE +#define OPTION_C6_STATE FALSE +#define OPTION_IO_CSTATE FALSE +#define OPTION_CPB FALSE +#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE +#define OPTION_S3SCRIPT FALSE +#define OPTION_GFX_RECOVERY FALSE + +/* Default FCH controls to off */ +#define FCH_SUPPORT FALSE + +/* Enable all private controls based on socket/family enables */ +#if (OPTION_G34_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_HY + #define OPTION_FAMILY10H_HY TRUE + #undef OPTION_MEMCTLR_HY + #define OPTION_MEMCTLR_HY TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET TRUE + #undef OPTION_SRAT + #define OPTION_SRAT TRUE + #undef OPTION_SLIT + #define OPTION_SLIT TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif + #if (OPTION_FAMILY15H == TRUE) + #undef OPTION_FAMILY15H_OR + #define OPTION_FAMILY15H_OR TRUE + #undef OPTION_MEMCTLR_OR + #define OPTION_MEMCTLR_OR TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT + #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE + #undef OPTION_SRAT + #define OPTION_SRAT TRUE + #undef OPTION_SLIT + #define OPTION_SLIT TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST TRUE + #undef OPTION_ATM_MODE + #define OPTION_ATM_MODE TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_LRDIMMS + #define OPTION_LRDIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_C32_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_HY + #define OPTION_FAMILY10H_HY TRUE + #undef OPTION_MEMCTLR_C32 + #define OPTION_MEMCTLR_C32 TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET TRUE + #undef OPTION_SRAT + #define OPTION_SRAT TRUE + #undef OPTION_SLIT + #define OPTION_SLIT TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif + #if (OPTION_FAMILY15H == TRUE) + #undef OPTION_FAMILY15H_OR + #define OPTION_FAMILY15H_OR TRUE + #undef OPTION_MEMCTLR_OR + #define OPTION_MEMCTLR_OR TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT + #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE + #undef OPTION_SRAT + #define OPTION_SRAT TRUE + #undef OPTION_SLIT + #define OPTION_SLIT TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST TRUE + #undef OPTION_ATM_MODE + #define OPTION_ATM_MODE TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_LRDIMMS + #define OPTION_LRDIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_BL + #define OPTION_FAMILY10H_BL TRUE + #undef OPTION_FAMILY10H_DA + #define OPTION_FAMILY10H_DA TRUE + #undef OPTION_MEMCTLR_DA + #define OPTION_MEMCTLR_DA TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_BL + #define OPTION_FAMILY10H_BL TRUE + #undef OPTION_FAMILY10H_DA + #define OPTION_FAMILY10H_DA TRUE + #undef OPTION_MEMCTLR_DA + #define OPTION_MEMCTLR_DA TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_BL + #define OPTION_FAMILY10H_BL TRUE + #undef OPTION_FAMILY10H_DA + #define OPTION_FAMILY10H_DA TRUE + #undef OPTION_MEMCTLR_Ni + #define OPTION_MEMCTLR_Ni TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_FS1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == TRUE) + #undef OPTION_FAMILY12H_LN + #define OPTION_FAMILY12H_LN TRUE + #undef OPTION_MEMCTLR_LN + #define OPTION_MEMCTLR_LN TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_FM1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == TRUE) + #undef OPTION_FAMILY12H_LN + #define OPTION_FAMILY12H_LN TRUE + #undef OPTION_MEMCTLR_LN + #define OPTION_MEMCTLR_LN TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_FP1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == TRUE) + #undef OPTION_FAMILY12H_LN + #define OPTION_FAMILY12H_LN TRUE + #undef OPTION_MEMCTLR_LN + #define OPTION_MEMCTLR_LN TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_FT1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY14H == TRUE) + #undef OPTION_FAMILY14H_ON + #define OPTION_FAMILY14H_ON TRUE + #undef OPTION_MEMCTLR_ON + #define OPTION_MEMCTLR_ON TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_BL + #define OPTION_FAMILY10H_BL TRUE + #undef OPTION_FAMILY10H_DA + #define OPTION_FAMILY10H_DA TRUE + #undef OPTION_FAMILY10H_PH + #define OPTION_FAMILY10H_PH TRUE + #undef OPTION_FAMILY10H_RB + #define OPTION_FAMILY10H_RB TRUE + #undef OPTION_MEMCTLR_RB + #define OPTION_MEMCTLR_RB TRUE + #undef OPTION_MEMCTLR_DA + #define OPTION_MEMCTLR_DA TRUE + #undef OPTION_MEMCTLR_PH + #define OPTION_MEMCTLR_PH TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif + #if (OPTION_FAMILY15H == TRUE) + #undef OPTION_FAMILY15H_OR + #define OPTION_FAMILY15H_OR TRUE + #undef OPTION_MEMCTLR_OR + #define OPTION_MEMCTLR_OR TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT + #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE + #undef OPTION_ATM_MODE + #define OPTION_ATM_MODE TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS TRUE + #undef OPTION_LRDIMMS + #define OPTION_LRDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) + #undef GNB_SUPPORT + #define GNB_SUPPORT TRUE +#endif + +#define OPTION_ACPI_PSTATES TRUE +#define OPTION_WHEA TRUE +#define OPTION_DMI TRUE +#define OPTION_EARLY_SAMPLES FALSE +#define CFG_ACPI_PSTATES_PPC TRUE +#define CFG_ACPI_PSTATES_PCT TRUE +#define CFG_ACPI_PSTATES_PSD TRUE +#define CFG_ACPI_PSTATES_PSS TRUE +#define CFG_ACPI_PSTATES_XPSS TRUE +#define CFG_ACPI_PSTATE_PSD_INDPX FALSE +#define CFG_VRM_HIGH_SPEED_ENABLE FALSE +#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define OPTION_ALIB TRUE +/*--------------------------------------------------------------------------- + * Processing the options: Second, process the user's selections + *--------------------------------------------------------------------------*/ +#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT + #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ECC_SUPPORT + #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE + #undef OPTION_ECC + #define OPTION_ECC FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT + #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT + #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT + #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT + #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE + #undef OPTION_LRDIMMS + #define OPTION_LRDIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE + #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE + #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE + #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING + #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT + #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT + #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING + #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ACPI_PSTATES + #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE + #undef OPTION_ACPI_PSTATES + #define OPTION_ACPI_PSTATES FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SRAT + #if BLDOPT_REMOVE_SRAT == TRUE + #undef OPTION_SRAT + #define OPTION_SRAT FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SLIT + #if BLDOPT_REMOVE_SLIT == TRUE + #undef OPTION_SLIT + #define OPTION_SLIT FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_WHEA + #if BLDOPT_REMOVE_WHEA == TRUE + #undef OPTION_WHEA + #define OPTION_WHEA FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_DMI + #if BLDOPT_REMOVE_DMI == TRUE + #undef OPTION_DMI + #define OPTION_DMI FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR + #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_HT_ASSIST + #if BLDOPT_REMOVE_HT_ASSIST == TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_ATM_MODE + #if BLDOPT_REMOVE_ATM_MODE == TRUE + #undef OPTION_ATM_MODE + #define OPTION_ATM_MODE FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_MSG_BASED_C1E + #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_C6_STATE + #if BLDOPT_REMOVE_C6_STATE == TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_GFX_RECOVERY + #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC + #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE + #undef CFG_ACPI_PSTATES_PPC + #define CFG_ACPI_PSTATES_PPC FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT + #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE + #undef CFG_ACPI_PSTATES_PCT + #define CFG_ACPI_PSTATES_PCT FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD + #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE + #undef CFG_ACPI_PSTATES_PSD + #define CFG_ACPI_PSTATES_PSD FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS + #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE + #undef CFG_ACPI_PSTATES_PSS + #define CFG_ACPI_PSTATES_PSS FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS + #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE + #undef CFG_ACPI_PSTATES_XPSS + #define CFG_ACPI_PSTATES_XPSS FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT + #if BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE + #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT + #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE + #endif +#endif + +#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT + #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE + #undef CFG_ACPI_PSTATE_PSD_INDPX + #define CFG_ACPI_PSTATE_PSD_INDPX TRUE + #endif +#endif + +#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE + #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE + #undef CFG_VRM_HIGH_SPEED_ENABLE + #define CFG_VRM_HIGH_SPEED_ENABLE TRUE + #endif +#endif + +#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE + #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE + #undef CFG_VRM_NB_HIGH_SPEED_ENABLE + #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE + #endif +#endif + +#ifdef BLDCFG_STARTING_BUSNUM + #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM) +#else + #define CFG_STARTING_BUSNUM (0) +#endif + +#ifdef BLDCFG_AMD_PLATFORM_TYPE + #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE +#else + #define CFG_AMD_PLATFORM_TYPE 0 +#endif + +CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; + +#ifdef BLDCFG_MAXIMUM_BUSNUM + #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM) +#else + #define CFG_MAXIMUM_BUSNUM (0xF8) +#endif + +#ifdef BLDCFG_ALLOCATED_BUSNUM + #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM) +#else + #define CFG_ALLOCATED_BUSNUM (0x20) +#endif + +#ifdef BLDCFG_BUID_SWAP_LIST + #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST) +#else + #define CFG_BUID_SWAP_LIST (NULL) +#endif + +#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST + #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST) +#else + #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL) +#endif + +#ifdef BLDCFG_HTFABRIC_LIMITS_LIST + #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST) +#else + #define CFG_HTFABRIC_LIMITS_LIST (NULL) +#endif + +#ifdef BLDCFG_HTCHAIN_LIMITS_LIST + #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST) +#else + #define CFG_HTCHAIN_LIMITS_LIST (NULL) +#endif + +#ifdef BLDCFG_BUS_NUMBERS_LIST + #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST) +#else + #define CFG_BUS_NUMBERS_LIST (NULL) +#endif + +#ifdef BLDCFG_IGNORE_LINK_LIST + #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST) +#else + #define CFG_IGNORE_LINK_LIST (NULL) +#endif + +#ifdef BLDCFG_LINK_SKIP_REGANG_LIST + #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST) +#else + #define CFG_LINK_SKIP_REGANG_LIST (NULL) +#endif + +#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD + #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD) +#else + #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE) +#endif + +#ifdef BLDCFG_USE_UNIT_ID_CLUMPING + #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING) +#else + #define CFG_USE_UNIT_ID_CLUMPING (FALSE) +#endif + +#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST + #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST) +#else + #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL) +#endif + +#ifdef BLDCFG_USE_HT_ASSIST + #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST) +#else + #define CFG_USE_HT_ASSIST (TRUE) +#endif + +#ifdef BLDCFG_USE_ATM_MODE + #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE) +#else + #define CFG_USE_ATM_MODE (TRUE) +#endif + +#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE + #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE) +#else + #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm) +#endif + +#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST + #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST) +#else + #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL) +#endif + +#ifdef BLDCFG_VRM_ADDITIONAL_DELAY + #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY) +#else + #define CFG_VRM_ADDITIONAL_DELAY (0) +#endif + +#ifdef BLDCFG_VRM_CURRENT_LIMIT + #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT +#else + #define CFG_VRM_CURRENT_LIMIT 0 +#endif + +#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD + #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD +#else + #define CFG_VRM_LOW_POWER_THRESHOLD 0 +#endif + +#ifdef BLDCFG_VRM_SLEW_RATE + #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#else + #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE +#endif + +#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT + #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT +#else + #define CFG_VRM_INRUSH_CURRENT_LIMIT 0 +#endif + +#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY + #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY) +#else + #define CFG_VRM_NB_ADDITIONAL_DELAY (0) +#endif + +#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT + #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT +#else + #define CFG_VRM_NB_CURRENT_LIMIT (0) +#endif + +#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD + #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD +#else + #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0) +#endif + +#ifdef BLDCFG_VRM_NB_SLEW_RATE + #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE +#else + #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE +#endif + +#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT + #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT +#else + #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0) +#endif + + +#ifdef BLDCFG_PLAT_NUM_IO_APICS + #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS +#else + #define CFG_PLAT_NUM_IO_APICS 0 +#endif + +#ifdef BLDCFG_MEM_INIT_PSTATE + #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE +#else + #define CFG_MEM_INIT_PSTATE 0 +#endif + +#ifdef BLDCFG_PLATFORM_C1E_MODE + #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE +#else + #define CFG_C1E_MODE C1eModeDisabled +#endif + +#ifdef BLDCFG_PLATFORM_C1E_OPDATA + #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA +#else + #define CFG_C1E_OPDATA 0 +#endif + +#ifdef BLDCFG_PLATFORM_C1E_OPDATA1 + #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1 +#else + #define CFG_C1E_OPDATA1 0 +#endif + +#ifdef BLDCFG_PLATFORM_C1E_OPDATA2 + #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2 +#else + #define CFG_C1E_OPDATA2 0 +#endif + +#ifdef BLDCFG_PLATFORM_C1E_OPDATA3 + #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3 +#else + #define CFG_C1E_OPDATA3 0 +#endif + +#ifdef BLDCFG_PLATFORM_CSTATE_MODE + #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE +#else + #define CFG_CSTATE_MODE CStateModeDisabled +#endif + +#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA + #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA +#else + #define CFG_CSTATE_OPDATA 0 +#endif + +#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS + #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS +#else + #define CFG_CSTATE_IO_BASE_ADDRESS 0 +#endif + +#ifdef BLDCFG_PLATFORM_CPB_MODE + #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE +#else + #define CFG_CPB_MODE CpbModeAuto +#endif + +#ifdef BLDCFG_CORE_LEVELING_MODE + #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE +#else + #define CFG_CORE_LEVELING_MODE 0 +#endif + +#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE + #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE +#else + #define CFG_AMD_PSTATE_CAP_VALUE 0 +#endif + +#ifdef BLDCFG_HEAP_DRAM_ADDRESS + #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS +#else + #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS +#endif + +#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT +#else + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY +#endif + +#ifdef BLDCFG_MEMORY_MODE_UNGANGED + #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED +#else + #define CFG_MEMORY_MODE_UNGANGED TRUE +#endif + +#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE + #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE +#else + #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_QUADRANK_TYPE + #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE +#else + #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE +#endif + +#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE + #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE +#else + #define CFG_MEMORY_RDIMM_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE + #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE +#else + #define CFG_MEMORY_LRDIMM_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE + #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE +#else + #define CFG_MEMORY_UDIMM_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE + #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE +#else + #define CFG_MEMORY_SODIMM_CAPABLE FALSE +#endif + +#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB + #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB +#else + #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE +#endif + +#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING + #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING +#else + #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#endif + +#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING + #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING +#else + #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#endif + +#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING + #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING +#else + #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#endif + +#ifdef BLDCFG_MEMORY_POWER_DOWN + #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN +#else + #define CFG_MEMORY_POWER_DOWN FALSE +#endif + +#ifdef BLDCFG_POWER_DOWN_MODE + #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE +#else + #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO +#endif + +#ifdef BLDCFG_ONLINE_SPARE + #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE +#else + #define CFG_ONLINE_SPARE FALSE +#endif + +#ifdef BLDCFG_MEMORY_PARITY_ENABLE + #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE +#else + #define CFG_MEMORY_PARITY_ENABLE FALSE +#endif + +#ifdef BLDCFG_BANK_SWIZZLE + #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE +#else + #define CFG_BANK_SWIZZLE TRUE +#endif + +#ifdef BLDCFG_TIMING_MODE_SELECT + #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT +#else + #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#endif + +#ifdef BLDCFG_MEMORY_CLOCK_SELECT + #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT +#else + #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#endif + +#ifdef BLDCFG_DQS_TRAINING_CONTROL + #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL +#else + #define CFG_DQS_TRAINING_CONTROL TRUE +#endif + +#ifdef BLDCFG_IGNORE_SPD_CHECKSUM + #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM +#else + #define CFG_IGNORE_SPD_CHECKSUM FALSE +#endif + +#ifdef BLDCFG_USE_BURST_MODE + #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE +#else + #define CFG_USE_BURST_MODE FALSE +#endif + +#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON + #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON +#else + #define CFG_MEMORY_ALL_CLOCKS_ON FALSE +#endif + +#ifdef BLDCFG_ENABLE_ECC_FEATURE + #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE +#else + #define CFG_ENABLE_ECC_FEATURE TRUE +#endif + +#ifdef BLDCFG_ECC_REDIRECTION + #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION +#else + #define CFG_ECC_REDIRECTION FALSE +#endif + +#ifdef BLDCFG_SCRUB_DRAM_RATE + #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE +#else + #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE +#endif + +#ifdef BLDCFG_SCRUB_L2_RATE + #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE +#else + #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE +#endif + +#ifdef BLDCFG_SCRUB_L3_RATE + #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE +#else + #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE +#endif + +#ifdef BLDCFG_SCRUB_IC_RATE + #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE +#else + #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE +#endif + +#ifdef BLDCFG_SCRUB_DC_RATE + #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE +#else + #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE +#endif + +#ifdef BLDCFG_ECC_SYNC_FLOOD + #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD +#else + #define CFG_ECC_SYNC_FLOOD TRUE +#endif + +#ifdef BLDCFG_ECC_SYMBOL_SIZE + #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE +#else + #define CFG_ECC_SYMBOL_SIZE 0 +#endif + +#ifdef BLDCFG_1GB_ALIGN + #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN +#else + #define CFG_1GB_ALIGN FALSE +#endif + +#ifdef BLDCFG_UMA_ALLOCATION_MODE + #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE +#else + #define CFG_UMA_MODE UMA_AUTO +#endif + +#ifdef BLDCFG_UMA_ALLOCATION_SIZE + #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE +#else + #define CFG_UMA_SIZE 0 +#endif + +#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT + #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT +#else + #define CFG_UMA_ABOVE4G FALSE +#endif + +#ifdef BLDCFG_UMA_ALIGNMENT + #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT +#else + #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB + #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB +#else + #define CFG_PROCESSOR_SCOPE_IN_SB FALSE +#endif + +#ifdef BLDCFG_S3_LATE_RESTORE + #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE +#else + #define CFG_S3_LATE_RESTORE TRUE +#endif + +#ifdef BLDCFG_USE_32_BYTE_REFRESH + #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH) +#else + #define CFG_USE_32_BYTE_REFRESH (FALSE) +#endif + +#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY + #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY) +#else + #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE) +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0 + #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0 +#else + #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1 + #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1 +#else + #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1 +#endif + +#ifdef BLDCFG_CFG_GNB_HD_AUDIO + #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO +#else + #define CFG_GNB_HD_AUDIO TRUE +#endif + +#ifdef BLDCFG_CFG_ABM_SUPPORT + #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT +#else + #define CFG_ABM_SUPPORT FALSE +#endif + +#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE + #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE +#else + #define CFG_DYNAMIC_REFRESH_RATE 0 +#endif + +#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL + #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL +#else + #define CFG_LCD_BACK_LIGHT_CONTROL 0 +#endif + +#ifdef BLDCFG_STEREO_3D_PINOUT + #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT +#else + #define CFG_GNB_STEREO_3D_PINOUT 0 +#endif + +#ifdef BLDCFG_IGPU_SUBSYSTEM_ID + #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID +#else + #define CFG_GNB_IGPU_SSID 0 +#endif + +#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID + #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID +#else + #define CFG_GNB_HDAUDIO_SSID 0 +#endif + +#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID + #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID +#else + #define CFG_GNB_PCIE_SSID 0x12341022 +#endif + +#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM + #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM +#else + #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0 +#endif + +#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE + #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE +#else + #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0 +#endif + +#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM + #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM +#else + #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0 +#endif + +#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS + #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS +#else + #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 +#endif + +#ifdef BLDOPT_REMOVE_EARLY_SAMPLES + #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE + #undef OPTION_EARLY_SAMPLES + #define OPTION_EARLY_SAMPLES FALSE + #else + #undef OPTION_EARLY_SAMPLES + #define OPTION_EARLY_SAMPLES TRUE + #endif +#endif + +#ifdef BLDOPT_REMOVE_ALIB + #if BLDOPT_REMOVE_ALIB == TRUE + #undef OPTION_ALIB + #define OPTION_ALIB FALSE + #else + #undef OPTION_ALIB + #define OPTION_ALIB TRUE + #endif +#endif + +#ifdef BLDCFG_IOMMU_SUPPORT + #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT +#else + #define CFG_IOMMU_SUPPORT TRUE +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE + #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE +#else + #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0 +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL + #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL +#else + #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0 +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON + #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON +#else + #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0 +#endif + +#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE + #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE +#else + #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0 +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY + #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY +#else + #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0 +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON + #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON +#else + #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0 +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL + #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL +#else + #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0 +#endif + +#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ + #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ +#else + #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0 +#endif + +#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE + #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE +#else + #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0 +#endif + + +// BLDCFG_LVDS_24BBP_PANEL_MODE +// This specifies the LVDS 24 BBP mode. +// 0 - Use LDI mode (default). +// 1 - Use FPDI mode. +#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE + #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE +#else + #define CFG_LVDS_24BBP_PANEL_MODE 0 +#endif + +#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE + #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE) +#else + #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) +#endif + +#ifdef BLDCFG_PCI_MMIO_BASE + #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE) +#else + #define CFG_PCI_MMIO_BASE (0) +#endif + +#ifdef BLDCFG_PCI_MMIO_SIZE + #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE) +#else + #define CFG_PCI_MMIO_SIZE (0) +#endif + +#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST + #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) +#else + #define CFG_AP_MTRR_SETTINGS_LIST (NULL) +#endif + +/*--------------------------------------------------------------------------- + * Processing the options: Third, perform the option cross checks + *--------------------------------------------------------------------------*/ +// Assure that at least one type of memory support is included +#if OPTION_UDIMMS == FALSE + #if OPTION_RDIMMS == FALSE + #if OPTION_SODIMMS == FALSE + #if OPTION_LRDIMMS == FALSE + #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE. + #endif + #endif + #endif +#endif +// Ensure at least one dimm type is capable +#if CFG_MEMORY_RDIMM_CAPABLE == FALSE + #if CFG_MEMORY_UDIMM_CAPABLE == FALSE + #if CFG_MEMORY_SODIMM_CAPABLE == FALSE + #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE + #error BLDCFG: No dimm type is capable + #endif + #endif + #endif +#endif +// Turn off multi-socket based features if only one node... +#if OPTION_MULTISOCKET == FALSE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING FALSE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE FALSE +#endif +// Ensure that at least one write leveling option is selected +#if OPTION_DDR3 == TRUE + #if OPTION_HW_WRITE_LEV_TRAINING == FALSE + #if OPTION_SW_WRITE_LEV_TRAINING == FALSE + #error No Write leveling option selected for DDR3 + #endif + #endif + #if OPTION_SW_DRAM_INIT == FALSE + #error Software dram init must be enabled for DDR3 dimms + #endif +#endif +// Ensure at least one DQS receiver training option is selected +#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE + #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE + #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE + #error No DQS receiver training option has been slected + #endif + #endif +#endif +// Ensure at least one Rd Wr position training option has been selected +#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE + #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE + #error No Rd Wr position training option has been selected + #endif +#endif +// Ensure at least one dram init option has been selected +#if OPTION_HW_DRAM_INIT == FALSE + #if OPTION_SW_DRAM_INIT == FALSE + #error No Dram init option has been selected + #endif +#endif +/* As an ENUM, DDRXXX_FREQUENCY is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS +// Ensure the frequency limit is valid +#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200) + #error BLDCFG: Unsupported memory bus frequency + #endif + #endif + #endif + #endif + #endif + #endif + #endif +#endif + +#endif +/* As an ENUM, TIMING_MODE_XXX is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS + +// Ensure timing mode is valid +#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC + #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED + #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO + #error BLDCFG: Invalid timing mode is set + #endif + #endif +#endif + +#endif +// Ensure the scrub rate is valid +#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF)) + #error BLDCFG: Unsupported dram scrub rate set +#endif +#if CFG_SCRUB_L2_RATE > 0x16 + #error BLDCFG: Unsupported L2 scrubber rate set +#endif +#if CFG_SCRUB_L3_RATE > 0x16 + #error BLDCFG: unsupported L3 scrubber rate set +#endif +#if CFG_SCRUB_IC_RATE > 0x16 + #error BLDCFG: Unsupported Instruction cache scrub rate set +#endif +#if CFG_SCRUB_DC_RATE > 0x16 + #error BLDCFG: Unsupported Dcache scrub rate set +#endif +/* As an ENUM, QUADRANK_XXX is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS + +// Ensure Quad rank dimm type is valid +#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED + #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED + #error BLDCFG: Invalid quad rank dimm type set + #endif +#endif + +#endif +// Ensure ECC symbol size is valid +#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG + #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4 + #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8 + #error BLDCFG: Invalid Ecc symbol size set + #endif + #endif +#endif +/* As an ENUM, POWER_DOWN_BY_XXX is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS + +// Ensure power down mode is valid +#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT + #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL + #error BLDCFG: Invalid power down mode set + #endif +#endif + +#endif +/***************************************************************************** + * + * Process the option logic, setting local control variables + * + ****************************************************************************/ +#if OPTION_ACPI_PSTATES == TRUE + #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain + #define OPTFCN_GATHER_DATA PStateGatherData + #if OPTION_MULTISOCKET == TRUE + #define OPTFCN_PSTATE_LEVELING PStateLeveling + #else + #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess + #endif +#else + #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess + #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess + #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess +#endif + + +/***************************************************************************** + * + * Include the structure definitions for the defaults table structures + * + ****************************************************************************/ +#include +#include +#include "Options.h" +#include "OptionCpuFamiliesInstall.h" +#include "OptionsHt.h" +#include "OptionHtInstall.h" +#include "OptionMemory.h" +#include "OptionMemoryInstall.h" +#include "OptionMemoryRecovery.h" +#include "OptionMemoryRecoveryInstall.h" +#include "OptionCpuFeaturesInstall.h" +#include "OptionDmi.h" +#include "OptionDmiInstall.h" +#include "OptionPstate.h" +#include "OptionPstateInstall.h" +#include "OptionWhea.h" +#include "OptionWheaInstall.h" +#include "OptionSrat.h" +#include "OptionSratInstall.h" +#include "OptionSlit.h" +#include "OptionSlitInstall.h" +#include "OptionMultiSocket.h" +#include "OptionMultiSocketInstall.h" +#include "OptionIdsInstall.h" +#include "OptionGfxRecovery.h" +#include "OptionGfxRecoveryInstall.h" +#include "OptionGnb.h" +#include "OptionGnbInstall.h" +#include "OptionS3ScriptInstall.h" +#include "OptionFchInstall.h" + + +/***************************************************************************** + * + * Generate the output structures (defaults tables) + * + ****************************************************************************/ +BUILD_OPT_CFG UserOptions = { + { // AGESA version string + AGESA_CODE_SIGNATURE, // code header Signature + AGESA_PACKAGE_STRING, // 8 character ID + AGESA_VERSION_STRING, // 12 character version string + 0 // null string terminator + }, + //Build Option Area + OPTION_UDIMMS, //UDIMMS + OPTION_RDIMMS, //RDIMMS + OPTION_LRDIMMS, //LRDIMMS + OPTION_ECC, //ECC + OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE + OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE + OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE + OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING + OPTION_ONLINE_SPARE, //ONLINE_SPARE + OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE + OPTION_MULTISOCKET, //MULTISOCKET + OPTION_ACPI_PSTATES, //ACPI_PSTATES + OPTION_SRAT, //SRAT + OPTION_SLIT, //SLIT + OPTION_WHEA, //WHEA + OPTION_DMI, //DMI + OPTION_EARLY_SAMPLES, //EARLY_SAMPLES + OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR + + //Build Configuration Area + CFG_PCI_MMIO_BASE, + CFG_PCI_MMIO_SIZE, + { + // CoreVrm + { + CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit + CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold + CFG_VRM_SLEW_RATE, // VrmSlewRate + CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay + CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable + CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit + }, + // NbVrm + { + CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit + CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold + CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate + CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay + CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable + CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit + } + }, + CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber + CFG_MEM_INIT_PSTATE, //MemoryInitPstate + CFG_C1E_MODE, //C1eMode + CFG_C1E_OPDATA, //C1ePlatformData + CFG_C1E_OPDATA1, //C1ePlatformData1 + CFG_C1E_OPDATA2, //C1ePlatformData2 + CFG_C1E_OPDATA3, //C1ePlatformData3 + CFG_CSTATE_MODE, //CStateMode + CFG_CSTATE_OPDATA, //CStatePlatformData + CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress + CFG_CPB_MODE, //CpbMode + CFG_CORE_LEVELING_MODE, //CoreLevelingCofig + { + CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode. + CFG_USE_HT_ASSIST, // CfgUseHtAssist + CFG_USE_ATM_MODE, // CfgUseAtmMode + CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets. + CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority. + CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode. + }, + (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings + CFG_AMD_PLATFORM_TYPE, //AmdPlatformType + CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck + + CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit + CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged + CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable + CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType + CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable + CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable + CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable + CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable + CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb + CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving + CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving + CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving + CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown + CFG_POWER_DOWN_MODE, // CfgPowerDownMode + CFG_ONLINE_SPARE, // CfgOnlineSpare + CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable + CFG_BANK_SWIZZLE, // CfgBankSwizzle + CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect + CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect + CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl + CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum + CFG_USE_BURST_MODE, // CfgUseBurstMode + CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn + CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature + CFG_ECC_REDIRECTION, // CfgEccRedirection + CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate + CFG_SCRUB_L2_RATE, // CfgScrubL2Rate + CFG_SCRUB_L3_RATE, // CfgScrubL3Rate + CFG_SCRUB_IC_RATE, // CfgScrubIcRate + CFG_SCRUB_DC_RATE, // CfgScrubDcRate + CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood + CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize + CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress + CFG_1GB_ALIGN, // CfgNodeMem1GBAlign + CFG_S3_LATE_RESTORE, // CfgS3LateRestore + CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent + (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList + CFG_UMA_MODE, // CfgUmaMode + CFG_UMA_SIZE, // CfgUmaSize + CFG_UMA_ABOVE4G, // CfgUmaAbove4G + CFG_UMA_ALIGNMENT, // CfgUmaAlignment + CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb + CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0 + CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1 + CFG_GNB_HD_AUDIO, // CfgGnbHdAudio + CFG_ABM_SUPPORT, // CfgAbmSupport + CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate + CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl + CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex + CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress + CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID + CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID + CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID + CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum + CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate + + CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress + CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress + CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress + CFG_ACPI_PM1_EVT_BLOCK_ADDRESS, // CfgAcpiPm1EvtBlkAddr + CFG_ACPI_PM1_CNT_BLOCK_ADDRESS, // CfgAcpiPm1CntBlkAddr + CFG_ACPI_PM_TMR_BLOCK_ADDRESS, // CfgAcpiPmTmrBlkAddr + CFG_ACPI_CPU_CNT_BLOCK_ADDRESS, // CfgCpuControlBlkAddr + CFG_ACPI_GPE0_BLOCK_ADDRESS, // CfgAcpiGpe0BlkAddr + CFG_SMI_CMD_PORT_ADDRESS, // CfgSmiCmdPortAddr + CFG_ACPI_PMA_CNTBLK_ADDRESS, // CfgAcpiPmaCntBlkAddr + CFG_GEC_SHADOW_ROM_BASE, // CfgGecShadowRomBase + CFG_WATCHDOG_TIMER_BASE, // CfgWatchDogTimerBase + CFG_SPI_ROM_BASE_ADDRESS, // CfgSpiRomBaseAddress + CFG_HPET_BASE_ADDRESS, // CfgHpetBaseAddress + CFG_AZALIA_SSID, // CfgAzaliaSsid + CFG_SMBUS_SSID, // CfgSmbusSsid + CFG_IDE_SSID, // CfgIdeSsid + CFG_SATA_AHCI_SSID, // CfgSataAhciSsid + CFG_SATA_IDE_SSID, // CfgSataIdeSsid + CFG_SATA_RAID5_SSID, // CfgSataRaid5Ssid + CFG_SATA_RAID_SSID, // CfgSataRaidSsid + CFG_EHCI_SSID, // CfgEhcidSsid + CFG_OHCI_SSID, // CfgOhcidSsid + CFG_LPC_SSID, // CfgLpcSsid + CFG_FCH_GPP_LINK_CONFIG, // CfgFchGppLinkConfig + CFG_FCH_GPP_PORT0_PRESENT, // CfgFchGppPort0Present + CFG_FCH_GPP_PORT1_PRESENT, // CfgFchGppPort1Present + CFG_FCH_GPP_PORT2_PRESENT, // CfgFchGppPort2Present + CFG_FCH_GPP_PORT3_PRESENT, // CfgFchGppPort3Present + CFG_FCH_GPP_PORT0_HOTPLUG, // CfgFchGppPort0HotPlug + CFG_FCH_GPP_PORT1_HOTPLUG, // CfgFchGppPort1HotPlug + CFG_FCH_GPP_PORT2_HOTPLUG, // CfgFchGppPort2HotPlug + CFG_FCH_GPP_PORT3_HOTPLUG, // CfgFchGppPort3HotPlug + + + CFG_IOMMU_SUPPORT, // CfgIommuSupport + CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE, // CfgLvdsPowerOnSeqDigonToDe + CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL, // CfgLvdsPowerOnSeqDeToVaryBl + CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON, // CfgLvdsPowerOnSeqDeToDigon + CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe + CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay + CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon + CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl + CFG_LVDS_MAX_PIXEL_CLOCK_FREQ, // CfgLvdsMaxPixelClockFreq + CFG_LCD_BIT_DEPTH_CONTROL_VALUE, // CfgLcdBitDepthControlValue + CFG_LVDS_24BBP_PANEL_MODE, // CfgLvds24bbpPanelMode + CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum + 0, //reserved... +}; + +CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = +{ + IDS_LATE_RUN_AP_TASK + // Get DMI info + CPU_DMI_AP_GET_TYPE4_TYPE7 + // Probe filter enable + L3_FEAT_AP_DISABLE_CACHE + L3_FEAT_AP_ENABLE_CACHE + + { 0, NULL } +}; + +#if AGESA_ENTRY_INIT_EARLY == TRUE + #if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_TRACING_ENABLED == TRUE + #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y) + CONST CHAR8 *BldOptDebugOutput[] = { + #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE + //Build Option Area + MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS) + MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS) + MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS) + MAKE_DBG_STR (\nOptECC, OPTION_ECC) + MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE) + MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE) + MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE) + //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING) + MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE) + MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR) + MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE) + MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET) + MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES) + MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT) + MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT) + MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA) + MAKE_DBG_STR (\nOptDMI, OPTION_DMI) + MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES), + + //Build Configuration Area + // CoreVrm + MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT) + MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD) + MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE) + MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY) + MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE) + MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT) + // NbVrm + MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT) + MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD) + MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE) + MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY) + MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE) + MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT), + + MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS) + MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE) + MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE) + MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA) + MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1) + MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2) + MAKE_DBG_STR (\nC1eOpdata3 , CFG_C1E_OPDATA3) + MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE) + MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA) + MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS) + MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE) + MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE), + + MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE) + MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST) + MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE) + MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH) + MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY) + MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD) + + MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST) + + MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE) + MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE) + MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE) + MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE), + + MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT) + MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT) + MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT) + + MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED) + MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE) + MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE) + MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE) + MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE) + MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE) + MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE) + MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL) + MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM) + MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE) + MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON), + + MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN) + MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE) + MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE) + MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE) + MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE) + MAKE_DBG_STR (\nLimitBelow1TB , CFG_LIMIT_MEMORY_TO_BELOW_1TB) + MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING) + MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING) + MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING), + + MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE) + MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE) + MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G) + MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT) + + MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE) + MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION) + MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE) + MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE) + MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE) + MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE) + MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE) + MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD) + MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE) + MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS) + MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN), + + MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE) + MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX) + + MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST) + + MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB) + MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0) + MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1) + MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO) + MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT) + MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE) + MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL) + MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT) + MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS), + MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID) + MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID) + MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID) + MAKE_DBG_STR (\nCfgIommuSupport , CFG_IOMMU_SUPPORT) + MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM) + MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL) + MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ) + MAKE_DBG_STR (\nCfgLcdBitDepthControlValue , CFG_LCD_BIT_DEPTH_CONTROL_VALUE) + MAKE_DBG_STR (\nCfgLvds24bbpPanelMode , CFG_LVDS_24BBP_PANEL_MODE), + MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM), + #endif + NULL + }; + #endif + #endif +#endif diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f12/Include/OptionC6Install.h deleted file mode 100644 index e5c2c8e2ee..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionC6Install.h +++ /dev/null @@ -1,140 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: C6 C-state - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_C6_STATE_INSTALL_H_ -#define _OPTION_C6_STATE_INSTALL_H_ - -#include "cpuC6State.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_C6_STATE_FEAT -#define F12_C6_STATE_SUPPORT -#define F14_ON_C6_STATE_SUPPORT -#define F15_OR_C6_STATE_SUPPORT - -#if OPTION_C6_STATE == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - #if OPTION_FAMILY12H_LN == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; - #undef OPTION_C6_STATE_FEAT - #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, - extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support; - #undef F12_C6_STATE_SUPPORT - #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support}, - - #if OPTION_EARLY_SAMPLES == TRUE - extern F_F12_ES_C6_INIT F12C6A0Workaround; - - CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support = - { - F12C6A0Workaround - }; - #else - CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support = - { - (PF_F12_ES_C6_INIT) CommonVoid - }; - #endif - - #endif - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - #if (OPTION_FAMILY14H_ON == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; - #undef OPTION_C6_STATE_FEAT - #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, - extern CONST C6_FAMILY_SERVICES ROMDATA F14OnC6Support; - #undef F14_ON_C6_STATE_SUPPORT - #define F14_ON_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14OnC6Support}, - - CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support = - { - (PF_F14_ON_ES_IS_C6_SUPPORTED) CommonVoid, - (PF_F14_ON_ES_C6_INIT) CommonVoid - }; - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_FAMILY15H_OR == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; - #undef OPTION_C6_STATE_FEAT - #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, - extern CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support; - #undef F15_OR_C6_STATE_SUPPORT - #define F15_OR_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrC6Support}, - CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support = - { - (PF_F15_OR_ES_IS_C6_SUPPORTED) CommonVoid - }; - #endif - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] = -{ - F12_C6_STATE_SUPPORT - F14_ON_C6_STATE_SUPPORT - F15_OR_C6_STATE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable = -{ - (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &C6FamilyServiceArray[0] -}; - -#endif // _OPTION_C6_STATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionCpbInstall.h deleted file mode 100644 index 72720063c7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionCpbInstall.h +++ /dev/null @@ -1,144 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Core Performance Boost - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 46389 $ @e \$Date: 2011-02-01 11:22:49 +0800 (Tue, 01 Feb 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_CPB_INSTALL_H_ -#define _OPTION_CPB_INSTALL_H_ - -#include "cpuCpb.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPB_FEAT -#define F10_CPB_SUPPORT -#define F12_CPB_SUPPORT -#define F14_ON_CPB_SUPPORT -#define F15_OR_CPB_SUPPORT - -#if OPTION_CPB == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - // Family 10h - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_PH == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport; - #undef F10_CPB_SUPPORT - #define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport}, - #endif - #endif - #endif - - // Family 12h - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - #if OPTION_FAMILY12H_LN == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport; - #undef F12_CPB_SUPPORT - #define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport}, -// CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport = -// { -// (PF_F12_ES_CPB_INIT) CommonVoid -// }; - #endif - #endif - #endif - - // Family 14h - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - #if OPTION_FAMILY14H_ON == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport; - #undef F14_ON_CPB_SUPPORT - #define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport}, - #endif - #endif - #endif - - // Family 15h - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_FAMILY15H_OR == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport; - #undef F15_OR_CPB_SUPPORT - #define F15_OR_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15OrCpbSupport}, - - CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport = - { - (PF_F15_OR_ES_IS_CPB_SUPPORTED) CommonVoid - }; - #endif - #endif - #endif - - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] = -{ - F10_CPB_SUPPORT - F12_CPB_SUPPORT - F14_ON_CPB_SUPPORT - F15_OR_CPB_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable = -{ - (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CpbFamilyServiceArray[0] -}; - -#endif // _OPTION_CPB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionCpuCacheFlushOnHaltInstall.h deleted file mode 100644 index 15949d0e34..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionCpuCacheFlushOnHaltInstall.h +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: CPU Cache Flush On Halt - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44737 $ @e \$Date: 2011-01-05 15:59:55 +0800 (Wed, 05 Jan 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ -#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ - -#include "cpuPostInit.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT -#define F10_BL_CPU_CFOH_SUPPORT -#define F10_DA_CPU_CFOH_SUPPORT -#define F10_CPU_CFOH_SUPPORT -#define F15_OR_CPU_CFOH_SUPPORT - -#if OPTION_CPU_CFOH == TRUE - #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt; - #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT - #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt, - - #if OPTION_FAMILY10H_BL == TRUE - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt; - #undef F10_BL_CPU_CFOH_SUPPORT - #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt}, - #endif - - #if OPTION_FAMILY10H_DA == TRUE - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt; - #undef F10_DA_CPU_CFOH_SUPPORT - #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt}, - #endif - - #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt; - #undef F10_CPU_CFOH_SUPPORT - #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt; - #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT - #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt, - - #if OPTION_FAMILY15H_OR == TRUE - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt; - #undef F15_OR_CPU_CFOH_SUPPORT - #define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15OrCacheFlushOnHalt}, - #endif - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] = -{ - F10_BL_CPU_CFOH_SUPPORT - F10_DA_CPU_CFOH_SUPPORT - F10_CPU_CFOH_SUPPORT - F15_OR_CPU_CFOH_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable = -{ - (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CacheFlushOnHaltFamilyServiceArray[0] -}; - -#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionCpuCoreLevelingInstall.h deleted file mode 100644 index c598283b6b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionCpuCoreLevelingInstall.h +++ /dev/null @@ -1,109 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: CPU Core Leveling - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_ -#define _OPTION_CPU_CORELEVELING_INSTALL_H_ - - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_CORE_LEVELING_FEAT -#define F10_REVE_CPU_CORELEVELING_SUPPORT -#define F10_REVD_CPU_CORELEVELING_SUPPORT -#define F10_REVC_CPU_CORELEVELING_SUPPORT -#define F15_OR_CPU_CORELEVELING_SUPPORT - -#if OPTION_CPU_CORELEVLING == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) - // Family 10h - #if OPTION_FAMILY10H == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling; - #undef OPTION_CPU_CORE_LEVELING_FEAT - #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling, - #if OPTION_FAMILY10H_HY == TRUE - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling; - #undef F10_REVD_CPU_CORELEVELING_SUPPORT - #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling}, - #endif - - #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling; - #undef F10_REVC_CPU_CORELEVELING_SUPPORT - #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling}, - #endif - - #if (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling; - #undef F10_REVE_CPU_CORELEVELING_SUPPORT - #define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling}, - #endif - #endif - // Family 15h - #if OPTION_FAMILY15H == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling; - #undef OPTION_CPU_CORE_LEVELING_FEAT - #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling, - - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling; - #undef F15_OR_CPU_CORELEVELING_SUPPORT - #define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling}, - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] = -{ - F10_REVE_CPU_CORELEVELING_SUPPORT - F10_REVD_CPU_CORELEVELING_SUPPORT - F10_REVC_CPU_CORELEVELING_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable = -{ - (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CoreLevelingFamilyServiceArray[0] -}; - -#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionCpuFamiliesInstall.h deleted file mode 100644 index b161cd3be7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionCpuFamiliesInstall.h +++ /dev/null @@ -1,382 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of all appropriate CPU family specific support. - * - * This file generates the defaults tables for all family specific - * combinations. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -/* Default all CPU Specific Service members to off. They - will be enabled as needed by cross referencing families - with entry points in the family / model install files. */ -#define GET_PSTATE_POWER FALSE -#define GET_PSTATE_FREQ FALSE -#define DISABLE_PSTATE FALSE -#define TRANSITION_PSTATE FALSE -#define PROC_IDD_MAX FALSE -#define GET_TSC_RATE FALSE -#define PSTATE_TRANSITION_LATENCY FALSE -#define GET_PSTATE_REGISTER_INFO FALSE -#define GET_PSTATE_MAX_STATE FALSE -#define SET_PSTATE_LEVELING_REG FALSE -#define GET_NB_FREQ FALSE -#define GET_NB_IDD_MAX FALSE -#define IS_NBCOF_INIT_NEEDED FALSE -#define AP_INITIAL_LAUNCH FALSE -#define GET_AP_MAILBOX_FROM_HW FALSE -#define SET_AP_CORE_NUMBER FALSE -#define GET_AP_CORE_NUMBER FALSE -#define TRANSFER_AP_CORE_NUMBER FALSE -#define ID_POSITION_INITIAL_APICID FALSE -#define SAVE_FEATURES FALSE -#define WRITE_FEATURES FALSE -#define SET_DOWN_CORE_REG FALSE -#define SET_WARM_RESET_FLAG FALSE -#define GET_WARM_RESET_FLAG FALSE -#define USES_REGISTER_TABLES FALSE -#define BASE_FAMILY_PCI FALSE -#define MODEL_SPECIFIC_PCI FALSE -#define BASE_FAMILY_MSR FALSE -#define MODEL_SPECIFIC_MSR FALSE -#define BRAND_STRING1 FALSE -#define BRAND_STRING2 FALSE -#define BASE_FAMILY_HT_PCI FALSE -#define MODEL_SPECIFIC_HT_PCI FALSE -#define BASE_FAMILY_WORKAROUNDS FALSE -#define GET_PATCHES FALSE -#define GET_PATCHES_EQUIVALENCE_TABLE FALSE -#define GET_CACHE_INFO FALSE -#define GET_SYSTEM_PM_TABLE FALSE -#define GET_WHEA_INIT FALSE -#define GET_CFOH_REG FALSE -#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE -#define IS_NB_PSTATE_ENABLED FALSE - -/* - * Pull in family specific services based on entry point - */ -#if AGESA_ENTRY_INIT_RESET == TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE - #undef GET_AP_MAILBOX_FROM_HW - #define GET_AP_MAILBOX_FROM_HW TRUE - #undef SET_WARM_RESET_FLAG - #define SET_WARM_RESET_FLAG TRUE - #undef GET_WARM_RESET_FLAG - #define GET_WARM_RESET_FLAG TRUE - #undef GET_CACHE_INFO - #define GET_CACHE_INFO TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef TRANSFER_AP_CORE_NUMBER - #define TRANSFER_AP_CORE_NUMBER TRUE -#endif - -#if AGESA_ENTRY_INIT_RECOVERY == TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE - #undef USES_REGISTER_TABLES - #define USES_REGISTER_TABLES TRUE - #undef BASE_FAMILY_PCI - #define BASE_FAMILY_PCI TRUE - #undef MODEL_SPECIFIC_PCI - #define MODEL_SPECIFIC_PCI TRUE - #undef BASE_FAMILY_MSR - #define BASE_FAMILY_MSR TRUE - #undef MODEL_SPECIFIC_MSR - #define MODEL_SPECIFIC_MSR TRUE - #undef GET_CACHE_INFO - #define GET_CACHE_INFO TRUE - #undef GET_PLATFORM_TYPE_SPECIFIC_INFO - #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE - #undef IS_NB_PSTATE_ENABLED - #define IS_NB_PSTATE_ENABLED TRUE - #undef GET_PATCHES - #define GET_PATCHES TRUE - #undef GET_PATCHES_EQUIVALENCE_TABLE - #define GET_PATCHES_EQUIVALENCE_TABLE TRUE -#endif - -#if AGESA_ENTRY_INIT_EARLY == TRUE - #undef TRANSITION_PSTATE - #define TRANSITION_PSTATE TRUE - #undef DISABLE_PSTATE - #define DISABLE_PSTATE TRUE - #undef PROC_IDD_MAX - #define PROC_IDD_MAX TRUE - #undef GET_TSC_RATE - #define GET_TSC_RATE TRUE - #undef GET_NB_FREQ - #define GET_NB_FREQ TRUE - #undef GET_NB_IDD_MAX - #define GET_NB_IDD_MAX TRUE - #undef IS_NBCOF_INIT_NEEDED - #define IS_NBCOF_INIT_NEEDED TRUE - #undef AP_INITIAL_LAUNCH - #define AP_INITIAL_LAUNCH TRUE - #undef GET_AP_MAILBOX_FROM_HW - #define GET_AP_MAILBOX_FROM_HW TRUE - #undef SET_AP_CORE_NUMBER - #define SET_AP_CORE_NUMBER TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef TRANSFER_AP_CORE_NUMBER - #define TRANSFER_AP_CORE_NUMBER TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE - #undef SET_DOWN_CORE_REG - #define SET_DOWN_CORE_REG TRUE - #undef SET_WARM_RESET_FLAG - #define SET_WARM_RESET_FLAG TRUE - #undef GET_WARM_RESET_FLAG - #define GET_WARM_RESET_FLAG TRUE - #undef USES_REGISTER_TABLES - #define USES_REGISTER_TABLES TRUE - #undef BASE_FAMILY_PCI - #define BASE_FAMILY_PCI TRUE - #undef MODEL_SPECIFIC_PCI - #define MODEL_SPECIFIC_PCI TRUE - #undef BASE_FAMILY_MSR - #define BASE_FAMILY_MSR TRUE - #undef MODEL_SPECIFIC_MSR - #define MODEL_SPECIFIC_MSR TRUE - #undef BRAND_STRING1 - #define BRAND_STRING1 TRUE - #undef BRAND_STRING2 - #define BRAND_STRING2 TRUE - #undef BASE_FAMILY_HT_PCI - #define BASE_FAMILY_HT_PCI TRUE - #undef MODEL_SPECIFIC_HT_PCI - #define MODEL_SPECIFIC_HT_PCI TRUE - #undef BASE_FAMILY_WORKAROUNDS - #define BASE_FAMILY_WORKAROUNDS TRUE - #undef GET_PATCHES - #define GET_PATCHES TRUE - #undef GET_PATCHES_EQUIVALENCE_TABLE - #define GET_PATCHES_EQUIVALENCE_TABLE TRUE - #undef GET_SYSTEM_PM_TABLE - #define GET_SYSTEM_PM_TABLE TRUE - #undef GET_CACHE_INFO - #define GET_CACHE_INFO TRUE - #undef GET_PLATFORM_TYPE_SPECIFIC_INFO - #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE - #undef IS_NB_PSTATE_ENABLED - #define IS_NB_PSTATE_ENABLED TRUE -#endif - -#if AGESA_ENTRY_INIT_POST == TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE - #undef GET_PSTATE_POWER - #define GET_PSTATE_POWER TRUE - #undef GET_PSTATE_FREQ - #define GET_PSTATE_FREQ TRUE - #undef TRANSITION_PSTATE - #define TRANSITION_PSTATE TRUE - #undef PROC_IDD_MAX - #define PROC_IDD_MAX TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef GET_PSTATE_REGISTER_INFO - #define GET_PSTATE_REGISTER_INFO TRUE - #undef GET_PSTATE_MAX_STATE - #define GET_PSTATE_MAX_STATE TRUE - #undef SET_PSTATE_LEVELING_REG - #define SET_PSTATE_LEVELING_REG TRUE - #undef SET_WARM_RESET_FLAG - #define SET_WARM_RESET_FLAG TRUE - #undef GET_WARM_RESET_FLAG - #define GET_WARM_RESET_FLAG TRUE - #undef SAVE_FEATURES - #define SAVE_FEATURES TRUE - #undef WRITE_FEATURES - #define WRITE_FEATURES TRUE - #undef GET_CFOH_REG - #define GET_CFOH_REG TRUE - #undef IS_NB_PSTATE_ENABLED - #define IS_NB_PSTATE_ENABLED TRUE -#endif - -#if AGESA_ENTRY_INIT_ENV == TRUE -#endif - -#if AGESA_ENTRY_INIT_MID == TRUE -#endif - -#if AGESA_ENTRY_INIT_LATE == TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef GET_PSTATE_FREQ - #define GET_PSTATE_FREQ TRUE - #undef TRANSITION_PSTATE - #define TRANSITION_PSTATE TRUE - #undef PSTATE_TRANSITION_LATENCY - #define PSTATE_TRANSITION_LATENCY TRUE - #undef GET_WHEA_INIT - #define GET_WHEA_INIT TRUE - #undef GET_PLATFORM_TYPE_SPECIFIC_INFO - #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE - #undef GET_TSC_RATE - #define GET_TSC_RATE TRUE - #undef BRAND_STRING1 - #define BRAND_STRING1 TRUE - #undef BRAND_STRING2 - #define BRAND_STRING2 TRUE -#endif - -#if AGESA_ENTRY_INIT_S3SAVE == TRUE -#endif - -#if AGESA_ENTRY_INIT_RESUME == TRUE - #undef GET_CFOH_REG - #define GET_CFOH_REG TRUE -#endif - -#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE -#endif - -#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE -#endif - -/* - * Initialize PCI MMIO mask to 0 - */ -#define FAMILY_MMIO_BASE_MASK (0ull) - - -/* - * Initialize all families to disabled - */ -#define OPT_F12_TABLE - -#define OPT_F12_ID_TABLE - - -/* - * Install family specific support - */ - -#if (OPTION_FAMILY12H == TRUE) - #include "OptionFamily12hInstall.h" -#endif - -/* - * Process PCI MMIO mask - */ - -// If size is 0, but base is not, break the build. -#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0) - #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 -#endif - -// If base is 0, but size is not, break the build. -#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0) - #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater -#endif - -#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0) - // Both are non-zero, begin further processing. - - // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB. - #if (CFG_PCI_MMIO_BASE < 0x800000) - #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater - #endif - - // Break the build if the address is too high for the enabled families. - #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0) - #error BLDCFG: Invalid PCI MMIO base address for the installed CPU families - #endif - - // If the size parameter is not valid, break the build. - #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16) - #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256) - #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 - #endif - #endif - - #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1) - // If the base is not aligned according to size, break the build. - #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0) - #error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size - #endif - #undef PCI_MMIO_ALIGNMENT -#endif - -/* - * Process sockets / modules - */ -#ifndef ADVCFG_PLATFORM_SOCKETS - #error BLDOPT Set Family supported sockets. -#endif -#ifndef ADVCFG_PLATFORM_MODULES - #error BLDOPT Set Family supported modules. -#endif - -CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration = -{ - ADVCFG_PLATFORM_SOCKETS, - ADVCFG_PLATFORM_MODULES -}; - -/* - * Instantiate global data needed for processor identification - */ -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] = -{ - OPT_F12_TABLE -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable = -{ - (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CpuSupportedFamiliesArray[0] -}; - - -CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] = -{ - OPT_F12_ID_TABLE -}; - -CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable = -{ - (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)), - CpuSupportedFamilyIdArray -}; diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionCpuFeaturesInstall.h deleted file mode 100644 index ba4b42b8fb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionCpuFeaturesInstall.h +++ /dev/null @@ -1,75 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of multiple CPU features. - * - * Aggregates enabled CPU features into a list for the dispatcher to process. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_CPU_FEATURES_INSTALL_H_ -#define _OPTION_CPU_FEATURES_INSTALL_H_ - -#include "OptionHwC1eInstall.h" -#include "OptionMsgBasedC1eInstall.h" -#include "OptionSwC1eInstall.h" -#include "OptionL3FeaturesInstall.h" -#include "OptionCpuCoreLevelingInstall.h" -#include "OptionIoCstateInstall.h" -#include "OptionC6Install.h" -#include "OptionCpbInstall.h" -#include "OptionCpuCacheFlushOnHaltInstall.h" -#include "OptionLowPwrPstateInstall.h" -#include "OptionPreserveMailboxInstall.h" - -CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] = -{ - OPTION_HW_C1E_FEAT - OPTION_MSG_BASED_C1E_FEAT - OPTION_SW_C1E_FEAT - OPTION_L3_FEAT - OPTION_CPU_CORE_LEVELING_FEAT - OPTION_IO_CSTATE_FEAT - OPTION_C6_STATE_FEAT - OPTION_CPB_FEAT - OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT - OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT // this function should be run before creating ACPI objects and after Pstate initialization - OPTION_PRESERVE_MAILBOX_FEAT - NULL -}; - - -#endif // _OPTION_CPU_FEATURES_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h deleted file mode 100644 index ead4fcec6a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h +++ /dev/null @@ -1,206 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: DMI - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_DMI_INSTALL_H_ -#define _OPTION_DMI_INSTALL_H_ - -#include "cpuLateInit.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_DMI - #error BLDOPT: Option not defined: "OPTION_DMI" - #endif - #if OPTION_DMI == TRUE - OPTION_DMI_FEATURE GetDmiInfoMain; - OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer; - #define USER_DMI_OPTION &GetDmiInfoMain - #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer - - // This additional check keeps AP launch routines from being unnecessarily included - // in single socket systems. - #if OPTION_MULTISOCKET == TRUE - #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, - #else - #define CPU_DMI_AP_GET_TYPE4_TYPE7 - #endif - - // Family 10 - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - extern PROC_FAMILY_TABLE ProcFamily10DmiTable; - #define FAM10_DMI_SUPPORT FAM10_ENABLED, - #define FAM10_DMI_TABLE &ProcFamily10DmiTable, - #else - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #endif - #else - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #endif - - // Family 12 - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - extern PROC_FAMILY_TABLE ProcFamily12DmiTable; - #define FAM12_DMI_SUPPORT FAM12_ENABLED, - #define FAM12_DMI_TABLE &ProcFamily12DmiTable, - #else - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #endif - #else - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #endif - - // Family 14 - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - extern PROC_FAMILY_TABLE ProcFamily14DmiTable; - #define FAM14_DMI_SUPPORT FAM14_ENABLED, - #define FAM14_DMI_TABLE &ProcFamily14DmiTable, - #else - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #endif - #else - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #endif - - // Family 15 - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - extern PROC_FAMILY_TABLE ProcFamily15OrDmiTable; - #define FAM15_OR_DMI_SUPPORT FAM15_OR_ENABLED, - #define FAM15_OR_DMI_TABLE &ProcFamily15OrDmiTable, - #else - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #endif - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #else - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #endif - #else - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #endif - - #else - OPTION_DMI_FEATURE GetDmiInfoStub; - OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; - #define USER_DMI_OPTION GetDmiInfoStub - #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #define CPU_DMI_AP_GET_TYPE4_TYPE7 - #endif -#else - OPTION_DMI_FEATURE GetDmiInfoStub; - OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; - #define USER_DMI_OPTION GetDmiInfoStub - #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #define CPU_DMI_AP_GET_TYPE4_TYPE7 -#endif - -/// DMI supported families enum -typedef enum { - FAM10_DMI_SUPPORT ///< Conditionally define F10 support - FAM12_DMI_SUPPORT ///< Conditionally define F12 support - FAM14_DMI_SUPPORT ///< Conditionally define F14 support - FAM15_OR_DMI_SUPPORT ///< Conditionally define F15 OR support - FAM15_TN_DMI_SUPPORT ///< Conditionally define F15 TN support - NUM_DMI_FAMILIES ///< Number of installed families -} AGESA_DMI_SUPPORTED_FAM; - -/* Declare the Family List. An array of pointers to tables that each describe a family */ -CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = { - FAM10_DMI_TABLE - FAM12_DMI_TABLE - FAM14_DMI_TABLE - FAM15_OR_DMI_TABLE - FAM15_TN_DMI_TABLE - NULL -}; - -/* Declare the instance of the DMI option configuration structure */ -CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = { - DMI_STRUCT_VERSION, - USER_DMI_OPTION, - USER_DMI_RELEASE_BUFFER, - NUM_DMI_FAMILIES, - (VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl -}; - -#endif // _OPTION_DMI_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionFamily12hInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionFamily12hInstall.h deleted file mode 100644 index 63cb0ff3cb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionFamily12hInstall.h +++ /dev/null @@ -1,696 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of family 12h support - * - * This file generates the defaults tables for family 12h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_FAMILY_12H_INSTALL_H_ -#define _OPTION_FAMILY_12H_INSTALL_H_ - - -#include "OptionFamily12hEarlySample.h" - -/* - * Common Family 12h routines - */ -extern F_CPU_DISABLE_PSTATE F12DisablePstate; -extern F_CPU_TRANSITION_PSTATE F12TransitionPstate; -extern F_CPU_GET_TSC_RATE F12GetTscRate; -extern F_CPU_GET_NB_FREQ F12GetCurrentNbFrequency; -extern F_CPU_GET_NB_PSTATE_INFO F12GetNbPstateInfo; -extern F_CPU_IS_NBCOF_INIT_NEEDED F12GetNbCofVidUpdate; -extern F_CPU_AP_INITIAL_LAUNCH F12LaunchApCore; -extern F_CPU_GET_IDD_MAX F12GetProcIddMax; -extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F12GetApMailboxFromHardware; -extern F_CPU_GET_AP_CORE_NUMBER F12GetApCoreNumber; -extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F12CpuAmdCoreIdPositionInInitialApicId; -extern F_CPU_SET_DOWN_CORE_REGISTER F12SetDownCoreRegister; -extern F_CPU_SET_WARM_RESET_FLAG F12SetAgesaWarmResetFlag; -extern F_CPU_GET_WARM_RESET_FLAG F12GetAgesaWarmResetFlag; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString1; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString2; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12CacheInfo; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12SysPmTable; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12WheaInitData; -//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray; -extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F12GetPlatformTypeSpecificInfo; -extern CONST REGISTER_TABLE ROMDATA F12PciRegisterTable; -extern CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable; -extern CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable; -extern F_CPU_NUMBER_OF_PHYSICAL_CORES F12GetNumberOfPhysicalCores; -extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable; -extern F_IS_NB_PSTATE_ENABLED F12IsNbPstateEnabled; -#if OPTION_EARLY_SAMPLES == TRUE - extern CONST REGISTER_TABLE ROMDATA F12EarlySampleMsrRegisterTable; -#endif - -/* - * Install family 12h model 0 support - */ - -#ifdef OPTION_FAMILY12H_LN - #if OPTION_FAMILY12H_LN == TRUE - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicroCodePatchesStruct; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicrocodeEquivalenceTable; - - #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F12LnRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F12PciRegisterTable, - #endif - #if BASE_FAMILY_PCI == TRUE - &F12PerCorePciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F12MsrRegisterTable, - #if OPTION_EARLY_SAMPLES == TRUE - &F12EarlySampleMsrRegisterTable, - #endif - #endif - // the end. - NULL - }; - #endif - - #if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12LnTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; - #endif - - CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12LnServices = - { - 0, - #if DISABLE_PSTATE == TRUE - F12DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F12TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F12GetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F12GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F12GetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F12GetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F12GetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F12LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F12GetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F12GetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F12GetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F12CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - (PF_CPU_SAVE_FEATURES) CommonVoid, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - (PF_CPU_WRITE_FEATURES) CommonVoid, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F12SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F12GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - GetF12BrandIdString1, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - GetF12BrandIdString2, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetF12LnMicroCodePatchesStruct, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetF12LnMicrocodeEquivalenceTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF12CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF12SysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF12WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - F12GetPlatformTypeSpecificInfo, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - F12IsNbPstateEnabled, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - (PF_SET_HT_PHY_REGISTER) CommonVoid, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F12LnRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12LnTableEntryTypeDescriptors, - #else - NULL, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - NULL, - #else - NULL, - #endif - NULL, - InitCacheDisabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetCommonEarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif - }; - - #define LN_SOCKETS 1 - #define LN_MODULES 1 - #define LN_RECOVERY_SOCKETS 1 - #define LN_RECOVERY_MODULES 1 - extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF12LnLogicalIdAndRev; - #define OPT_F12_LN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF12LnLogicalIdAndRev, - #ifndef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS - #else - #if ADVCFG_PLATFORM_SOCKETS < LN_SOCKETS - #undef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS - #endif - #endif - #ifndef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES LN_MODULES - #else - #if ADVCFG_PLATFORM_MODULES < LN_MODULES - #undef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES LN_MODULES - #endif - #endif - - #if GET_PATCHES == TRUE - #define F12_LN_UCODE_02 - #define F12_LN_UCODE_0E - #define F12_LN_UCODE_0F - - // If a patch is required for recovery mode to function properly, add a - // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in. - #if AGESA_ENTRY_INIT_EARLY == TRUE - extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000f; - #undef F12_LN_UCODE_0F - #define F12_LN_UCODE_0F &CpuF12MicrocodePatch0300000f, - #if OPTION_EARLY_SAMPLES == TRUE - extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000002; - extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000e; - #undef F12_LN_UCODE_02 - #define F12_LN_UCODE_02 &CpuF12MicrocodePatch03000002, - #undef F12_LN_UCODE_0E - #define F12_LN_UCODE_0E &CpuF12MicrocodePatch0300000e, - #endif - #endif - - CONST MICROCODE_PATCHES ROMDATA *CpuF12LnMicroCodePatchArray[] = - { - F12_LN_UCODE_0F - F12_LN_UCODE_0E - F12_LN_UCODE_02 - NULL - }; - - CONST UINT8 ROMDATA CpuF12LnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF12LnMicroCodePatchArray) / sizeof (CpuF12LnMicroCodePatchArray[0])) - 1); - #endif - - #if OPTION_EARLY_SAMPLES == TRUE - extern F_F12_ES_NB_PSTATE_INIT F12NbPstateInitEarlySampleHook; - extern F_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitEarlySampleHook; - - CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport = - { - #if AGESA_ENTRY_INIT_EARLY == TRUE - F12PowerPlaneInitEarlySampleHook, - #else - (PF_F12_ES_POWER_PLANE_INIT) CommonAssert, - #endif - #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) - F12NbPstateInitEarlySampleHook - #else - (PF_F12_ES_NB_PSTATE_INIT) CommonAssert - #endif - }; - #else - CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport = - { - #if AGESA_ENTRY_INIT_EARLY == TRUE - (PF_F12_ES_POWER_PLANE_INIT) CommonVoid, - #else - (PF_F12_ES_POWER_PLANE_INIT) CommonAssert, - #endif - #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) - (PF_F12_ES_NB_PSTATE_INIT) CommonVoid - #else - (PF_F12_ES_NB_PSTATE_INIT) CommonAssert - #endif - }; - #endif - - #define OPT_F12_LN_CPU {AMD_FAMILY_12_LN, &cpuF12LnServices}, - #else // OPTION_FAMILY12H_LN == TRUE - #define OPT_F12_LN_CPU - #define OPT_F12_LN_ID - #endif // OPTION_FAMILY12H_LN == TRUE -#else // defined (OPTION_FAMILY12H_LN) - #define OPT_F12_LN_CPU - #define OPT_F12_LN_ID -#endif // defined (OPTION_FAMILY12H_LN) - - -/* - * Install unknown family 12h support - */ - -#if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F12UnknownRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F12PciRegisterTable, - #endif - #if BASE_FAMILY_PCI == TRUE - &F12PerCorePciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F12MsrRegisterTable, - #endif - // the end. - NULL - }; -#endif - -#if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12UnknownTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; -#endif - -CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12UnknownServices = -{ - 0, - #if DISABLE_PSTATE == TRUE - F12DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F12TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F12GetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F12GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F12GetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F12GetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F12GetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F12LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F12GetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F12GetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F12GetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F12CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - (PF_CPU_SAVE_FEATURES) CommonVoid, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - (PF_CPU_WRITE_FEATURES) CommonVoid, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F12SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F12GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - GetF12BrandIdString1, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - GetF12BrandIdString2, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetEmptyArray, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetEmptyArray, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF12CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF12SysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF12WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - F12GetPlatformTypeSpecificInfo, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - F12IsNbPstateEnabled, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - (PF_SET_HT_PHY_REGISTER) CommonVoid, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F12UnknownRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12UnknownTableEntryTypeDescriptors, - #else - NULL, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - NULL, - #else - NULL, - #endif - NULL, - InitCacheDisabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetCommonEarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif -}; - - // Family 12h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate. -#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull) - #undef FAMILY_MMIO_BASE_MASK - #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull) -#endif - -#undef OPT_F12_ID_TABLE -#define OPT_F12_ID_TABLE {0x12ul, {AMD_FAMILY_12, AMD_F12_UNKNOWN}, F12LogicalIdTable, (sizeof (F12LogicalIdTable) / sizeof (F12LogicalIdTable[0]))}, -#define OPT_F12_UNKNOWN_CPU {AMD_FAMILY_12, &cpuF12UnknownServices}, - -#undef OPT_F12_TABLE -#define OPT_F12_TABLE OPT_F12_LN_CPU OPT_F12_UNKNOWN_CPU - -#if OPTION_FS1_SOCKET_SUPPORT == TRUE - extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFs1; - extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFs1; - #define F12_FS1_BRANDSTRING1 &F12LnBrandIdString1ArrayFs1, - #define F12_FS1_BRANDSTRING2 &F12LnBrandIdString2ArrayFs1, -#else - #define F12_FS1_BRANDSTRING1 - #define F12_FS1_BRANDSTRING2 -#endif -#if OPTION_FM1_SOCKET_SUPPORT == TRUE - extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFm1; - extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFm1; - #define F12_FM1_BRANDSTRING1 &F12LnBrandIdString1ArrayFm1, - #define F12_FM1_BRANDSTRING2 &F12LnBrandIdString2ArrayFm1, -#else - #define F12_FM1_BRANDSTRING1 - #define F12_FM1_BRANDSTRING2 -#endif -#if OPTION_FP1_SOCKET_SUPPORT == TRUE - #define F12_FP1_BRANDSTRING1 NULL, - #define F12_FP1_BRANDSTRING2 NULL, -#else - #define F12_FP1_BRANDSTRING1 - #define F12_FP1_BRANDSTRING2 -#endif - -#if BRAND_STRING1 == TRUE - CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString1Tables[] = - { - F12_FS1_BRANDSTRING1 - F12_FM1_BRANDSTRING1 - F12_FP1_BRANDSTRING1 - }; - - CONST UINT8 F12BrandIdString1TableCount = (sizeof (F12BrandIdString1Tables) / sizeof (F12BrandIdString1Tables[0])); -#endif - -#if BRAND_STRING2 == TRUE - CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString2Tables[] = - { - F12_FS1_BRANDSTRING2 - F12_FM1_BRANDSTRING2 - F12_FP1_BRANDSTRING2 - }; - - CONST UINT8 F12BrandIdString2TableCount = (sizeof (F12BrandIdString2Tables) / sizeof (F12BrandIdString2Tables[0])); -#endif - -CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F12LogicalIdTable[] = -{ - OPT_F12_LN_ID -}; - -#endif // _OPTION_FAMILY_12H_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionFchInstall.h deleted file mode 100644 index f1799f6507..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionFchInstall.h +++ /dev/null @@ -1,928 +0,0 @@ -/********************************************************************************* -; -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;*********************************************************************************/ - -#ifndef _OPTION_FCH_INSTALL_H_ -#define _OPTION_FCH_INSTALL_H_ - -#include "AmdFch.h" - -#ifndef FCH_SUPPORT - #define FCH_SUPPORT FALSE -#endif - - -/* ACPI block register offset definitions */ -#define PM1_STATUS_OFFSET 0x00 -#define PM1_ENABLE_OFFSET 0x02 -#define PM_CONTROL_OFFSET 0x04 -#define PM_TIMER_OFFSET 0x08 -#define CPU_CONTROL_OFFSET 0x10 -#define EVENT_STATUS_OFFSET 0x20 -#define EVENT_ENABLE_OFFSET 0x24 - - -#if FCH_SUPPORT == TRUE - /* - * FCH subfunctions - */ - #ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - extern FCH_TASK_ENTRY FchInitResetHwAcpiP; - extern FCH_TASK_ENTRY FchInitResetHwAcpi; - extern FCH_TASK_ENTRY FchInitResetAb; - extern FCH_TASK_ENTRY FchInitResetSpi; - extern FCH_TASK_ENTRY FchInitResetGec; - extern FCH_TASK_ENTRY FchInitResetSata; - extern FCH_TASK_ENTRY FchInitResetLpc; - extern FCH_TASK_ENTRY FchInitResetPcib; - extern FCH_TASK_ENTRY FchInitResetPcie; - extern FCH_TASK_ENTRY FchInitResetGpp; - extern FCH_TASK_ENTRY FchInitResetUsb; - extern FCH_TASK_ENTRY FchInitResetEhci; - extern FCH_TASK_ENTRY FchInitResetOhci; - extern FCH_TASK_ENTRY FchInitResetXhci; - extern FCH_TASK_ENTRY FchInitResetImc; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - extern FCH_TASK_ENTRY FchInitEnvUsbXhci; - extern FCH_TASK_ENTRY FchInitEnvUsbOhci; - extern FCH_TASK_ENTRY FchInitEnvUsbEhci; - extern FCH_TASK_ENTRY FchInitEnvUsb; - extern FCH_TASK_ENTRY FchInitEnvAb; - extern FCH_TASK_ENTRY FchInitEnvGpp; - extern FCH_TASK_ENTRY FchInitEnvPcie; - extern FCH_TASK_ENTRY FchInitEnvPcib; - extern FCH_TASK_ENTRY FchInitEnvHwAcpiP; - extern FCH_TASK_ENTRY FchInitEnvHwAcpi; - extern FCH_TASK_ENTRY FchInitEnvAbSpecial; - extern FCH_TASK_ENTRY FchInitEnvSpi; - extern FCH_TASK_ENTRY FchInitEnvGec; - extern FCH_TASK_ENTRY FchInitEnvSata; - extern FCH_TASK_ENTRY FchInitEnvIde; - extern FCH_TASK_ENTRY FchInitEnvSd; - extern FCH_TASK_ENTRY FchInitEnvIr; - extern FCH_TASK_ENTRY FchInitEnvAzalia; - extern FCH_TASK_ENTRY FchInitEnvHwm; - extern FCH_TASK_ENTRY FchInitEnvImc; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_MID - #if AGESA_ENTRY_INIT_MID == TRUE - extern FCH_TASK_ENTRY FchInitMidHwm; - extern FCH_TASK_ENTRY FchInitMidAzalia; - extern FCH_TASK_ENTRY FchInitMidGec; - extern FCH_TASK_ENTRY FchInitMidSata; - extern FCH_TASK_ENTRY FchInitMidIde; - extern FCH_TASK_ENTRY FchInitMidAb; - extern FCH_TASK_ENTRY FchInitMidUsb; - extern FCH_TASK_ENTRY FchInitMidUsbEhci; - extern FCH_TASK_ENTRY FchInitMidUsbOhci; - extern FCH_TASK_ENTRY FchInitMidUsbXhci; - extern FCH_TASK_ENTRY FchInitMidImc; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - extern FCH_TASK_ENTRY FchInitLateHwAcpi; - extern FCH_TASK_ENTRY FchInitLateSpi; - extern FCH_TASK_ENTRY FchInitLateGec; - extern FCH_TASK_ENTRY FchInitLateSata; - extern FCH_TASK_ENTRY FchInitLateIde; - extern FCH_TASK_ENTRY FchInitLatePcib; - extern FCH_TASK_ENTRY FchInitLateAb; - extern FCH_TASK_ENTRY FchInitLatePcie; - extern FCH_TASK_ENTRY FchInitLateGpp; - extern FCH_TASK_ENTRY FchInitLateUsb; - extern FCH_TASK_ENTRY FchInitLateUsbEhci; - extern FCH_TASK_ENTRY FchInitLateUsbOhci; - extern FCH_TASK_ENTRY FchInitLateUsbXhci; - extern FCH_TASK_ENTRY FchInitLateImc; - extern FCH_TASK_ENTRY FchInitLateAzalia; - extern FCH_TASK_ENTRY FchInitLateHwm; - #endif - #endif - - extern FCH_TASK_ENTRY FchTaskDummy; - /* FCH Interface entries */ - extern FCH_INIT CommonFchInitStub; - - /* FCH Interface entries */ - #ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - extern FCH_INIT FchInitReset; - extern FCH_INIT FchResetConstructor; - - #define FP_FCH_INIT_RESET &FchInitReset - #define FP_FCH_INIT_RESET_CONSTRUCT &FchResetConstructor - #else - #define FP_FCH_INIT_RESET &CommonFchInitStub - #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - extern FCH_INIT FchInitEnv; - extern FCH_INIT FchEnvConstructor; - - #define FP_FCH_INIT_ENV &FchInitEnv - #define FP_FCH_INIT_ENV_CONSTRUCT &FchEnvConstructor - #else - #define FP_FCH_INIT_ENV &CommonFchInitStub - #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_MID - #if AGESA_ENTRY_INIT_MID == TRUE - extern FCH_INIT FchInitMid; - extern FCH_INIT FchMidConstructor; - - #define FP_FCH_INIT_MID &FchInitMid - #define FP_FCH_INIT_MID_CONSTRUCT &FchMidConstructor - #else - #define FP_FCH_INIT_MID &CommonFchInitStub - #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - extern FCH_INIT FchInitLate; - extern FCH_INIT FchLateConstructor; - - #define FP_FCH_INIT_LATE &FchInitLate - #define FP_FCH_INIT_LATE_CONSTRUCT &FchLateConstructor - #else - #define FP_FCH_INIT_LATE &CommonFchInitStub - #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub - #endif - #endif - - /* FCH subcomponent build options */ - #undef FCH_NO_HWACPI_SUPPORT - #undef FCH_NO_AB_SUPPORT - #undef FCH_NO_SPI_SUPPORT - #undef FCH_NO_GEC_SUPPORT - #undef FCH_NO_SATA_SUPPORT - #undef FCH_NO_IDE_SUPPORT - #undef FCH_NO_LPC_SUPPORT - #undef FCH_NO_PCIB_SUPPORT - #undef FCH_NO_PCIE_SUPPORT - #undef FCH_NO_GPP_SUPPORT - #undef FCH_NO_USB_SUPPORT - #undef FCH_NO_EHCI_SUPPORT - #undef FCH_NO_OHCI_SUPPORT - #undef FCH_NO_XHCI_SUPPORT - #undef FCH_NO_IMC_SUPPORT - #undef FCH_NO_SD_SUPPORT - #undef FCH_NO_IR_SUPPORT - #undef FCH_NO_AZALIA_SUPPORT - #undef FCH_NO_HWM_SUPPORT - - // Following are determined by silicon characteristics - #if (OPTION_FAMILY14H_KR == TRUE) - #define FCH_NO_GPP_SUPPORT TRUE - #define FCH_NO_PCIB_SUPPORT TRUE - #define FCH_NO_PCIE_SUPPORT TRUE - - #else - #if (OPTION_FAMILY15H_TN == TRUE) - //#define FCH_NO_GEC_SUPPORT TRUE - #else - #error FCH_SUPPORT: No chip type selected. - #endif - #endif - - - // - // Installable blocks depending on build switches - // - #ifndef FCH_NO_HWACPI_SUPPORT - #define BLOCK_HWACPI_SIZE sizeof (FCH_ACPI) - #define InstallFchInitResetHwAcpiP &FchInitResetHwAcpiP - #define InstallFchInitResetHwAcpi &FchInitResetHwAcpi - #define InstallFchInitEnvHwAcpiP &FchInitEnvHwAcpiP - #define InstallFchInitEnvHwAcpi &FchInitEnvHwAcpi - #define InstallFchInitMidHwAcpi &FchTaskDummy - #define InstallFchInitLateHwAcpi &FchInitLateHwAcpi - #else - #define BLOCK_HWACPI_SIZE 0 - #define InstallFchInitResetHwAcpiP &FchTaskDummy - #define InstallFchInitResetHwAcpi &FchTaskDummy - #define InstallFchInitEnvHwAcpi &FchTaskDummy - #define InstallFchInitMidHwAcpi &FchTaskDummy - #define InstallFchInitLateHwAcpi &FchTaskDummy - #endif - - #ifndef FCH_NO_AB_SUPPORT - #define BLOCK_AB_SIZE sizeof (FCH_AB) - #define InstallFchInitResetAb &FchInitResetAb - #define InstallFchInitEnvAb &FchInitEnvAb - #define InstallFchInitEnvAbS &FchInitEnvAbSpecial - #define InstallFchInitMidAb &FchInitMidAb - #define InstallFchInitLateAb &FchInitLateAb - #else - #define BLOCK_AB_SIZE 0 - #define InstallFchInitResetAb &FchTaskDummy - #define InstallFchInitEnvAb &FchTaskDummy - #define InstallFchInitEnvAbS &FchTaskDummy - #define InstallFchInitMidAb &FchTaskDummy - #define InstallFchInitLateAb &FchTaskDummy - #endif - - #ifndef FCH_NO_SPI_SUPPORT - #define BLOCK_SPI_SIZE sizeof (FCH_SPI) - #define InstallFchInitResetSpi &FchInitResetSpi - #define InstallFchInitEnvSpi &FchInitEnvSpi - #define InstallFchInitMidSpi &FchTaskDummy - #define InstallFchInitLateSpi &FchInitLateSpi - #else - #define BLOCK_SPI_SIZE 0 - #define InstallFchInitResetSpi &FchTaskDummy - #define InstallFchInitEnvSpi &FchTaskDummy - #define InstallFchInitMidSpi &FchTaskDummy - #define InstallFchInitLateSpi &FchTaskDummy - #endif - - #ifndef FCH_NO_GEC_SUPPORT - #define BLOCK_GEC_SIZE sizeof (FCH_GEC) - #define InstallFchInitResetGec &FchInitResetGec - #define InstallFchInitEnvGec &FchInitEnvGec - #define InstallFchInitMidGec &FchInitMidGec - #define InstallFchInitLateGec &FchInitLateGec - #else - #define BLOCK_GEC_SIZE 0 - #define InstallFchInitResetGec &FchTaskDummy - #define InstallFchInitEnvGec &FchTaskDummy - #define InstallFchInitMidGec &FchTaskDummy - #define InstallFchInitLateGec &FchTaskDummy - #endif - - #ifndef FCH_NO_SATA_SUPPORT - #define BLOCK_SATA_SIZE sizeof (FCH_SATA) - #define InstallFchInitResetSata &FchInitResetSata - #define InstallFchInitEnvSata &FchInitEnvSata - #define InstallFchInitMidSata &FchInitMidSata - #define InstallFchInitLateSata &FchInitLateSata - #else - #define BLOCK_SATA_SIZE 0 - #define InstallFchInitResetSata &FchTaskDummy - #define InstallFchInitEnvSata &FchTaskDummy - #define InstallFchInitMidSata &FchTaskDummy - #define InstallFchInitLateSata &FchTaskDummy - #endif - - #ifndef FCH_NO_IDE_SUPPORT - #define BLOCK_IDE_SIZE sizeof (FCH_IDE) - #define InstallFchInitResetIde &FchTaskDummy - #define InstallFchInitEnvIde &FchInitEnvIde - #define InstallFchInitMidIde &FchInitMidIde - #define InstallFchInitLateIde &FchInitLateIde - #else - #define BLOCK_IDE_SIZE 0 - #define InstallFchInitResetIde &FchTaskDummy - #define InstallFchInitEnvIde &FchTaskDummy - #define InstallFchInitMidIde &FchTaskDummy - #define InstallFchInitLateIde &FchTaskDummy - #endif - - #ifndef FCH_NO_LPC_SUPPORT - #define BLOCK_LPC_SIZE sizeof (FCH_LPC) - #define InstallFchInitResetLpc &FchInitResetLpc - #define InstallFchInitEnvLpc &FchTaskDummy - #define InstallFchInitMidLpc &FchTaskDummy - #define InstallFchInitLateLpc &FchTaskDummy - #else - #define BLOCK_LPC_SIZE 0 - #define InstallFchInitResetLpc &FchTaskDummy - #define InstallFchInitEnvLpc &FchTaskDummy - #define InstallFchInitMidLpc &FchTaskDummy - #define InstallFchInitLateLpc &FchTaskDummy - #endif - - #ifndef FCH_NO_PCIB_SUPPORT - #define BLOCK_PCIB_SIZE sizeof (FCH_PCIB) - #define InstallFchInitResetPcib &FchInitResetPcib - #define InstallFchInitEnvPcib &FchInitEnvPcib - #define InstallFchInitMidPcib &FchTaskDummy - #define InstallFchInitLatePcib &FchInitLatePcib - #else - #define BLOCK_PCIB_SIZE 0 - #define InstallFchInitResetPcib &FchTaskDummy - #define InstallFchInitEnvPcib &FchTaskDummy - #define InstallFchInitMidPcib &FchTaskDummy - #define InstallFchInitLatePcib &FchTaskDummy - #endif - - #ifndef FCH_NO_PCIE_SUPPORT - #define InstallFchInitResetPcie &FchInitResetPcie - #define InstallFchInitEnvPcie &FchInitEnvPcie - #define InstallFchInitMidPcie &FchTaskDummy - #define InstallFchInitLatePcie &FchInitLatePcie - #else - #define InstallFchInitResetPcie &FchTaskDummy - #define InstallFchInitEnvPcie &FchTaskDummy - #define InstallFchInitMidPcie &FchTaskDummy - #define InstallFchInitLatePcie &FchTaskDummy - #endif - - #ifndef FCH_NO_GPP_SUPPORT - #define BLOCK_GPP_SIZE sizeof (FCH_GPP) - #define InstallFchInitResetGpp &FchInitResetGpp - #define InstallFchInitEnvGpp &FchInitEnvGpp - #define InstallFchInitMidGpp &FchTaskDummy - #define InstallFchInitLateGpp &FchInitLateGpp - #else - #define BLOCK_GPP_SIZE 0 - #define InstallFchInitResetGpp &FchTaskDummy - #define InstallFchInitEnvGpp &FchTaskDummy - #define InstallFchInitMidGpp &FchTaskDummy - #define InstallFchInitLateGpp &FchTaskDummy - #endif - - #ifndef FCH_NO_USB_SUPPORT - #define BLOCK_USB_SIZE sizeof (FCH_USB) - #define InstallFchInitResetUsb &FchInitResetUsb - #define InstallFchInitEnvUsb &FchInitEnvUsb - #define InstallFchInitMidUsb &FchInitMidUsb - #define InstallFchInitLateUsb &FchInitLateUsb - #else - #define BLOCK_USB_SIZE 0 - #define InstallFchInitResetUsb &FchTaskDummy - #define InstallFchInitEnvUsb &FchTaskDummy - #define InstallFchInitMidUsb &FchTaskDummy - #define InstallFchInitLateUsb &FchTaskDummy - #endif - - #ifndef FCH_NO_EHCI_SUPPORT - #define InstallFchInitResetUsbEhci &FchInitResetEhci - #define InstallFchInitEnvUsbEhci &FchInitEnvUsbEhci - #define InstallFchInitMidUsbEhci &FchInitMidUsbEhci - #define InstallFchInitLateUsbEhci &FchInitLateUsbEhci - #else - #define InstallFchInitResetUsbEhci &FchTaskDummy - #define InstallFchInitEnvUsbEhci &FchTaskDummy - #define InstallFchInitMidUsbEhci &FchTaskDummy - #define InstallFchInitLateUsbEhci &FchTaskDummy - #endif - - #ifndef FCH_NO_OHCI_SUPPORT - #define InstallFchInitResetUsbOhci &FchInitResetOhci - #define InstallFchInitEnvUsbOhci &FchInitEnvUsbOhci - #define InstallFchInitMidUsbOhci &FchInitMidUsbOhci - #define InstallFchInitLateUsbOhci &FchInitLateUsbOhci - #else - #define InstallFchInitResetUsbOhci &FchTaskDummy - #define InstallFchInitEnvUsbOhci &FchTaskDummy - #define InstallFchInitMidUsbOhci &FchTaskDummy - #define InstallFchInitLateUsbOhci &FchTaskDummy - #endif - - #ifndef FCH_NO_XHCI_SUPPORT - #define InstallFchInitResetUsbXhci &FchInitResetXhci - #define InstallFchInitEnvUsbXhci &FchInitEnvUsbXhci - #define InstallFchInitMidUsbXhci &FchInitMidUsbXhci - #define InstallFchInitLateUsbXhci &FchInitLateUsbXhci - #else - #define InstallFchInitResetUsbXhci &FchTaskDummy - #define InstallFchInitEnvUsbXhci &FchTaskDummy - #define InstallFchInitMidUsbXhci &FchTaskDummy - #define InstallFchInitLateUsbXhci &FchTaskDummy - #endif - - #ifndef FCH_NO_IMC_SUPPORT - #define BLOCK_IMC_SIZE sizeof (FCH_IMC) - #define InstallFchInitResetImc &FchInitResetImc - #define InstallFchInitEnvImc &FchInitEnvImc - #define InstallFchInitMidImc &FchInitMidImc - #define InstallFchInitLateImc &FchInitLateImc - #else - #define BLOCK_IMC_SIZE 0 - #define InstallFchInitResetImc &FchTaskDummy - #define InstallFchInitEnvImc &FchTaskDummy - #define InstallFchInitMidImc &FchTaskDummy - #define InstallFchInitLateImc &FchTaskDummy - #endif - - - #ifndef FCH_NO_SD_SUPPORT - #define BLOCK_SD_SIZE sizeof (FCH_SD) - #define InstallFchInitResetSd &FchTaskDummy - #define InstallFchInitEnvSd &FchInitEnvSd - #define InstallFchInitMidSd &FchTaskDummy - #define InstallFchInitLateSd &FchTaskDummy - #else - #define BLOCK_SD_SIZE 0 - #define InstallFchInitResetSd &FchTaskDummy - #define InstallFchInitEnvSd &FchTaskDummy - #define InstallFchInitMidSd &FchTaskDummy - #define InstallFchInitLateSd &FchTaskDummy - #endif - - #ifndef FCH_NO_IR_SUPPORT - #define BLOCK_IR_SIZE sizeof (FCH_IR) - #define InstallFchInitResetIr &FchTaskDummy - #define InstallFchInitEnvIr &FchInitEnvIr - #define InstallFchInitMidIr &FchTaskDummy - #define InstallFchInitLateIr &FchTaskDummy - #else - #define BLOCK_IR_SIZE 0 - #define InstallFchInitResetIr &FchTaskDummy - #define InstallFchInitEnvIr &FchTaskDummy - #define InstallFchInitMidIr &FchTaskDummy - #define InstallFchInitLateIr &FchTaskDummy - #endif - - #ifndef FCH_NO_AZALIA_SUPPORT - #define BLOCK_AZALIA_SIZE sizeof (FCH_AZALIA) - #define InstallFchInitResetAzalia &FchTaskDummy - #define InstallFchInitEnvAzalia &FchInitEnvAzalia - #define InstallFchInitMidAzalia &FchInitMidAzalia - #define InstallFchInitLateAzalia &FchInitLateAzalia - #else - #define BLOCK_AZALIA_SIZE 0 - #define InstallFchInitResetAzalia &FchTaskDummy - #define InstallFchInitEnvAzalia &FchTaskDummy - #define InstallFchInitMidAzalia &FchTaskDummy - #define InstallFchInitLateAzalia &FchTaskDummy - #endif - - #ifndef FCH_NO_HWM_SUPPORT - #define BLOCK_HWM_SIZE sizeof (FCH_HWM) - #define InstallFchInitResetHwm &FchTaskDummy - #define InstallFchInitEnvHwm &FchInitEnvHwm - #define InstallFchInitMidHwm &FchInitMidHwm - #define InstallFchInitLateHwm &FchInitLateHwm - #else - #define InstallFchInitResetHwm &FchTaskDummy - #define InstallFchInitEnvHwm &FchTaskDummy - #define InstallFchInitMidHwm &FchTaskDummy - #define InstallFchInitLateHwm &FchTaskDummy - #endif - - - #define BLOCK_SMBUS_SIZE sizeof (FCH_SMBUS) - #define BLOCK_HPET_SIZE sizeof (FCH_HPET) - #define BLOCK_GCPU_SIZE sizeof (FCH_GCPU) - #define BLOCK_SDB_SIZE sizeof (FCH_SERIALDB) - #define BLOCK_MISC_SIZE sizeof (FCH_MISC) - - - // Optionally declare OEM hooks after each phase - #ifndef FCH_INIT_RESET_HOOK - #define InstallFchInitResetHook FchTaskDummy - #else - #define InstallFchInitResetHook OemFchInitResetHook - #endif - - - // - // Define FCH build time options and configurations - // - #ifdef BLDCFG_SMBUS0_BASE_ADDRESS - #define CFG_SMBUS0_BASE_ADDRESS BLDCFG_SMBUS0_BASE_ADDRESS - #else - #define CFG_SMBUS0_BASE_ADDRESS DFLT_SMBUS0_BASE_ADDRESS - #endif - - #ifdef BLDCFG_SMBUS1_BASE_ADDRESS - #define CFG_SMBUS1_BASE_ADDRESS BLDCFG_SMBUS1_BASE_ADDRESS - #else - #define CFG_SMBUS1_BASE_ADDRESS DFLT_SMBUS1_BASE_ADDRESS - #endif - - #ifdef BLDCFG_SIO_PME_BASE_ADDRESS - #define CFG_SIO_PME_BASE_ADDRESS BLDCFG_SIO_PME_BASE_ADDRESS - #else - #define CFG_SIO_PME_BASE_ADDRESS DFLT_SIO_PME_BASE_ADDRESS - #endif - - #ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS - #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS - #else - #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS - #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS - #else - #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS - #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS - #else - #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS DFLT_ACPI_PM_TMR_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS - #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS - #else - #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS - #define CFG_ACPI_GPE0_BLOCK_ADDRESS BLDCFG_ACPI_GPE0_BLOCK_ADDRESS - #else - #define CFG_ACPI_GPE0_BLOCK_ADDRESS DFLT_ACPI_GPE0_BLOCK_ADDRESS - #endif - - - #ifdef BLDCFG_WATCHDOG_TIMER_BASE - #define CFG_WATCHDOG_TIMER_BASE BLDCFG_WATCHDOG_TIMER_BASE - #else - #define CFG_WATCHDOG_TIMER_BASE DFLT_WATCHDOG_TIMER_BASE_ADDRESS - #endif - - #ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS - #define CFG_ACPI_PMA_CNTBLK_ADDRESS BLDCFG_ACPI_PMA_BLK_ADDRESS - #else - #define CFG_ACPI_PMA_CNTBLK_ADDRESS DFLT_ACPI_PMA_CNT_BLK_ADDRESS - #endif - - #ifdef BLDCFG_SMI_CMD_PORT_ADDRESS - #define CFG_SMI_CMD_PORT_ADDRESS BLDCFG_SMI_CMD_PORT_ADDRESS - #else - #define CFG_SMI_CMD_PORT_ADDRESS DFLT_SMI_CMD_PORT - #endif - - #ifdef BLDCFG_ROM_BASE_ADDRESS - #define CFG_SPI_ROM_BASE_ADDRESS BLDCFG_ROM_BASE_ADDRESS - #else - #define CFG_SPI_ROM_BASE_ADDRESS DFLT_SPI_BASE_ADDRESS - #endif - - #ifdef BLDCFG_GEC_SHADOW_ROM_BASE - #define CFG_GEC_SHADOW_ROM_BASE BLDCFG_GEC_SHADOW_ROM_BASE - #else - #define CFG_GEC_SHADOW_ROM_BASE DFLT_GEC_BASE_ADDRESS - #endif - - #ifdef BLDCFG_HPET_BASE_ADDRESS - #define CFG_HPET_BASE_ADDRESS BLDCFG_HPET_BASE_ADDRESS - #else - #define CFG_HPET_BASE_ADDRESS DFLT_HPET_BASE_ADDRESS - #endif - - #ifdef BLDCFG_AZALIA_SSID - #define CFG_AZALIA_SSID BLDCFG_AZALIA_SSID - #else - #define CFG_AZALIA_SSID DFLT_AZALIA_SSID - #endif - - #ifdef BLDCFG_SMBUS_SSID - #define CFG_SMBUS_SSID BLDCFG_SMBUS_SSID - #else - #define CFG_SMBUS_SSID DFLT_SMBUS_SSID - #endif - - #ifdef BLDCFG_IDE_SSID - #define CFG_IDE_SSID BLDCFG_IDE_SSID - #else - #define CFG_IDE_SSID DFLT_IDE_SSID - #endif - - #ifdef BLDCFG_SATA_AHCI_SSID - #define CFG_SATA_AHCI_SSID BLDCFG_SATA_AHCI_SSID - #else - #define CFG_SATA_AHCI_SSID DFLT_SATA_AHCI_SSID - #endif - - #ifdef BLDCFG_SATA_IDE_SSID - #define CFG_SATA_IDE_SSID BLDCFG_SATA_IDE_SSID - #else - #define CFG_SATA_IDE_SSID DFLT_SATA_IDE_SSID - #endif - - #ifdef BLDCFG_SATA_RAID5_SSID - #define CFG_SATA_RAID5_SSID BLDCFG_SATA_RAID5_SSID - #else - #define CFG_SATA_RAID5_SSID DFLT_SATA_RAID5_SSID - #endif - - #ifdef BLDCFG_SATA_RAID_SSID - #define CFG_SATA_RAID_SSID BLDCFG_SATA_RAID_SSID - #else - #define CFG_SATA_RAID_SSID DFLT_SATA_RAID_SSID - #endif - - #ifdef BLDCFG_EHCI_SSID - #define CFG_EHCI_SSID BLDCFG_EHCI_SSID - #else - #define CFG_EHCI_SSID DFLT_EHCI_SSID - #endif - - #ifdef BLDCFG_OHCI_SSID - #define CFG_OHCI_SSID BLDCFG_OHCI_SSID - #else - #define CFG_OHCI_SSID DFLT_OHCI_SSID - #endif - - #ifdef BLDCFG_LPC_SSID - #define CFG_LPC_SSID BLDCFG_LPC_SSID - #else - #define CFG_LPC_SSID DFLT_LPC_SSID - #endif - - #ifdef BLDCFG_FCH_GPP_LINK_CONFIG - #define CFG_FCH_GPP_LINK_CONFIG BLDCFG_FCH_GPP_LINK_CONFIG - #else - #define CFG_FCH_GPP_LINK_CONFIG DFLT_FCH_GPP_LINK_CONFIG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT0_PRESENT - #define CFG_FCH_GPP_PORT0_PRESENT BLDCFG_FCH_GPP_PORT0_PRESENT - #else - #define CFG_FCH_GPP_PORT0_PRESENT DFLT_FCH_GPP_PORT0_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT1_PRESENT - #define CFG_FCH_GPP_PORT1_PRESENT BLDCFG_FCH_GPP_PORT1_PRESENT - #else - #define CFG_FCH_GPP_PORT1_PRESENT DFLT_FCH_GPP_PORT1_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT2_PRESENT - #define CFG_FCH_GPP_PORT2_PRESENT BLDCFG_FCH_GPP_PORT2_PRESENT - #else - #define CFG_FCH_GPP_PORT2_PRESENT DFLT_FCH_GPP_PORT2_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT3_PRESENT - #define CFG_FCH_GPP_PORT3_PRESENT BLDCFG_FCH_GPP_PORT3_PRESENT - #else - #define CFG_FCH_GPP_PORT3_PRESENT DFLT_FCH_GPP_PORT3_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG - #define CFG_FCH_GPP_PORT0_HOTPLUG BLDCFG_FCH_GPP_PORT0_HOTPLUG - #else - #define CFG_FCH_GPP_PORT0_HOTPLUG DFLT_FCH_GPP_PORT0_HOTPLUG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG - #define CFG_FCH_GPP_PORT1_HOTPLUG BLDCFG_FCH_GPP_PORT1_HOTPLUG - #else - #define CFG_FCH_GPP_PORT1_HOTPLUG DFLT_FCH_GPP_PORT1_HOTPLUG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG - #define CFG_FCH_GPP_PORT2_HOTPLUG BLDCFG_FCH_GPP_PORT2_HOTPLUG - #else - #define CFG_FCH_GPP_PORT2_HOTPLUG DFLT_FCH_GPP_PORT2_HOTPLUG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG - #define CFG_FCH_GPP_PORT3_HOTPLUG BLDCFG_FCH_GPP_PORT3_HOTPLUG - #else - #define CFG_FCH_GPP_PORT3_HOTPLUG DFLT_FCH_GPP_PORT3_HOTPLUG - #endif - - - #ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - // - // Define task list for InitReset phase - // - FCH_TASK_ENTRY ROMDATA *FchInitResetTaskTable[] = { - InstallFchInitResetHwAcpiP, - InstallFchInitResetAb, - InstallFchInitResetSpi, - InstallFchInitResetGec, - InstallFchInitResetHwAcpi, - InstallFchInitResetSata, - InstallFchInitResetLpc, - InstallFchInitResetPcib, - InstallFchInitResetPcie, - InstallFchInitResetGpp, - InstallFchInitResetUsb, - InstallFchInitResetUsbEhci, - InstallFchInitResetUsbOhci, - InstallFchInitResetUsbXhci, - InstallFchInitResetImc, - NULL - }; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - // - // Define task list for InitEnv phase - // - FCH_TASK_ENTRY ROMDATA *FchInitEnvTaskTable[] = { - InstallFchInitEnvHwAcpiP, - InstallFchInitEnvPcib, - InstallFchInitEnvPcie, - InstallFchInitEnvIr, - InstallFchInitEnvHwAcpi, - InstallFchInitEnvSpi, - InstallFchInitEnvSd, - InstallFchInitEnvImc, - InstallFchInitEnvUsb, - InstallFchInitEnvUsbEhci, - InstallFchInitEnvUsbOhci, - InstallFchInitEnvUsbXhci, - InstallFchInitEnvSata, - InstallFchInitEnvIde, - InstallFchInitEnvGec, - InstallFchInitEnvAzalia, - InstallFchInitEnvAb, - InstallFchInitEnvGpp, - InstallFchInitEnvAbS, - InstallFchInitEnvHwm, - NULL - }; - #endif - #endif - - - #ifdef AGESA_ENTRY_INIT_MID - #if AGESA_ENTRY_INIT_MID == TRUE - // - // Define task list for InitMid phase - // - FCH_TASK_ENTRY ROMDATA *FchInitMidTaskTable[] = { - InstallFchInitMidImc, - InstallFchInitMidUsb, - InstallFchInitMidUsbEhci, - InstallFchInitMidUsbOhci, - InstallFchInitMidUsbXhci, - InstallFchInitMidSata, - InstallFchInitMidIde, - InstallFchInitMidGec, - InstallFchInitMidAzalia, - InstallFchInitMidHwm, - NULL - }; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - // - // Define task list for InitLate phase - // - FCH_TASK_ENTRY ROMDATA *FchInitLateTaskTable[] = { - InstallFchInitLatePcie, - InstallFchInitLatePcib, - InstallFchInitLateSpi, - InstallFchInitLateUsb, - InstallFchInitLateUsbEhci, - InstallFchInitLateUsbOhci, - InstallFchInitLateUsbXhci, - InstallFchInitLateSata, - InstallFchInitLateIde, - InstallFchInitLateGec, - InstallFchInitLateAzalia, - InstallFchInitLateImc, - InstallFchInitLateHwm, - InstallFchInitLateGpp, - InstallFchInitLateHwAcpi, - NULL - }; - #endif - #endif - - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - // - // Define task list for S3 resume before PCI phase - // - FCH_TASK_ENTRY ROMDATA *FchInitS3EarlyTaskTable[] = { - InstallFchInitEnvPcie, - InstallFchInitEnvPcib, - InstallFchInitEnvIr, - InstallFchInitEnvHwAcpi, - InstallFchInitEnvSpi, - InstallFchInitEnvSd, - InstallFchInitEnvUsb, - InstallFchInitEnvSata, - InstallFchInitEnvIde, - InstallFchInitEnvGec, - InstallFchInitEnvAzalia, - InstallFchInitEnvAb, - InstallFchInitEnvGpp, - InstallFchInitEnvAbS, - NULL - }; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - // - // Define task list for S3 resume after PCI phase - // - FCH_TASK_ENTRY ROMDATA *FchInitS3LateTaskTable[] = { - InstallFchInitLatePcie, - InstallFchInitLatePcib, - InstallFchInitLateSpi, - InstallFchInitLateUsb, - InstallFchInitLateUsbEhci, - InstallFchInitLateUsbOhci, - InstallFchInitLateUsbXhci, - InstallFchInitMidSata, - InstallFchInitMidIde, - InstallFchInitMidGec, - InstallFchInitMidAzalia, - InstallFchInitLateSata, - InstallFchInitLateIde, - InstallFchInitLateHwAcpi, - InstallFchInitEnvHwm, - InstallFchInitLateHwm, - NULL - }; - #endif - #endif - -#else // FCH_SUPPORT == FALSE - /* FCH Interface entries */ - extern FCH_INIT CommonFchInitStub; - - #define FP_FCH_INIT_RESET &CommonFchInitStub - #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub - #define FP_FCH_INIT_ENV &CommonFchInitStub - #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub - #define FP_FCH_INIT_MID &CommonFchInitStub - #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub - #define FP_FCH_INIT_LATE &CommonFchInitStub - #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub - - #define CFG_SMBUS0_BASE_ADDRESS 0 - #define CFG_SMBUS1_BASE_ADDRESS 0 - #define CFG_SIO_PME_BASE_ADDRESS 0 - #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0 - #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0 - #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS 0 - #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0 - #define CFG_ACPI_GPE0_BLOCK_ADDRESS 0 - #define CFG_SPI_ROM_BASE_ADDRESS 0 - #define CFG_WATCHDOG_TIMER_BASE 0 - #define CFG_HPET_BASE_ADDRESS 0 - #define CFG_SMI_CMD_PORT_ADDRESS 0 - #define CFG_ACPI_PMA_CNTBLK_ADDRESS 0 - #define CFG_GEC_SHADOW_ROM_BASE 0 - #define CFG_AZALIA_SSID 0 - #define CFG_SMBUS_SSID 0 - #define CFG_IDE_SSID 0 - #define CFG_SATA_AHCI_SSID 0 - #define CFG_SATA_IDE_SSID 0 - #define CFG_SATA_RAID5_SSID 0 - #define CFG_SATA_RAID_SSID 0 - #define CFG_EHCI_SSID 0 - #define CFG_OHCI_SSID 0 - #define CFG_LPC_SSID 0 - #define CFG_FCH_GPP_LINK_CONFIG 0 - #define CFG_FCH_GPP_PORT0_PRESENT 0 - #define CFG_FCH_GPP_PORT1_PRESENT 0 - #define CFG_FCH_GPP_PORT2_PRESENT 0 - #define CFG_FCH_GPP_PORT3_PRESENT 0 - #define CFG_FCH_GPP_PORT0_HOTPLUG 0 - #define CFG_FCH_GPP_PORT1_HOTPLUG 0 - #define CFG_FCH_GPP_PORT2_HOTPLUG 0 - #define CFG_FCH_GPP_PORT3_HOTPLUG 0 - -#endif - - -CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = { - FP_FCH_INIT_RESET, - FP_FCH_INIT_RESET_CONSTRUCT, - FP_FCH_INIT_ENV, - FP_FCH_INIT_ENV_CONSTRUCT, - FP_FCH_INIT_MID, - FP_FCH_INIT_MID_CONSTRUCT, - FP_FCH_INIT_LATE, - FP_FCH_INIT_LATE_CONSTRUCT, -}; - -#endif // _OPTION_FCH_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionGfxRecoveryInstall.h deleted file mode 100644 index c031f326c1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionGfxRecoveryInstall.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: GfxRecovery - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_ -#define _OPTION_GFX_RECOVERY_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - - -#endif // _OPTION_GFX_RECOVERY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionGnbInstall.h deleted file mode 100644 index bcd9700293..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionGnbInstall.h +++ /dev/null @@ -1,592 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: GNB - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 49877 $ @e \$Date: 2011-03-30 13:15:18 +0800 (Wed, 30 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_GNB_INSTALL_H_ -#define _OPTION_GNB_INSTALL_H_ - -#include "S3SaveState.h" -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -//--------------------------------------------------------------------------------------------------- -// Family installation -//--------------------------------------------------------------------------------------------------- - - -#define GNB_TYPE_KR FALSE -#define GNB_TYPE_TN FALSE -#define GNB_TYPE_LN FALSE -#define GNB_TYPE_ON FALSE - -#if (OPTION_FAMILY14H_ON == TRUE) - #undef GNB_TYPE_ON - #define GNB_TYPE_ON TRUE -#endif - -#if (OPTION_FAMILY12H_LN == TRUE) - #undef GNB_TYPE_LN - #define GNB_TYPE_LN TRUE -#endif - -#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) -//--------------------------------------------------------------------------------------------------- -// Service installation -//--------------------------------------------------------------------------------------------------- - - #include "Gnb.h" - #include "GnbPcie.h" - - #define SERVICES_POINTER NULL - GNB_SERVICE *ServiceTable = SERVICES_POINTER; - -//--------------------------------------------------------------------------------------------------- -// BUILD options -//--------------------------------------------------------------------------------------------------- - - #ifndef CFG_IGFX_AS_PCIE_EP - #define CFG_IGFX_AS_PCIE_EP TRUE - #endif - - #ifndef CFG_LCLK_DEEP_SLEEP_EN - #define CFG_LCLK_DEEP_SLEEP_EN TRUE - #endif - - #ifndef CFG_LCLK_DPM_EN - #define CFG_LCLK_DPM_EN TRUE - #endif - - #ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY - #define CFG_GMC_POWER_GATE_STUTTER_ONLY FALSE - #endif - - #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE - #if (GNB_TYPE_ON == TRUE) - #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE - #else - #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE - #endif - #endif - - #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE - #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE - #endif - - #ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT - #define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE - #endif - - #ifndef CFG_GNB_LOAD_REAL_FUSE - #define CFG_GNB_LOAD_REAL_FUSE TRUE - #endif - - #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING - #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) - #endif - - #ifndef CFG_GNB_PCIE_LINK_L0_POOLING - #define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000) - #endif - - #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME - #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) - #endif - - #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME - #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) - #endif - - #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM - #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM - #else - #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard - #endif - - #ifndef CFG_GNB_FORCE_CABLESAFE_OFF - #define CFG_GNB_FORCE_CABLESAFE_OFF FALSE - #endif - - #ifndef CFG_ORB_CLOCK_GATING_ENABLE - #define CFG_ORB_CLOCK_GATING_ENABLE TRUE - #endif - - #ifndef CFG_GNB_PCIE_POWERGATING_FLAGS - #define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0 - #endif - - #ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE - #define CFG_IOC_LCLK_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE - #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE - #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE - #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_GNB_ALTVDDNB_SUPPORT - #define CFG_GNB_ALTVDDNB_SUPPORT TRUE - #endif - - GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = { - CFG_IGFX_AS_PCIE_EP, - CFG_LCLK_DEEP_SLEEP_EN, - CFG_LCLK_DPM_EN, - CFG_GMC_POWER_GATE_STUTTER_ONLY, - CFG_SMU_SCLK_CLOCK_GATING_ENABLE, - CFG_PCIE_ASPM_BLACK_LIST_ENABLE, - CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT, - CFG_GNB_LOAD_REAL_FUSE, - CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING, - CFG_GNB_PCIE_LINK_L0_POOLING, - CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME, - CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME, - CFG_GNB_PCIE_TRAINING_ALGORITHM, - CFG_GNB_FORCE_CABLESAFE_OFF, - CFG_ORB_CLOCK_GATING_ENABLE, - CFG_GNB_PCIE_POWERGATING_FLAGS, - CFG_IOC_LCLK_CLOCK_GATING_ENABLE, - CFG_IOC_SCLK_CLOCK_GATING_ENABLE, - CFG_IOMMU_L1_CLOCK_GATING_ENABLE, - CFG_IOMMU_L2_CLOCK_GATING_ENABLE, - CFG_GNB_ALTVDDNB_SUPPORT - }; - - //--------------------------------------------------------------------------------------------------- - // Module entries - //--------------------------------------------------------------------------------------------------- - - #if (AGESA_ENTRY_INIT_EARLY == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_EARLY_INIT - #define OPTION_NB_EARLY_INIT TRUE - #endif - #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtEarly; - #define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly}, - #else - #define OPTION_NBINITATEARLY_ENTRY - #endif - #define OPTION_GNBEARLYINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - // SMU init - #ifndef OPTION_SMU - #define OPTION_SMU TRUE - #endif - #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE F12NbSmuInitFeature; - #define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature}, - #else - #define OPTION_F12NBSMUINITFEATURE_ENTRY - #endif - #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE F14NbSmuInitFeature; - #define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature}, - #else - #define OPTION_F14NBSMUINITFEATURE_ENTRY - #endif - #define OPTION_KRNBSMUINITFEATURE_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_CONFIG_INIT - #define OPTION_PCIE_CONFIG_INIT TRUE - #endif - #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieConfigurationInit; - #define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit}, - #else - #define OPTION_PCIECONFIGURATIONINIT_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_EARLY_INIT - #define OPTION_PCIE_EARLY_INIT TRUE - #endif - #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtEarly; - #define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly}, - #else - #define OPTION_PCIEINITATEARLY_ENTRY - #endif - #define OPTION_PCIEEARLYINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { - OPTION_NBINITATEARLY_ENTRY - OPTION_GNBEARLYINTERFACETN_ENTRY - OPTION_F12NBSMUINITFEATURE_ENTRY - OPTION_F14NBSMUINITFEATURE_ENTRY - OPTION_KRNBSMUINITFEATURE_ENTRY - OPTION_PCIECONFIGURATIONINIT_ENTRY - OPTION_PCIEINITATEARLY_ENTRY - OPTION_PCIEEARLYINTERFACETN_ENTRY - {0, NULL} - }; - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_EARLIER_INIT - #define OPTION_NB_EARLIER_INIT TRUE - #endif - #define OPTION_GNBEARLIERINTERFACETN_ENTRY - - OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = { - OPTION_GNBEARLIERINTERFACETN_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_POST == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_CONFIG_POST_INIT - #define OPTION_GFX_CONFIG_POST_INIT TRUE - #endif - #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxConfigPostInterface; - #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface}, - #else - #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_POST_INIT - #define OPTION_GFX_POST_INIT TRUE - #endif - #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxInitAtPost; - #define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost}, - #else - #define OPTION_GFXINITATPOST_ENTRY - #endif - #define OPTION_GFXPOSTINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_POST_INIT - #define OPTION_NB_POST_INIT TRUE - #endif - #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtPost; - #define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost}, - #else - #define OPTION_NBINITATPOST_ENTRY - #endif - #define OPTION_GNBPOSTINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_POST_EALRY_INIT - #define OPTION_PCIE_POST_EALRY_INIT TRUE - #endif - #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtPostEarly; - #define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly}, - #else - #define OPTION_PCIEINITATPOSTEARLY_ENTRY - #endif - #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_POST_INIT - #define OPTION_PCIE_POST_INIT TRUE - #endif - #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtPost; - #define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost}, - #else - #define OPTION_PCIEINITATPOST_ENTRY - #endif - #define OPTION_PCIEPOSTINTERFACETN_ENTRY - - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { - OPTION_PCIEINITATPOSTEARLY_ENTRY - OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY - OPTION_GFXCONFIGPOSTINTERFACE_ENTRY - OPTION_GFXINITATPOST_ENTRY - OPTION_GFXPOSTINTERFACETN_ENTRY - {0, NULL} - }; - - OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { - OPTION_NBINITATPOST_ENTRY - OPTION_GNBPOSTINTERFACETN_ENTRY - OPTION_PCIEINITATPOST_ENTRY - OPTION_PCIEPOSTINTERFACETN_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_ENV == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_FUSE_TABLE_INIT - #define OPTION_FUSE_TABLE_INIT TRUE - #endif - #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbFuseTableFeature; - #define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature}, - #else - #define OPTION_NBFUSETABLEFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_ENV_INIT - #define OPTION_NB_ENV_INIT TRUE - #endif - #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtEnv; - #define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv}, - #else - #define OPTION_NBINITATENVT_ENTRY - #endif - #define OPTION_GNBENVINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_CONFIG_ENV_INIT - #define OPTION_GFX_CONFIG_ENV_INIT TRUE - #endif - #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxConfigEnvInterface; - #define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface}, - #else - #define OPTION_GFXCONFIGENVINTERFACE_ENTRY - #endif - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_ENV_INIT - #define OPTION_GFX_ENV_INIT TRUE - #endif - #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxInitAtEnvPost; - #define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost}, - #else - #define OPTION_GFXINITATENVPOST_ENTRY - #endif - #define OPTION_GFXENVINTERFACETN_ENTRY - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_POWER_GATE - #define OPTION_POWER_GATE TRUE - #endif - #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE F12NbPowerGateFeature; - #define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature}, - #else - #define OPTION_F12NBPOWERGATEFEATURE_ENTRY - #endif - #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE F14NbPowerGateFeature; - #define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature}, - #else - #define OPTION_F14NBPOWERGATEFEATURE_ENTRY - #endif - #define OPTION_KRNBPOWERGATEFEATURE_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_ENV_INIT - #define OPTION_PCIE_ENV_INIT TRUE - #endif - #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtEnv; - #define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv}, - #else - #define OPTION_PCIEINITATENV_ENTRY - #endif - #define OPTION_PCIEENVINTERFACETN_ENTRY - - //--------------------------------------------------------------------------------------------------- - - OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = { - OPTION_NBFUSETABLEFEATURE_ENTRY - OPTION_NBINITATENVT_ENTRY - OPTION_GNBENVINTERFACETN_ENTRY - OPTION_PCIEINITATENV_ENTRY - OPTION_PCIEENVINTERFACETN_ENTRY - OPTION_GFXCONFIGENVINTERFACE_ENTRY - OPTION_GFXINITATENVPOST_ENTRY - OPTION_GFXENVINTERFACETN_ENTRY - OPTION_F12NBPOWERGATEFEATURE_ENTRY - OPTION_F14NBPOWERGATEFEATURE_ENTRY - OPTION_KRNBPOWERGATEFEATURE_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_MID == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTOIN_GNB_CABLESAFE - #define OPTOIN_GNB_CABLESAFE TRUE - #endif - #if (OPTOIN_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE GnbCableSafeEntry; - #define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry}, - #else - #define OPTION_GNBCABLESAFEENTRY_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTOIN_NB_LCLK_NCLK_RATIO - #define OPTOIN_NB_LCLK_NCLK_RATIO TRUE - #endif - #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature; - #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature}, - #else - #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY - #endif - #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_LCLK_DPM_INIT - #define OPTION_NB_LCLK_DPM_INIT TRUE - #endif - #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbLclkDpmFeature; - #define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature}, - #else - #define OPTION_NBLCLKDPMFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_POWER_GATE - #define OPTION_PCIE_POWER_GATE TRUE - #endif - #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE PciePowerGateFeature; - #define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature}, - #else - #define OPTION_PCIEPOWERGATEFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_MID_INIT - #define OPTION_GFX_MID_INIT TRUE - #endif - #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxInitAtMidPost; - #define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost}, - #else - #define OPTION_GFXINITATMIDPOST_ENTRY - #endif - #define OPTION_GFXMIDINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT - #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE - #endif - #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry; - #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry}, - #else - #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY - #endif - #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIe_MID_INIT - #define OPTION_PCIe_MID_INIT TRUE - #endif - #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtMid; - #define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid}, - #else - #define OPTION_PCIEINITATMID_ENTRY - #endif - #define OPTION_PCIEMIDINTERFACETN_ENTRY - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_MID_INIT - #define OPTION_NB_MID_INIT TRUE - #endif - #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtLatePost; - #define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost}, - #else - #define OPTION_NBINITATLATEPOST_ENTRY - #endif - #define OPTION_GNBMIDINTERFACETN_ENTRY - - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = { - OPTION_GFXINITATMIDPOST_ENTRY - OPTION_GFXMIDINTERFACETN_ENTRY - OPTION_GFXINTEGRATEDINFOTABLE_ENTRY - OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY - OPTION_GNBCABLESAFEENTRY_ENTRY - OPTION_PCIEINITATMID_ENTRY - OPTION_PCIEMIDINTERFACETN_ENTRY - OPTION_NBINITATLATEPOST_ENTRY - OPTION_GNBMIDINTERFACETN_ENTRY - OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY - OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY - OPTION_NBLCLKDPMFEATURE_ENTRY - OPTION_PCIEPOWERGATEFEATURE_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_LATE == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_ALIB - #define OPTION_ALIB FALSE - #endif - #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieAlibFeature; - #define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature}, - #else - #define OPTION_PCIEALIBFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_IOMMU_ACPI_IVRS - #define OPTION_IOMMU_ACPI_IVRS TRUE - #endif - #define OPTIONIOMMUACPIIVRSLATE_ENTRY - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = { - OPTION_PCIEALIBFEATURE_ENTRY - OPTIONIOMMUACPIIVRSLATE_ENTRY - {0, NULL} - }; - #endif - - #if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script; - S3_DISPATCH_FUNCTION PcieLateRestoreS3Script; - S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script; - #define GNB_S3_DISPATCH_FUNCTION_TABLE \ - {NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \ - {NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \ - {PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script}, - #endif - - -#endif -#endif // _OPTION_GNB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionHtInstall.h deleted file mode 100644 index eb4e44b5af..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionHtInstall.h +++ /dev/null @@ -1,304 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Ht - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_HT_INSTALL_H_ -#define _OPTION_HT_INSTALL_H_ - -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "htTopologies.h" -/* - * Advanced Option only, hardware socket naming is the preferred method. - */ -#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP - #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP) -#else - #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL) -#endif - -/* - * OPTION_IS_RECOVERY_HT is true if Basic API is being used. - */ -#ifndef OPTION_IS_RECOVERY_HT - #define OPTION_IS_RECOVERY_HT TRUE -#endif - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition. - */ - -#ifndef OPTION_MULTISOCKET - #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" -#endif - -/* - * Based on user level options, set Ht internal options. - * For now, Family 10h support will assume single module. For multi module, - * this will have to be changed to not set non-coherent only. - */ -#define OPTION_HT_NON_COHERENT_ONLY FALSE - -#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE)) -/* Fusion Families do not need a non-coherent only option. */ -#else - // Process Family 10h and 15h by socket, applying the MultiSocket option where it is allowable. - #if OPTION_G34_SOCKET_SUPPORT == FALSE - // Hydra has coherent support, other Family 10h should follow MultiSocket support. - #if OPTION_MULTISOCKET == FALSE - #undef OPTION_HT_NON_COHERENT_ONLY - #define OPTION_HT_NON_COHERENT_ONLY TRUE - #endif - #endif -#endif - -/* - * Macros will generate the correct item reference based on options - */ -#if AGESA_ENTRY_INIT_EARLY == TRUE - // Select the interface and features - #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE)) - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL - #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone - #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly - #else - // Family 10h and 15h Models 00h-0Fh - #if OPTION_HT_NON_COHERENT_ONLY == FALSE - #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault - #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault - #else - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL - #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly - #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly - #endif - #endif - // Select Northbridge components - #if OPTION_FAMILY10H == TRUE - #if OPTION_HT_NON_COHERENT_ONLY == TRUE - #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly, - #else - #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault, - #endif - #else - #define INTERNAL_HT_OPTION_FAM10_NB - #endif - #if OPTION_FAMILY12H == TRUE - #define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb, - #else - #define INTERNAL_HT_OPTION_FAM12_NB - #endif - #if OPTION_FAMILY14H == TRUE - #define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb, - #else - #define INTERNAL_HT_OPTION_FAM14_NB - #endif - #if OPTION_FAMILY15H == TRUE - #if OPTION_HT_NON_COHERENT_ONLY == TRUE - #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly, - #else - #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault, - #endif - #else - #define INTERNAL_HT_OPTION_FAM15_NB - #endif - - #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS, - #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS - #undef INTERNAL_ONLY_NB_LIST_ITEM - #define INTERNAL_ONLY_NB_LIST_ITEM - #endif - - /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item - * is ok to have a comma because the final item (NULL) is added below. - */ - #define INTERNAL_HT_OPTION_SUPPORTED_NBS \ - INTERNAL_ONLY_NB_LIST_ITEM \ - INTERNAL_HT_OPTION_FAM10_NB \ - INTERNAL_HT_OPTION_FAM15_NB \ - INTERNAL_HT_OPTION_FAM12_NB \ - INTERNAL_HT_OPTION_FAM14_NB - -#else - // Not Init Early - #define INTERNAL_HT_OPTION_FEATURES NULL - #define INTERNAL_HT_OPTION_INTERFACE NULL - #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL - #define HT_OPTIONS_PLATFORM NULL - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL -#endif - -#ifdef AGESA_ENTRY_INIT_EARLY - #if AGESA_ENTRY_INIT_EARLY == TRUE - - extern HT_FEATURES HtFeaturesDefault; - extern HT_FEATURES HtFeaturesNonCoherentOnly; - extern HT_FEATURES HtFeaturesNone; - extern HT_INTERFACE HtInterfaceDefault; - extern HT_INTERFACE HtInterfaceNonCoherentOnly; - extern HT_INTERFACE HtInterfaceMapsOnly; - extern HT_INTERFACE HtInterfaceNone; - extern NORTHBRIDGE HtFam10NbDefault; - extern NORTHBRIDGE HtFam10RevDNbDefault; - extern NORTHBRIDGE HtFam10NbNonCoherentOnly; - extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly; - extern NORTHBRIDGE HtFam12Nb; - extern NORTHBRIDGE HtFam14Nb; - extern NORTHBRIDGE HtFam10NbNone; - extern NORTHBRIDGE HtFam15NbDefault; - extern NORTHBRIDGE HtFam15NbNonCoherentOnly; - - CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = { - INTERNAL_HT_OPTION_SUPPORTED_NBS - NULL - }; - - STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform = - { - CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM, - (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST, - (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST, - (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST, - (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST, - (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST, - (IGNORE_LINK *)CFG_IGNORE_LINK_LIST, - (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST, - (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST, - (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP - }; - #ifndef HT_OPTIONS_PLATFORM - #define HT_OPTIONS_PLATFORM &HtOptionsPlatform - #endif - - /** - * A list of all the supported topologies. - * - */ - #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES - CONST UINT8 *CONST ROMDATA AmdTopolist[] = - { - amdHtTopologySingleNode, - amdHtTopologyDualNode, - amdHtTopologyThreeLine, - amdHtTopologyTriangle, - amdHtTopologyFourLine, - amdHtTopologyFourStar, - amdHtTopologyFourDegenerate, - amdHtTopologyFourSquare, - amdHtTopologyFourKite, - amdHtTopologyFourFully, - amdHtTopologyFiveFully, - amdHtTopologyFiveTwistedLadder, - amdHtTopologySixFully, - amdHtTopologySixDoubloonLower, - amdHtTopologySixDoubloonUpper, - amdHtTopologySixTwistedLadder, - amdHtTopologySevenFully, - amdHtTopologySevenTwistedLadder, - amdHtTopologyEightFully, - amdHtTopologyEightDoubloon, - amdHtTopologyEightTwistedLadder, - amdHtTopologyEightStraightLadder, - amdHtTopologySixTwinTriangles, - amdHtTopologyEightTwinFullyFourWays, - NULL - }; - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist - #endif - - /** - * Declare the instance of the Ht option configuration structure - */ - CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = { - OPTION_IS_RECOVERY_HT, - CFG_SET_HTCRC_SYNC_FLOOD, - CFG_USE_UNIT_ID_CLUMPING, - HT_OPTIONS_PLATFORM, - INTERNAL_HT_OPTION_INTERFACE, - INTERNAL_HT_OPTION_FEATURES, - &HtInstalledFamilyNorthbridgeList, - INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES - }; - - #endif -#endif - -#ifndef OPTION_HT_INIIT_RESET_ENTRY - - #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset - #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor - - #if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) - #undef OPTION_HT_INIIT_RESET_ENTRY - #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY - #define OPTION_HT_INIIT_RESET_ENTRY NULL - #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL - #endif - - #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE)) - #undef OPTION_HT_INIIT_RESET_ENTRY - #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY - #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset - #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor - #endif - -#endif - -#ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - - CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = { - (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST, - 0 // Unused by options - }; - - CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = { - OPTION_HT_INIIT_RESET_ENTRY, - OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY - }; - #endif - -#endif - -#endif // _OPTION_HT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionHwC1eInstall.h deleted file mode 100644 index e30f0488ff..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionHwC1eInstall.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: HW C1e - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_HW_C1E_INSTALL_H_ -#define _OPTION_HW_C1E_INSTALL_H_ - -#include "cpuHwC1e.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_HW_C1E_FEAT -#define F10_HW_C1E_SUPPORT -#if AGESA_ENTRY_INIT_EARLY == TRUE - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e; - #undef OPTION_HW_C1E_FEAT - #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e, - extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e; - #undef F10_HW_C1E_SUPPORT - #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e}, - #endif - #endif - #endif - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] = - { - F10_HW_C1E_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable = - { - (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &HwC1eFamilyServiceArray[0] - }; -#endif - -#endif // _OPTION_HW_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionIdsInstall.h deleted file mode 100644 index 4778de358d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionIdsInstall.h +++ /dev/null @@ -1,414 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * IDS Option Install File - * - * This file generates the defaults tables for family 10h model 5 processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 47940 $ @e \$Date: 2011-03-02 14:25:35 +0800 (Wed, 02 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -#ifndef _OPTION_IDS_INSTALL_H_ -#define _OPTION_IDS_INSTALL_H_ -#include "Ids.h" -#include "IdsHt.h" -#include "IdsLib.h" -#ifdef __IDS_EXTENDED__ - #include OPTION_IDS_EXT_INSTALL_FILE -#endif - -#define IDS_LATE_RUN_AP_TASK - -#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid -#if (IDSOPT_IDS_ENABLED == TRUE) - #if (IDSOPT_CONTROL_ENABLED == TRUE) - // Check for all families which include HT Features. - #if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE) - #undef M_HTIDS_PORT_OVERRIDE_HOOK - #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride - #endif - #endif -#endif // OPTION_IDS_LEVEL -CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK; - -#if (IDSOPT_IDS_ENABLED == TRUE) - #if (AGESA_ENTRY_INIT_LATE == TRUE) - #undef IDS_LATE_RUN_AP_TASK - #define IDS_LATE_RUN_AP_TASK - #endif -#endif // OPTION_IDS_LEVEL - -#if (IDSOPT_TRACING_ENABLED == TRUE) - #if (AGESA_ENTRY_INIT_POST == TRUE) - #include - CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, - { (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, - { (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} - }; - #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE) - #include - CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINTN) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"}, - { (UINTN) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"}, - { (UINTN) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"} - }; - #else - CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINTN) CommonReturnFalse, "DefRet()"}, - { (UINTN) CommonReturnFalse, "DefRet()"}, - { (UINTN) CommonReturnFalse, "DefRet()"} - }; - #endif -#endif - - -///Ids Feat Options -#if (IDSOPT_IDS_ENABLED == TRUE) - #if (IDSOPT_CONTROL_ENABLED == TRUE) - - #ifndef OPTION_IDS_EXTEND_FEATS - #define OPTION_IDS_EXTEND_FEATS - #endif - - #define OPTION_IDS_FEAT_ECCCTRL\ - OPTION_IDS_FEAT_ECCCTRL_F10 \ - OPTION_IDS_FEAT_ECCCTRL_F12 \ - OPTION_IDS_FEAT_ECCCTRL_F15_OR - - #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\ - OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \ - OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 - - #define OPTION_IDS_FEAT_CPB_CTRL\ - OPTION_IDS_FEAT_CPB_CTRL_F12 - - #define OPTION_IDS_FEAT_HTC_CTRL\ - OPTION_IDS_FEAT_HTC_CTRL_F15 - - #define OPTION_IDS_FEAT_MEMORY_MAPPING\ - OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \ - OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR - #define OPTION_IDS_FEAT_HT_ASSIST\ - OPTION_IDS_FEAT_HT_ASSIST_F10HY \ - OPTION_IDS_FEAT_HT_ASSIST_F15_OR - - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE\ - OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \ - OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR - -/*---------------------------------------------------------------------------- - * Family 10 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 - #define OPTION_IDS_FEAT_ECCCTRL_F10 - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE -//Ecc symbol size - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10; - #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10, - -//ECC scrub control - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10; - #undef OPTION_IDS_FEAT_ECCCTRL_F10 - #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10, - #endif - #endif - - //Misc Features - #define OPTION_IDS_FEAT_HT_ASSIST_F10HY - #ifdef OPTION_FAMILY10H_HY - #if OPTION_FAMILY10H_HY == TRUE - #undef OPTION_IDS_FEAT_HT_ASSIST_F10HY - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy; - - #define OPTION_IDS_FEAT_HT_ASSIST_F10HY \ - &IdsFeatHtAssistBlockPlatformCfgF10Hy, - #endif - #endif -/*---------------------------------------------------------------------------- - * Family 12 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 - #define OPTION_IDS_FEAT_ECCCTRL_F12 - #define OPTION_IDS_FEAT_CPB_CTRL_F12 - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12; - #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12, - - //ECC scrub control - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12; - #undef OPTION_IDS_FEAT_ECCCTRL_F12 - #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12, - - #undef OPTION_IDS_FEAT_CPB_CTRL_F12 - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12; - #define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12, - - #endif - #endif - -/*---------------------------------------------------------------------------- - * Family 14 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14; - #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14, - #endif - #endif - -/*---------------------------------------------------------------------------- - * Family 15 OR feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR - #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR - #define OPTION_IDS_FEAT_ECCCTRL_F15_OR - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR - #ifdef OPTION_FAMILY15H_OR - #if OPTION_FAMILY15H_OR == TRUE - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Or; - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15Or; - #undef OPTION_IDS_FEAT_HTC_CTRL_F15_OR - #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR\ - &IdsFeatHtcControlBlockF15Or,\ - &IdsFeatHtcControlLateBlockF15Or, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Or; - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Or; - #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR\ - &IdsFeatMemoryMappingPostBeforeBlockF15Or,\ - &IdsFeatMemoryMappingChIntlvBlockF15Or, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15Or; - #undef OPTION_IDS_FEAT_HT_ASSIST_F15_OR - #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR\ - &IdsFeatHtAssistBlockPlatformCfgF15Or, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15Or; - #undef OPTION_IDS_FEAT_ECCCTRL_F15_OR - #define OPTION_IDS_FEAT_ECCCTRL_F15_OR &IdsFeatEccCtrlBlockF15Or, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15Or; - #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR &IdsFeatEccSymbolSizeBlockF15Or, - - #endif - #endif - - - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock = - { - IDS_FEAT_UCODE_UPDATE, - IDS_ALL_CORES, - IDS_UCODE, - IDS_FAMILY_ALL, - IdsSubUCode - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock = - { - IDS_FEAT_POWER_POLICY, - IDS_ALL_CORES, - IDS_PLATFORMCFG_OVERRIDE, - IDS_FAMILY_ALL, - IdsSubPowerPolicyOverride - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock = - { - IDS_FEAT_TARGET_PSTATE, - IDS_BSP_ONLY, - IDS_INIT_LATE_AFTER, - IDS_FAMILY_ALL, - IdsSubTargetPstate - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock = - { - IDS_FEAT_POSTPSTATE, - IDS_ALL_CORES, - IDS_CPU_Early_Override, - IDS_FAMILY_ALL, - IdsSubPostPState - }; - - //Dram controller Features - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock = - { - IDS_FEAT_DCT_ALLMEMCLK, - IDS_BSP_ONLY, - IDS_ALL_MEMORY_CLOCK, - IDS_FAMILY_ALL, - IdsSubAllMemClkEn - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock = - { - IDS_FEAT_DCT_GANGMODE, - IDS_BSP_ONLY, - IDS_GANGING_MODE, - IDS_FAMILY_ALL, - IdsSubGangingMode - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock = - { - IDS_FEAT_DCT_BURSTLENGTH, - IDS_BSP_ONLY, - IDS_BURST_LENGTH32, - AMD_FAMILY_10, - IdsSubBurstLength32 - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock = - { - IDS_FEAT_DCT_POWERDOWN, - IDS_BSP_ONLY, - IDS_INIT_POST_BEFORE, - IDS_FAMILY_ALL, - IdsSubPowerDownCtrl - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock = - { - IDS_FEAT_DCT_DLLSHUTDOWN, - IDS_BSP_ONLY, - IDS_DLL_SHUT_DOWN, - IDS_FAMILY_ALL, - IdsSubDllShutDownSR - }; - - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock = - { - IDS_FEAT_DCT_POWERDOWN, - IDS_BSP_ONLY, - IDS_POWERDOWN_MODE, - IDS_FAMILY_ALL, - IdsSubPowerDownMode - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock = - { - IDS_FEAT_HDTOUT, - IDS_BSP_ONLY, - IDS_INIT_EARLY_BEFORE, - IDS_FAMILY_ALL, - IdsSubHdtOut - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock = - { - IDS_FEAT_HT_SETTING, - IDS_BSP_ONLY, - IDS_HT_CONTROL, - IDS_FAMILY_ALL, - IdsSubHtLinkControl - }; - - CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = - { - &IdsFeatUcodeBlock, - &IdsFeatPowerPolicyBlock, - - &IdsFeatTargetPstateBlock, - - &IdsFeatPostPstateBlock, - - OPTION_IDS_FEAT_ECCSYMBOLSIZE - - OPTION_IDS_FEAT_ECCCTRL - - &IdsFeatDctAllMemClkBlock, - - &IdsFeatDctGangModeBlock, - - &IdsFeatDctBurstLengthBlock, - - &IdsFeatDctPowerDownCtrlBlock, - - &IdsFeatDctPowerDownModeBlock, - - &IdsFeatDctPowerDownModeBlock, - - OPTION_IDS_FEAT_HT_ASSIST - - &IdsFeatHdtOutBlock, - - &IdsFeatHtSettingBlock, - - OPTION_IDS_FEAT_GNB_PLATFORMCFG - - OPTION_IDS_FEAT_CPB_CTRL - - OPTION_IDS_FEAT_HTC_CTRL - - OPTION_IDS_FEAT_MEMORY_MAPPING - - OPTION_IDS_EXTEND_FEATS - - NULL - }; - #else - CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = - { - NULL - }; - #endif//IDSOPT_CONTROL_ENABLED -#else - CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = - { - NULL - }; -#endif// IDSOPT_IDS_ENABLED - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionIoCstateInstall.h deleted file mode 100644 index 3402809b3f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionIoCstateInstall.h +++ /dev/null @@ -1,132 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: IO C-state - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_IO_CSTATE_INSTALL_H_ -#define _OPTION_IO_CSTATE_INSTALL_H_ - -#include "cpuIoCstate.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -#define OPTION_IO_CSTATE_FEAT -#define F10_IO_CSTATE_SUPPORT -#define F12_IO_CSTATE_SUPPORT -#define F14_IO_CSTATE_SUPPORT -#define F15_OR_IO_CSTATE_SUPPORT - -#if OPTION_IO_CSTATE == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_PH == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport; - #undef F10_IO_CSTATE_SUPPORT - #define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - #if OPTION_FAMILY12H_LN == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport; - #undef F12_IO_CSTATE_SUPPORT - #define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - #if OPTION_FAMILY14H_ON == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport; - #undef F14_IO_CSTATE_SUPPORT - #define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14, &F14IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport; - #undef F15_OR_IO_CSTATE_SUPPORT - #define F15_OR_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrIoCstateSupport}, - #endif - #endif - #endif - - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] = -{ - F10_IO_CSTATE_SUPPORT - F12_IO_CSTATE_SUPPORT - F14_IO_CSTATE_SUPPORT - F15_OR_IO_CSTATE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable = -{ - (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &IoCstateFamilyServiceArray[0] -}; - -#endif // _OPTION_IO_CSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h deleted file mode 100644 index 7f3ac0769f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h +++ /dev/null @@ -1,104 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: L3 Dependent Features - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_L3_FEATURES_INSTALL_H_ -#define _OPTION_L3_FEATURES_INSTALL_H_ - -#include "cpuL3Features.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_L3_FEAT -#define F10_L3_FEAT_SUPPORT -#define F15_L3_FEAT_SUPPORT -#define L3_FEAT_AP_DISABLE_CACHE -#define L3_FEAT_AP_ENABLE_CACHE - -#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE) - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_HY == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features; - #undef OPTION_L3_FEAT - #define OPTION_L3_FEAT &CpuL3Features, - extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features; - #undef F10_L3_FEAT_SUPPORT - #define F10_L3_FEAT_SUPPORT {AMD_FAMILY_10_HY, &F10L3Features}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features; - #undef OPTION_L3_FEAT - #define OPTION_L3_FEAT &CpuL3Features, - extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features; - #undef F15_L3_FEAT_SUPPORT - #define F15_L3_FEAT_SUPPORT {AMD_FAMILY_15, &F15OrL3Features}, - #endif - #endif - - #undef L3_FEAT_AP_DISABLE_CACHE - #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, - #undef L3_FEAT_AP_ENABLE_CACHE - #define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches}, - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] = -{ - F10_L3_FEAT_SUPPORT - F15_L3_FEAT_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable = -{ - (sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &L3FeatureFamilyServiceArray[0] -}; - -#endif // _OPTION_L3_FEATURES_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionLowPwrPstateInstall.h deleted file mode 100644 index 3f9a3def52..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionLowPwrPstateInstall.h +++ /dev/null @@ -1,86 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Low Power Pstate for PROCHOT_L Throttling. - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_ -#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_ - -#include "cpuLowPwrPstate.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT -#define F15_LOW_PWR_PSTATE_SUPPORT - -#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - // Family 15h - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate; - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate, - extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport; - #undef F15_LOW_PWR_PSTATE_SUPPORT - #define F15_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrLowPwrPstateSupport}, - #endif - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] = -{ - F15_LOW_PWR_PSTATE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable = -{ - (sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &LowPwrPstateFamilyServiceArray[0] -}; - -#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h deleted file mode 100644 index 0fd8232ead..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h +++ /dev/null @@ -1,4202 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Memory - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 49545 $ @e \$Date: 2011-03-25 05:58:58 +0800 (Fri, 25 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_MEMORY_INSTALL_H_ -#define _OPTION_MEMORY_INSTALL_H_ - -#ifndef RUN_BROKEN_AGESA_TESTS - #define RUN_BROKEN_AGESA_TESTS 0 -#endif - -/*------------------------------------------------------------------------------- - * This option file is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -/*---------------------------------------------------------------------------------- - * FEATURE BLOCK FUNCTIONS - * - * This section defines function names that depend upon options that are selected - * in the platform solution install file. - */ -BOOLEAN MemFDefRet ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return FALSE; -} - -BOOLEAN MemMDefRet ( - IN MEM_MAIN_DATA_BLOCK *MMPtr - ) -{ - return TRUE; -} - -BOOLEAN MemMDefRetFalse ( - IN MEM_MAIN_DATA_BLOCK *MMPtr - ) -{ - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for dimm identification translator - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in,out] NodeID - ID of current node to construct - * @return TRUE - This is the correct constructor for the targeted node. - * @return FALSE - This isn't the correct constructor for the targeted node. - */ -BOOLEAN MemNIdentifyDimmConstructorRetDef ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - return FALSE; -} -/*---------------------------------------------------------------------------------- - * TABLE FEATURE BLOCK FUNCTIONS - * - * This section defines function names that depend upon options that are selected - * in the platform solution install file. - */ -UINT8 MemFTableDefRet ( - IN OUT MEM_TABLE_ALIAS **MTPtr - ) -{ - return 0; -} -/*---------------------------------------------------------------------------------- - * FEATURE S3 BLOCK FUNCTIONS - * - * This section defines function names that depend upon options that are selected - * in the platform solution install file. - */ -BOOLEAN MemFS3DefConstructorRet ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - return TRUE; -} - -#if (OPTION_MEMCTLR_DR == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr; - #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr - #else - #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - #if (OPTION_MEMCTLR_Ni == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet - #endif - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA; - #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb; - #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh; - #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh - #else - #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef - #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef - #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_OR == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr; - #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr - #else - #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_HY == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy; - #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy - #else - #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_C32 == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32 - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32; - #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32 - #else - #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_LN == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockLN; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemS3ResumeConstructNBBlockLN - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorLN; - #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorLN - #else - #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_ON == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON; - #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON - #else - #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef - #endif -#endif - -/*---------------------------------------------------------------------------------- - * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS - * - *---------------------------------------------------------------------------------- -*/ -#define MEM_NB_SUPPORT_DR -#define MEM_NB_SUPPORT_RB -#define MEM_NB_SUPPORT_DA -#define MEM_NB_SUPPORT_Ni -#define MEM_NB_SUPPORT_PH -#define MEM_NB_SUPPORT_HY -#define MEM_NB_SUPPORT_LN -#define MEM_NB_SUPPORT_OR -#define MEM_NB_SUPPORT_C32 -#define MEM_NB_SUPPORT_ON -#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 } - -#if (AGESA_ENTRY_INIT_POST == TRUE) - /*---------------------------------------------------------------------------------- - * FLOW CONTROL FUNCTION - * - * This section selects the function that controls the memory initialization sequence - * based upon the number of processor families that the BIOS will support. - */ - - extern MEM_FLOW_CFG MemMFlowDef; - #if (OPTION_MEMCTLR_DR == TRUE) - extern MEM_FLOW_CFG MemMFlowDr; - #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - extern MEM_FLOW_CFG MemMFlowDA; - #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - extern MEM_FLOW_CFG MemMFlowHy; - #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_OR == TRUE) - extern MEM_FLOW_CFG MemMFlowOr; - #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_LN == TRUE) - extern MEM_FLOW_CFG MemMFlowLN; - #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - extern MEM_FLOW_CFG MemMFlowC32; - #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_ON == TRUE) - extern MEM_FLOW_CFG MemMFlowON; - #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_Ni == TRUE) - extern MEM_FLOW_CFG MemMFlowDA; - #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - extern MEM_FLOW_CFG MemMFlowRb; - #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - extern MEM_FLOW_CFG MemMFlowPh; - #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef, - #endif - - MEM_FLOW_CFG* memFlowControlInstalled[] = { - MEM_MAIN_FLOW_CONTROL_PTR_Dr - MEM_MAIN_FLOW_CONTROL_PTR_DA - MEM_MAIN_FLOW_CONTROL_PTR_RB - MEM_MAIN_FLOW_CONTROL_PTR_PH - MEM_MAIN_FLOW_CONTROL_PTR_Hy - MEM_MAIN_FLOW_CONTROL_PTR_OR - MEM_MAIN_FLOW_CONTROL_PTR_LN - MEM_MAIN_FLOW_CONTROL_PTR_C32 - MEM_MAIN_FLOW_CONTROL_PTR_ON - MEM_MAIN_FLOW_CONTROL_PTR_Ni - NULL - }; - - #if (OPTION_ONLINE_SPARE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare; - #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMOnlineSpare - extern OPTION_MEM_FEATURE_NB MemFOnlineSpare; - #define MEM_FEATURE_ONLINE_SPARE MemFOnlineSpare - #else - #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMDefRet - #define MEM_FEATURE_ONLINE_SPARE MemFDefRet - #endif - - #if (OPTION_MEM_RESTORE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMContextSave; - extern OPTION_MEM_FEATURE_MAIN MemMContextRestore; - #define MEM_MAIN_FEATURE_MEM_SAVE MemMContextSave - #define MEM_MAIN_FEATURE_MEM_RESTORE MemMContextRestore - #else - #define MEM_MAIN_FEATURE_MEM_SAVE MemMDefRet - #define MEM_MAIN_FEATURE_MEM_RESTORE MemMDefRetFalse - #endif - - #if (OPTION_BANK_INTERLEAVE == TRUE) - extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks; - #define MEM_FEATURE_BANK_INTERLEAVE MemFInterleaveBanks - extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks; - #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks - #else - #define MEM_FEATURE_BANK_INTERLEAVE MemFDefRet - #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet - #endif - - #if (OPTION_NODE_INTERLEAVE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes; - #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMInterleaveNodes - extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes; - extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes; - #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFCheckInterleaveNodes - #define MEM_FEATURE_NODE_INTERLEAVE MemFInterleaveNodes - #else - #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFDefRet - #define MEM_FEATURE_NODE_INTERLEAVE MemFDefRet - #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMDefRet - #endif - - #if (OPTION_DCT_INTERLEAVE == TRUE) - extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels; - #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFInterleaveChannels - #else - #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFDefRet - #endif - - #if (OPTION_ECC == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMEcc; - #define MEM_MAIN_FEATURE_ECC MemMEcc - extern OPTION_MEM_FEATURE_NB MemFCheckECC; - extern OPTION_MEM_FEATURE_NB MemFInitECC; - #define MEM_FEATURE_CK_ECC MemFCheckECC - #define MEM_FEATURE_ECC MemFInitECC - #define MEM_FEATURE_ECCX8 MemMDefRet - #else - #define MEM_MAIN_FEATURE_ECC MemMDefRet - #define MEM_FEATURE_CK_ECC MemFDefRet - #define MEM_FEATURE_ECC MemFDefRet - #define MEM_FEATURE_ECCX8 MemMDefRet - #endif - - extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr; - #define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr - - #if (OPTION_DMI == TRUE) - #if (OPTION_DDR3 == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3; - #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3 - #else - extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2; - #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2 - #endif - #else - #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet - #endif - - #if (OPTION_DDR3 == TRUE) - extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal; - extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3; - extern OPTION_MEM_FEATURE_NB MemFLvDdr3; - #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal - #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3 - #define MEM_FEATURE_LVDDR3 MemFLvDdr3 - #else - #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet - #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet - #define MEM_FEATURE_LVDDR3 MemFDefRet - #endif - - extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion; - #define MEM_FEATURE_REGION_INTERLEAVE MemFInterleaveRegion - - extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc; - #define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc - - extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #if (OPTION_PARALLEL_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining - #else - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - #endif - - #if (OPTION_DIMM_EXCLUDE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM; - #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMRASExcludeDIMM - extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM; - #define MEM_FEATURE_DIMM_EXCLUDE MemFRASExcludeDIMM - #else - #define MEM_FEATURE_DIMM_EXCLUDE MemFDefRet - #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMDefRet - #endif - - /*---------------------------------------------------------------------------------- - * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS - * - *---------------------------------------------------------------------------------- - */ - #if OPTION_DDR2 == TRUE - extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2; - #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2, - #if (OPTION_HW_DRAM_INIT == TRUE) - extern MEM_TECH_FEAT MemTDramInitHw; - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw - #else - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef - #endif - #if (OPTION_SW_DRAM_INIT == TRUE) - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef - #else - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef - #endif - #else - #define MEM_TECH_CONSTRUCTOR_DDR2 - #endif - #if OPTION_DDR3 == TRUE - extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3; - #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3, - #if (OPTION_HW_DRAM_INIT == TRUE) - extern MEM_TECH_FEAT MemTDramInitHw; - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw - #else - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef - #endif - #if (OPTION_SW_DRAM_INIT == TRUE) - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3 - #else - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef - #endif - #else - #define MEM_TECH_CONSTRUCTOR_DDR3 - #endif - - /*--------------------------------------------------------------------------------------------------- - * FEATURE BLOCKS - * - * This section instantiates a feature block structure for each memory controller installed - * by the platform solution install file. - *--------------------------------------------------------------------------------------------------- - */ - - /*--------------------------------------------------------------------------------------------------- - * DEERHOUND FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DR == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockDr = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MemFDefRet, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_DR - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR; - extern MEM_INITIALIZER MemNInitDefaultsDR; - - - #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, - #endif // OPTION_MEMCTRL_DR - - /*--------------------------------------------------------------------------------------------------- - * DASHOUND FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - #if (OPTION_MEMCTLR_Ni == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockNi = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_Ni - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi; - extern MEM_INITIALIZER MemNInitDefaultsNi; - - #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA }, - #endif - - #if (OPTION_MEMCTLR_PH == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockPh = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_PH - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh; - extern MEM_INITIALIZER MemNInitDefaultsPh; - - #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, - #endif - - #if (OPTION_MEMCTLR_RB == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockRb = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_RB - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb; - extern MEM_INITIALIZER MemNInitDefaultsRb; - - #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, - #endif - - #if (OPTION_MEMCTLR_DA == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockDA = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_DA - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA; - extern MEM_INITIALIZER MemNInitDefaultsDA; - - #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, - #endif - #endif // OPTION_MEMCTRL_DA - - /*--------------------------------------------------------------------------------------------------- - * HYDRA FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_HY == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockHy = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MemFDefRet, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_HY - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY; - extern MEM_INITIALIZER MemNInitDefaultsHY; - #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, - #endif // OPTION_MEMCTRL_HY - /*--------------------------------------------------------------------------------------------------- - * LLANO FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_LN == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #if (OPTION_EARLY_SAMPLES == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportLN; - #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportLN - #else - #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet - #endif - - #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb; - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb - #else - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - #endif - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockLn = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MemFDefRet, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MEM_EARLY_SAMPLE_SUPPORT, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - #undef MEM_NB_SUPPORT_LN - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockLN; - extern MEM_INITIALIZER MemNInitDefaultsLN; - #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockLN, MemNInitDefaultsLN, &MemFeatBlockLn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN }, - - #endif // OPTION_MEMCTRL_LN - - /*--------------------------------------------------------------------------------------------------- - * ONTARIO FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_ON == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb; - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb - #else - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - #endif - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - #if (OPTION_EARLY_SAMPLES == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON; - #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportON - #else - #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet - #endif - - MEM_FEAT_BLOCK_NB MemFeatBlockOn = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MemFDefRet, - MemFDefRet, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MEM_EARLY_SAMPLE_SUPPORT, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_ON - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON; - extern MEM_INITIALIZER MemNInitDefaultsON; - #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, - - #endif // OPTION_MEMCTRL_ON - - /*--------------------------------------------------------------------------------------------------- - * OROCHI FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_OR == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_MAIN_FEATURE_LVDDR3 - extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre; - #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #if (OPTION_G34_SOCKET_SUPPORT || OPTION_C32_SOCKET_SUPPORT) - #undef MEM_FEATURE_REGION_INTERLEAVE - #define MEM_FEATURE_REGION_INTERLEAVE MemFDefRet - #endif - - #if (OPTION_EARLY_SAMPLES == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr; - #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportOr - #else - #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet - #endif - - #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb; - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemNInitCPGUnb - #else - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - #endif - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockOr = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MEM_EARLY_SAMPLE_SUPPORT, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_OR - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR; - extern MEM_INITIALIZER MemNInitDefaultsOR; - #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, - #endif // OPTION_MEMCTRL_OR - - /*--------------------------------------------------------------------------------------------------- - * C32 FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_C32 == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockC32 = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MemFDefRet, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_C32 - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32; - extern MEM_INITIALIZER MemNInitDefaultsC32; - #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, - #endif // OPTION_MEMCTRL_C32 - - /*--------------------------------------------------------------------------------------------------- - * MAIN FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - MEM_FEAT_BLOCK_MAIN MemFeatMain = { - MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION, - MEM_MAIN_FEATURE_TRAINING, - MEM_MAIN_FEATURE_DIMM_EXCLUDE, - MEM_MAIN_FEATURE_ONLINE_SPARE, - MEM_MAIN_FEATURE_NODE_INTERLEAVE, - MEM_MAIN_FEATURE_ECC, - MEM_MAIN_FEATURE_MEM_CLEAR, - MEM_MAIN_FEATURE_MEM_DMI, - MEM_MAIN_FEATURE_LVDDR3, - MEM_MAIN_FEATURE_UMAALLOC, - MEM_MAIN_FEATURE_MEM_SAVE, - MEM_MAIN_FEATURE_MEM_RESTORE - }; - - - /*--------------------------------------------------------------------------------------------------- - * Technology Training SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0 - #if OPTION_MEMCTLR_DR - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Dr = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr }, - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Dr = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB) - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2DA = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2PH = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Rb = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Ni = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #if (OPTION_MEMCTLR_DA) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_PH) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_RB) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if (OPTION_MEMCTLR_Ni) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3DA = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ph = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Rb = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ni = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #if (OPTION_MEMCTLR_DA) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_PH) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_RB) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_Ni) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if OPTION_MEMCTLR_HY - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy; - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Hy = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy }, - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Hy = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if OPTION_MEMCTLR_C32 - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32; - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2C32 = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 }, - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3C32 = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - - #if OPTION_MEMCTLR_LN - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceLN; - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3 - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3LN = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceLN, &memTechTrainingFeatSequenceDDR3LN }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - - #if OPTION_MEMCTLR_OR - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr; - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3OR = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - - #if OPTION_MEMCTLR_ON - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON; - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3 - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3ON = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 } - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB - MEM_TECH_ENABLE_TRAINING_SEQUENCE_END - }; - - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB - MEM_TECH_ENABLE_TRAINING_SEQUENCE_END - }; - /*--------------------------------------------------------------------------------------------------- - * NB TRAINING FLOW CONTROL - * - * - *--------------------------------------------------------------------------------------------------- - */ - OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NB_TRAIN_FLOW_DDR2, - NB_TRAIN_FLOW_DDR3, - }; - /*--------------------------------------------------------------------------------------------------- - * TECHNOLOGY BLOCK - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed - MEM_TECH_CONSTRUCTOR_DDR2 - MEM_TECH_CONSTRUCTOR_DDR3 - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if OPTION_MEMCTLR_HY - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUHy3, - #else - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsRHy3, - #else - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsSHy3, - #else - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { - PLAT_SP_HY_FF_UDIMM2 - PLAT_SP_HY_FF_RDIMM2 - PLAT_SP_HY_FF_SDIMM2 - PLAT_SP_HY_FF_UDIMM3 - PLAT_SP_HY_FF_RDIMM3 - PLAT_SP_HY_FF_SDIMM3 - }; - - #if OPTION_MEMCTLR_DR - #if OPTION_UDIMMS - #if OPTION_DDR2 - extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2; - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDr2, - #else - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDr3, - #else - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2; - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsRDr2, - #else - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsRDr3, - #else - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsSDr3, - #else - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = { - PLAT_SP_DR_FF_UDIMM2 - PLAT_SP_DR_FF_RDIMM2 - PLAT_SP_DR_FF_SDIMM2 - PLAT_SP_DR_FF_UDIMM3 - PLAT_SP_DR_FF_RDIMM3 - PLAT_SP_DR_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_DA == TRUE) - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDA3, - #else - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #else - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsSDA2, - #else - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsSDA3, - #else - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { - PLAT_SP_DA_FF_UDIMM2 - PLAT_SP_DA_FF_RDIMM2 - PLAT_SP_DA_FF_SDIMM2 - PLAT_SP_DA_FF_UDIMM3 - PLAT_SP_DA_FF_RDIMM3 - PLAT_SP_DA_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_Ni == TRUE) - #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsSNi3, - #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUNi3, - #else - #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { - PLAT_SP_NI_FF_UDIMM2 - PLAT_SP_NI_FF_RDIMM2 - PLAT_SP_NI_FF_SDIMM2 - PLAT_SP_NI_FF_UDIMM3 - PLAT_SP_NI_FF_RDIMM3 - PLAT_SP_NI_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_PH == TRUE) - #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsSPh3, - #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUPh3, - #else - #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { - PLAT_SP_PH_FF_UDIMM2 - PLAT_SP_PH_FF_RDIMM2 - PLAT_SP_PH_FF_SDIMM2 - PLAT_SP_PH_FF_UDIMM3 - PLAT_SP_PH_FF_RDIMM3 - PLAT_SP_PH_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_RB == TRUE) - #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsSRb3, - #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsURb3, - #else - #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { - PLAT_SP_RB_FF_UDIMM2 - PLAT_SP_RB_FF_RDIMM2 - PLAT_SP_RB_FF_SDIMM2 - PLAT_SP_RB_FF_UDIMM3 - PLAT_SP_RB_FF_RDIMM3 - PLAT_SP_RB_FF_SDIMM3 - }; - - #if OPTION_MEMCTLR_LN - #if OPTION_UDIMMS - #if OPTION_DDR3 - #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsULN3, - #else - #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR3 - #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsSLN3, - #else - #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[] = { - PLAT_SP_LN_FF_SDIMM3 - PLAT_SP_LN_FF_UDIMM3 - NULL - }; - - #if OPTION_MEMCTLR_C32 - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUC32_3, - #else - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsRC32_3, - #else - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { - PLAT_SP_C32_FF_UDIMM2 - PLAT_SP_C32_FF_RDIMM2 - PLAT_SP_C32_FF_SDIMM2 - PLAT_SP_C32_FF_UDIMM3 - PLAT_SP_C32_FF_RDIMM3 - PLAT_SP_C32_FF_SDIMM3 - }; - - #if OPTION_MEMCTLR_ON - #if OPTION_UDIMMS - #if OPTION_DDR3 - #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUON3, - #else - #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR3 - #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsSON3, - #else - #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = { - PLAT_SP_ON_FF_SDIMM3 - PLAT_SP_ON_FF_UDIMM3 - NULL - }; - - /*--------------------------------------------------------------------------------------------------- - * PLATFORM-SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - - #if OPTION_MEMCTLR_DR - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_DR_UDIMM_DDR2 //MemAGetPsCfgUDr2 - #else - #define PSC_DR_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DR_UDIMM_DDR3 MemAGetPsCfgUDr3, - #else - #define PSC_DR_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_DR_RDIMM_DDR2 MemAGetPsCfgRDr2, - #else - #define PSC_DR_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DR_RDIMM_DDR3 MemAGetPsCfgRDr3, - #else - #define PSC_DR_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_DR_SODIMM_DDR2 //MemAGetPsCfgSDr2 - #else - #define PSC_DR_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DR_SODIMM_DDR3 //MemAGetPsCfgSDr3 - #else - #define PSC_DR_SODIMM_DDR3 - #endif - #endif - #endif - - #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) - #if OPTION_MEMCTLR_Ni - #define PSC_NI_UDIMM_DDR2 - #define PSC_NI_UDIMM_DDR3 MemAGetPsCfgUNi3, - #define PSC_NI_RDIMM_DDR2 - #define PSC_NI_RDIMM_DDR3 - #define PSC_NI_SODIMM_DDR2 - #define PSC_NI_SODIMM_DDR3 MemAGetPsCfgSNi3, - #endif - #if OPTION_MEMCTLR_PH - #define PSC_PH_UDIMM_DDR2 - #define PSC_PH_UDIMM_DDR3 MemAGetPsCfgUPh3, - #define PSC_PH_RDIMM_DDR2 - #define PSC_PH_RDIMM_DDR3 - #define PSC_PH_SODIMM_DDR2 - #define PSC_PH_SODIMM_DDR3 MemAGetPsCfgSPh3, - #endif - #if OPTION_MEMCTLR_RB - #define PSC_RB_UDIMM_DDR2 - #define PSC_RB_UDIMM_DDR3 MemAGetPsCfgURb3, - #define PSC_RB_RDIMM_DDR2 - #define PSC_RB_RDIMM_DDR3 - #define PSC_RB_SODIMM_DDR2 - #define PSC_RB_SODIMM_DDR3 MemAGetPsCfgSRb3, - #endif - #if OPTION_MEMCTLR_DA - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_DA_UDIMM_DDR2 //MemAGetPsCfgUDr2 - #else - #define PSC_DA_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DA_UDIMM_DDR3 MemAGetPsCfgUDA3, - #else - #define PSC_DA_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_DA_RDIMM_DDR2 - #else - #define PSC_DA_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DA_RDIMM_DDR3 - #else - #define PSC_DA_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_DA_SODIMM_DDR2 MemAGetPsCfgSDA2, - #else - #define PSC_DA_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DA_SODIMM_DDR3 MemAGetPsCfgSDA3, - #else - #define PSC_DA_SODIMM_DDR3 - #endif - #endif - #endif - #endif - - #if OPTION_MEMCTLR_HY - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_HY_UDIMM_DDR2 //MemAGetPsCfgUDr2, - #else - #define PSC_HY_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_HY_UDIMM_DDR3 MemAGetPsCfgUHy3, - #else - #define PSC_HY_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_HY_RDIMM_DDR2 - #else - #define PSC_HY_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_HY_RDIMM_DDR3 MemAGetPsCfgRHy3, - #else - #define PSC_HY_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_HY_SODIMM_DDR2 //MemAGetPsCfgSHy2, - #else - #define PSC_HY_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_HY_SODIMM_DDR3 //MemAGetPsCfgSHy3, - #else - #define PSC_HY_SODIMM_DDR3 - #endif - #endif - #endif - - #if OPTION_MEMCTLR_C32 - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_C32_UDIMM_DDR2 //MemAGetPsCfgUDr2, - #else - #define PSC_C32_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_C32_UDIMM_DDR3 MemAGetPsCfgUC32_3, - #else - #define PSC_C32_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_C32_RDIMM_DDR2 - #else - #define PSC_C32_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_C32_RDIMM_DDR3 MemAGetPsCfgRC32_3, - #else - #define PSC_C32_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_C32_SODIMM_DDR2 //MemAGetPsCfgSC32_2, - #else - #define PSC_C32_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_C32_SODIMM_DDR3 //MemAGetPsCfgSC32_3, - #else - #define PSC_C32_SODIMM_DDR3 - #endif - #endif - #endif - - #if OPTION_MEMCTLR_LN - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_LN_UDIMM_DDR2 //MemAGetPsCfgULN2, - #else - #define PSC_LN_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_LN_UDIMM_DDR3 MemAGetPsCfgULN3, - #else - #define PSC_LN_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_LN_RDIMM_DDR2 - #else - #define PSC_LN_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_LN_RDIMM_DDR3 //MemAGetPsCfgRLN3, - #else - #define PSC_LN_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_LN_SODIMM_DDR2 //MemAGetPsCfgSLN2, - #else - #define PSC_LN_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_LN_SODIMM_DDR3 MemAGetPsCfgSLN3, - #else - #define PSC_LN_SODIMM_DDR3 - #endif - #endif - #endif - - #if OPTION_MEMCTLR_OR - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_OR_UDIMM_DDR2 //MemAGetPsCfgUOr2, - #else - #define PSC_OR_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_OR_UDIMM_DDR3 //MemAGetPsCfgUOr3, - #else - #define PSC_OR_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_OR_RDIMM_DDR2 - #else - #define PSC_OR_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_OR_RDIMM_DDR3 //MemAGetPsCfgROr3, - #else - #define PSC_OR_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_OR_SODIMM_DDR2 //MemAGetPsCfgSOr2, - #else - #define PSC_OR_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_OR_SODIMM_DDR3 //MemAGetPsCfgSOr3, - #else - #define PSC_OR_SODIMM_DDR3 - #endif - #endif - #endif - - #if OPTION_MEMCTLR_ON - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_ON_UDIMM_DDR2 //MemAGetPsCfgUON2, - #else - #define PSC_ON_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_ON_UDIMM_DDR3 MemAGetPsCfgUON3, - #else - #define PSC_ON_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_ON_RDIMM_DDR2 - #else - #define PSC_ON_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_ON_RDIMM_DDR3 //MemAGetPsCfgRON3, - #else - #define PSC_ON_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_ON_SODIMM_DDR2 //MemAGetPsCfgSON2, - #else - #define PSC_ON_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_ON_SODIMM_DDR3 MemAGetPsCfgSON3, - #else - #define PSC_ON_SODIMM_DDR3 - #endif - #endif - #endif - - /*---------------------------------------------------------------------- - * DEFAULT PSCFG DEFINITIONS - * - *---------------------------------------------------------------------- - */ - - #ifndef PSC_DR_UDIMM_DDR2 - #define PSC_DR_UDIMM_DDR2 - #endif - #ifndef PSC_DR_RDIMM_DDR2 - #define PSC_DR_RDIMM_DDR2 - #endif - #ifndef PSC_DR_SODIMM_DDR2 - #define PSC_DR_SODIMM_DDR2 - #endif - #ifndef PSC_DR_UDIMM_DDR3 - #define PSC_DR_UDIMM_DDR3 - #endif - #ifndef PSC_DR_RDIMM_DDR3 - #define PSC_DR_RDIMM_DDR3 - #endif - #ifndef PSC_DR_SODIMM_DDR3 - #define PSC_DR_SODIMM_DDR3 - #endif - #ifndef PSC_RB_UDIMM_DDR2 - #define PSC_RB_UDIMM_DDR2 - #endif - #ifndef PSC_RB_RDIMM_DDR2 - #define PSC_RB_RDIMM_DDR2 - #endif - #ifndef PSC_RB_SODIMM_DDR2 - #define PSC_RB_SODIMM_DDR2 - #endif - #ifndef PSC_RB_UDIMM_DDR3 - #define PSC_RB_UDIMM_DDR3 - #endif - #ifndef PSC_RB_RDIMM_DDR3 - #define PSC_RB_RDIMM_DDR3 - #endif - #ifndef PSC_RB_SODIMM_DDR3 - #define PSC_RB_SODIMM_DDR3 - #endif - #ifndef PSC_DA_UDIMM_DDR2 - #define PSC_DA_UDIMM_DDR2 - #endif - #ifndef PSC_DA_RDIMM_DDR2 - #define PSC_DA_RDIMM_DDR2 - #endif - #ifndef PSC_DA_SODIMM_DDR2 - #define PSC_DA_SODIMM_DDR2 - #endif - #ifndef PSC_DA_UDIMM_DDR3 - #define PSC_DA_UDIMM_DDR3 - #endif - #ifndef PSC_DA_RDIMM_DDR3 - #define PSC_DA_RDIMM_DDR3 - #endif - #ifndef PSC_DA_SODIMM_DDR3 - #define PSC_DA_SODIMM_DDR3 - #endif - #ifndef PSC_NI_UDIMM_DDR2 - #define PSC_NI_UDIMM_DDR2 - #endif - #ifndef PSC_NI_RDIMM_DDR2 - #define PSC_NI_RDIMM_DDR2 - #endif - #ifndef PSC_NI_SODIMM_DDR2 - #define PSC_NI_SODIMM_DDR2 - #endif - #ifndef PSC_NI_UDIMM_DDR3 - #define PSC_NI_UDIMM_DDR3 - #endif - #ifndef PSC_NI_RDIMM_DDR3 - #define PSC_NI_RDIMM_DDR3 - #endif - #ifndef PSC_NI_SODIMM_DDR3 - #define PSC_NI_SODIMM_DDR3 - #endif - #ifndef PSC_PH_UDIMM_DDR2 - #define PSC_PH_UDIMM_DDR2 - #endif - #ifndef PSC_PH_RDIMM_DDR2 - #define PSC_PH_RDIMM_DDR2 - #endif - #ifndef PSC_PH_SODIMM_DDR2 - #define PSC_PH_SODIMM_DDR2 - #endif - #ifndef PSC_PH_UDIMM_DDR3 - #define PSC_PH_UDIMM_DDR3 - #endif - #ifndef PSC_PH_RDIMM_DDR3 - #define PSC_PH_RDIMM_DDR3 - #endif - #ifndef PSC_PH_SODIMM_DDR3 - #define PSC_PH_SODIMM_DDR3 - #endif - #ifndef PSC_HY_UDIMM_DDR2 - #define PSC_HY_UDIMM_DDR2 - #endif - #ifndef PSC_HY_RDIMM_DDR2 - #define PSC_HY_RDIMM_DDR2 - #endif - #ifndef PSC_HY_SODIMM_DDR2 - #define PSC_HY_SODIMM_DDR2 - #endif - #ifndef PSC_HY_UDIMM_DDR3 - #define PSC_HY_UDIMM_DDR3 - #endif - #ifndef PSC_HY_RDIMM_DDR3 - #define PSC_HY_RDIMM_DDR3 - #endif - #ifndef PSC_HY_SODIMM_DDR3 - #define PSC_HY_SODIMM_DDR3 - #endif - #ifndef PSC_LN_UDIMM_DDR2 - #define PSC_LN_UDIMM_DDR2 - #endif - #ifndef PSC_LN_RDIMM_DDR2 - #define PSC_LN_RDIMM_DDR2 - #endif - #ifndef PSC_LN_SODIMM_DDR2 - #define PSC_LN_SODIMM_DDR2 - #endif - #ifndef PSC_LN_UDIMM_DDR3 - #define PSC_LN_UDIMM_DDR3 - #endif - #ifndef PSC_LN_RDIMM_DDR3 - #define PSC_LN_RDIMM_DDR3 - #endif - #ifndef PSC_LN_SODIMM_DDR3 - #define PSC_LN_SODIMM_DDR3 - #endif - #ifndef PSC_OR_UDIMM_DDR2 - #define PSC_OR_UDIMM_DDR2 - #endif - #ifndef PSC_OR_RDIMM_DDR2 - #define PSC_OR_RDIMM_DDR2 - #endif - #ifndef PSC_OR_SODIMM_DDR2 - #define PSC_OR_SODIMM_DDR2 - #endif - #ifndef PSC_OR_UDIMM_DDR3 - #define PSC_OR_UDIMM_DDR3 - #endif - #ifndef PSC_OR_RDIMM_DDR3 - #define PSC_OR_RDIMM_DDR3 - #endif - #ifndef PSC_OR_SODIMM_DDR3 - #define PSC_OR_SODIMM_DDR3 - #endif - #ifndef PSC_C32_UDIMM_DDR3 - #define PSC_C32_UDIMM_DDR3 - #endif - #ifndef PSC_C32_RDIMM_DDR3 - #define PSC_C32_RDIMM_DDR3 - #endif - #ifndef PSC_ON_UDIMM_DDR2 - #define PSC_ON_UDIMM_DDR2 - #endif - #ifndef PSC_ON_RDIMM_DDR2 - #define PSC_ON_RDIMM_DDR2 - #endif - #ifndef PSC_ON_SODIMM_DDR2 - #define PSC_ON_SODIMM_DDR2 - #endif - #ifndef PSC_ON_UDIMM_DDR3 - #define PSC_ON_UDIMM_DDR3 - #endif - #ifndef PSC_ON_RDIMM_DDR3 - #define PSC_ON_RDIMM_DDR3 - #endif - #ifndef PSC_ON_SODIMM_DDR3 - #define PSC_ON_SODIMM_DDR3 - #endif - - MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { - PSC_DR_UDIMM_DDR2 - PSC_DR_RDIMM_DDR2 - PSC_DR_SODIMM_DDR2 - PSC_DR_UDIMM_DDR3 - PSC_DR_RDIMM_DDR3 - PSC_DR_SODIMM_DDR3 - PSC_RB_UDIMM_DDR3 - PSC_RB_SODIMM_DDR3 - PSC_DA_SODIMM_DDR2 - PSC_DA_UDIMM_DDR3 - PSC_DA_SODIMM_DDR3 - PSC_NI_UDIMM_DDR3 - PSC_NI_SODIMM_DDR3 - PSC_PH_UDIMM_DDR3 - PSC_PH_SODIMM_DDR3 - PSC_HY_UDIMM_DDR3 - PSC_HY_RDIMM_DDR3 - PSC_HY_SODIMM_DDR3 - PSC_LN_UDIMM_DDR3 - PSC_LN_RDIMM_DDR3 - PSC_LN_SODIMM_DDR3 - PSC_OR_UDIMM_DDR3 - PSC_OR_RDIMM_DDR3 - PSC_OR_SODIMM_DDR3 - PSC_C32_UDIMM_DDR3 - PSC_C32_RDIMM_DDR3 - PSC_ON_UDIMM_DDR3 - PSC_ON_RDIMM_DDR3 - PSC_ON_SODIMM_DDR3 - NULL - }; - CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*)); -/* SIZE_OF_PLATFORM is not defined when the preprocessor runs - * Removing this test for coreboot. - */ -#if RUN_BROKEN_AGESA_TESTS - #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES - #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES - #endif -#endif - - /*--------------------------------------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #define MEM_PSC_FLOW_BLOCK_END NULL - #define PSC_TBL_END NULL - #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue - - #if OPTION_MEMCTLR_OR - #if OPTION_UDIMMS - #if OPTION_AM3_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 &MaxFreqTblEntUAM3, - extern PSC_TBL_ENTRY DramTermTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &DramTermTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &OdtPat1DTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &OdtPat2DTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &OdtPat3DTblEntUAM3, - extern PSC_TBL_ENTRY SAOTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_SAO_AM3 &SAOTblEntUAM3, - extern PSC_TBL_ENTRY ClkDisMapEntUAM3; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3, - #endif - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUC32; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 &MaxFreqTblEntUC32, - extern PSC_TBL_ENTRY DramTermTblEntUC32; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 &DramTermTblEntUC32, - extern PSC_TBL_ENTRY OdtPat1DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntUC32, - extern PSC_TBL_ENTRY OdtPat2DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntUC32, - extern PSC_TBL_ENTRY OdtPat3DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntUC32, - extern PSC_TBL_ENTRY SAOTblEntUC32; - #define PSC_TBL_OR_UDIMM3_SAO_C32 &SAOTblEntUC32, - extern PSC_TBL_ENTRY ClkDisMapEntUC32; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32, - extern PSC_TBL_ENTRY ClkDisMap3DEntUC32; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUG34; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 &MaxFreqTblEntUG34, - extern PSC_TBL_ENTRY DramTermTblEntUG34; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 &DramTermTblEntUG34, - extern PSC_TBL_ENTRY OdtPat1DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntUG34, - extern PSC_TBL_ENTRY OdtPat2DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntUG34, - extern PSC_TBL_ENTRY OdtPat3DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntUG34, - extern PSC_TBL_ENTRY SAOTblEntUG34; - #define PSC_TBL_OR_UDIMM3_SAO_G34 &SAOTblEntUG34, - extern PSC_TBL_ENTRY ClkDisMapEntUG34; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34, - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntRC32; - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 &MaxFreqTblEntRC32, - extern PSC_TBL_ENTRY DramTermTblEntRC32; - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 &DramTermTblEntRC32, - extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntRC32, - extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntRC32, - extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntRC32, - extern PSC_TBL_ENTRY SAOTblEntRC32; - #define PSC_TBL_OR_RDIMM3_SAO_C32 &SAOTblEntRC32, - extern PSC_TBL_ENTRY RC2IBTTblEntRC32; - #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 &RC2IBTTblEntRC32, - extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32; - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 &RC10OpSpdTblEntRC32, - extern PSC_TBL_ENTRY ClkDisMapEntRC32; - #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntRG34; - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 &MaxFreqTblEntRG34, - extern PSC_TBL_ENTRY DramTermTblEntRG34; - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 &DramTermTblEntRG34, - extern PSC_TBL_ENTRY OdtPat1DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntRG34, - extern PSC_TBL_ENTRY OdtPat2DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntRG34, - extern PSC_TBL_ENTRY OdtPat3DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntRG34, - extern PSC_TBL_ENTRY SAOTblEntRG34; - #define PSC_TBL_OR_RDIMM3_SAO_G34 &SAOTblEntRG34, - extern PSC_TBL_ENTRY RC2IBTTblEntRG34; - #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 &RC2IBTTblEntRG34, - extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34; - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 &RC10OpSpdTblEntRG34, - extern PSC_TBL_ENTRY ClkDisMapEntRG34; - #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34, - #endif - #endif - //#if OPTION_SODIMMS - //#endif - //#if OPTION_LRDIMMS - // #if OPTION_C32_SOCKET_SUPPORT - // extern PSC_TBL_ENTRY MaxFreqTblEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 &MaxFreqTblEntLRC32, - // extern PSC_TBL_ENTRY DramTermTblEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 &DramTermTblEntLRC32, - // extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntLRC32, - // extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntLRC32, - // extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntLRC32, - // extern PSC_TBL_ENTRY SAOTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_SAO_C32 &SAOTblEntLRC32, - // extern PSC_TBL_ENTRY IBTTblEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_IBT_C32 &IBTTblEntLRC32, - // extern PSC_TBL_ENTRY ClkDisMapEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32, - // #endif - // #if OPTION_G34_SOCKET_SUPPORT - // extern PSC_TBL_ENTRY MaxFreqTblEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 &MaxFreqTblEntLRG34, - // extern PSC_TBL_ENTRY DramTermTblEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 &DramTermTblEntLRG34, - // extern PSC_TBL_ENTRY OdtPat1DTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntLRG34, - // extern PSC_TBL_ENTRY OdtPat2DTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntLRG34, - // extern PSC_TBL_ENTRY OdtPat3DTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntLRG34, - // extern PSC_TBL_ENTRY SAOTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_SAO_G34 &SAOTblEntLRG34, - // extern PSC_TBL_ENTRY IBTTblEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_IBT_G34 &IBTTblEntLRG34, - // extern PSC_TBL_ENTRY ClkDisMapEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34, - // #endif - //#endif - extern PSC_TBL_ENTRY MR0WrTblEntry; - #define PSC_TBL_OR_MR0_WR &MR0WrTblEntry, - extern PSC_TBL_ENTRY MR0CLTblEntry; - #define PSC_TBL_OR_MR0_CL &MR0CLTblEntry, - extern PSC_TBL_ENTRY OrDdr3CKETriEnt; - #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt, - extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt; - #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt, - extern PSC_TBL_ENTRY OrDdr3ODTTriEnt; - #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt, - extern PSC_TBL_ENTRY OrUDdr3CSTriEnt; - #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt, - extern PSC_TBL_ENTRY OrDdr3CSTriEnt; - #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt, - extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt; - #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt, - extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt; - #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt, - - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3 - #define PSC_TBL_OR_UDIMM3_SAO_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_C32 - #define PSC_TBL_OR_UDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_G34 - #define PSC_TBL_OR_UDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3 - #define PSC_TBL_OR_RDIMM3_SAO_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_C32 - #define PSC_TBL_OR_RDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_G34 - #define PSC_TBL_OR_RDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32 - #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34 - #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32 - #define PSC_TBL_OR_LRDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34 - #define PSC_TBL_OR_LRDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32 - #define PSC_TBL_OR_LRDIMM3_IBT_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34 - #define PSC_TBL_OR_LRDIMM3_IBT_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - #endif - - PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = { - PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = { - PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = { - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = { - PSC_TBL_OR_UDIMM3_SAO_AM3 - PSC_TBL_OR_UDIMM3_SAO_C32 - PSC_TBL_OR_UDIMM3_SAO_G34 - PSC_TBL_OR_RDIMM3_SAO_AM3 - PSC_TBL_OR_RDIMM3_SAO_C32 - PSC_TBL_OR_RDIMM3_SAO_G34 - PSC_TBL_OR_LRDIMM3_SAO_C32 - PSC_TBL_OR_LRDIMM3_SAO_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = { - PSC_TBL_OR_MR0_WR - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = { - PSC_TBL_OR_MR0_CL - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = { - PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - PSC_TBL_OR_RDIMM3_RC2IBT_C32 - PSC_TBL_OR_RDIMM3_RC2IBT_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = { - PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = { - PSC_TBL_OR_LRDIMM3_IBT_C32 - PSC_TBL_OR_LRDIMM3_IBT_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = { - PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - PSC_TBL_OR_CKE_TRI - PSC_TBL_OR_ODT_TRI_3D - PSC_TBL_OR_ODT_TRI - PSC_TBL_OR_LRDIMM3_ODT_TRI_3D - PSC_TBL_OR_LRDIMM3_ODT_TRI - PSC_TBL_OR_UDIMM3_CS_TRI - PSC_TBL_OR_CS_TRI - PSC_TBL_END - }; - - MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = { - (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR, - NULL, - NULL, - (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR - }; - - extern MEM_PSC_FLOW MemPGetMaxFreqSupported; - #define PSC_FLOW_OR_MAX_FREQ MemPGetMaxFreqSupported - extern MEM_PSC_FLOW MemPGetRttNomWr; - #define PSC_FLOW_OR_DRAM_TERM MemPGetRttNomWr - extern MEM_PSC_FLOW MemPGetODTPattern; - #define PSC_FLOW_OR_ODT_PATTERN MemPGetODTPattern - extern MEM_PSC_FLOW MemPGetSAO; - #define PSC_FLOW_OR_SAO MemPGetSAO - extern MEM_PSC_FLOW MemPGetMR0WrCL; - #define PSC_FLOW_OR_MR0_WRCL MemPGetMR0WrCL - #if OPTION_RDIMMS - extern MEM_PSC_FLOW MemPGetRC2IBT; - #define PSC_FLOW_OR_RC2_IBT MemPGetRC2IBT - extern MEM_PSC_FLOW MemPGetRC10OpSpd; - #define PSC_FLOW_OR_RC10_OPSPD MemPGetRC10OpSpd - #endif - //#if OPTION_LRDIMMS - //extern MEM_PSC_FLOW MemPGetLRIBT; - //#define PSC_FLOW_OR_LR_IBT MemPGetLRIBT - //extern MEM_PSC_FLOW MemPGetLRNPR; - //#define PSC_FLOW_OR_LR_NPR MemPGetLRNPR - //extern MEM_PSC_FLOW MemPGetLRNLR; - //#define PSC_FLOW_OR_LR_NLR MemPGetLRNLR - //#endif - #ifndef PSC_FLOW_OR_MAX_FREQ - #define PSC_FLOW_OR_MAX_FREQ MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_DRAM_TERM - #define PSC_FLOW_OR_DRAM_TERM MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_ODT_PATTERN - #define PSC_FLOW_OR_ODT_PATTERN MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_SAO - #define PSC_FLOW_OR_SAO MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_MR0_WRCL - #define PSC_FLOW_OR_MR0_WRCL MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_RC2_IBT - #define PSC_FLOW_OR_RC2_IBT MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_RC10_OPSPD - #define PSC_FLOW_OR_RC10_OPSPD MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_IBT - #define PSC_FLOW_OR_LR_IBT MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_NPR - #define PSC_FLOW_OR_LR_NPR MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_NLR - #define PSC_FLOW_OR_LR_NLR MEM_PSC_FLOW_DEFTRUE - #endif - MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = { - &memPSCTblBlockOr, - PSC_FLOW_OR_MAX_FREQ, - PSC_FLOW_OR_DRAM_TERM, - PSC_FLOW_OR_ODT_PATTERN, - PSC_FLOW_OR_SAO, - PSC_FLOW_OR_MR0_WRCL, - PSC_FLOW_OR_RC2_IBT, - PSC_FLOW_OR_RC10_OPSPD, - PSC_FLOW_OR_LR_IBT, - PSC_FLOW_OR_LR_NPR, - PSC_FLOW_OR_LR_NLR - }; - #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR, - #else - #define MEM_PSC_FLOW_BLOCK_OR - #endif - - - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { - MEM_PSC_FLOW_BLOCK_OR - MEM_PSC_FLOW_BLOCK_END - }; - - /*--------------------------------------------------------------------------------------------------- - * - * LRDIMM CONTROL - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_LRDIMMS == TRUE) - #if (OPTION_MEMCTLR_OR == TRUE) - extern MEM_TECH_FEAT MemTLrdimmConstructor3; - #define MEM_TECH_FEATURE_LRDIMM_INIT &MemTLrdimmConstructor3 - #else //#if (OPTION_MEMCTLR_OR == FALSE) - #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef - #endif - #else //#if (OPTION_LRDIMMS == FALSE) - #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef - #endif - MEM_TECH_LRDIMM memLrdimmSupported = { - MEM_TECH_LRDIMM_STRUCT_VERSION, - MEM_TECH_FEATURE_LRDIMM_INIT - }; -#else - /*--------------------------------------------------------------------------------------------------- - * MAIN FLOW CONTROL - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_FLOW_CFG* memFlowControlInstalled[] = { - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * NB TRAINING FLOW CONTROL - * - * - *--------------------------------------------------------------------------------------------------- - */ - OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * DEFAULT TECHNOLOGY BLOCK - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed - NULL - }; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT TECHNOLOGY MAP - * - * - *--------------------------------------------------------------------------------------------------- - */ - UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT MAIN FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - MEM_FEAT_BLOCK_MAIN MemFeatMain = { - 0 - }; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT NORTHBRIDGE SUPPORT LIST - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DR == TRUE) - #undef MEM_NB_SUPPORT_DR - #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - #undef MEM_NB_SUPPORT_RB - #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - #undef MEM_NB_SUPPORT_DA - #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - #undef MEM_NB_SUPPORT_PH - #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - #undef MEM_NB_SUPPORT_HY - #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - #undef MEM_NB_SUPPORT_C32 - #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, - #endif - #if (OPTION_MEMCTLR_LN == TRUE) - #undef MEM_NB_SUPPORT_LN - #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN }, - #endif - #if (OPTION_MEMCTLR_ON == TRUE) - #undef MEM_NB_SUPPORT_ON - #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, - #endif - #if (OPTION_MEMCTLR_OR == TRUE) - #undef MEM_NB_SUPPORT_OR - #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, - #endif - /*--------------------------------------------------------------------------------------------------- - * DEFAULT Technology Training - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if OPTION_DDR2 - MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { - 0 - }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - { 0 } - }; - #endif - #if OPTION_DDR3 - MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { - 0 - }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - { 0 } - }; - #endif - /*--------------------------------------------------------------------------------------------------- - * DEFAULT Platform Specific list - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DR == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_Ni == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_LN == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_OR == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_ON == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { - NULL - }; - #endif - /*---------------------------------------------------------------------- - * DEFAULT PSCFG DEFINITIONS - * - *---------------------------------------------------------------------- - */ - MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { - NULL - }; - - /*---------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - *---------------------------------------------------------------------- - */ - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { - NULL - }; - - MEM_TECH_LRDIMM memLrdimmSupported = { - MEM_TECH_LRDIMM_STRUCT_VERSION, - NULL - }; -#endif - -/*--------------------------------------------------------------------------------------------------- - * NORTHBRIDGE SUPPORT LIST - * - * - *--------------------------------------------------------------------------------------------------- - */ -MEM_NB_SUPPORT memNBInstalled[] = { - MEM_NB_SUPPORT_RB - MEM_NB_SUPPORT_DA - MEM_NB_SUPPORT_Ni - MEM_NB_SUPPORT_PH - MEM_NB_SUPPORT_HY - MEM_NB_SUPPORT_LN - MEM_NB_SUPPORT_OR - MEM_NB_SUPPORT_C32 - MEM_NB_SUPPORT_ON - MEM_NB_SUPPORT_END -}; - -#endif // _OPTION_MEMORY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryRecoveryInstall.h deleted file mode 100644 index 6d2a445b53..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryRecoveryInstall.h +++ /dev/null @@ -1,599 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Memory - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 49896 $ @e \$Date: 2011-03-30 16:18:18 +0800 (Wed, 30 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_ -#define _OPTION_MEMORY_RECOVERY_INSTALL_H_ - -#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) - - #define MEM_REC_NB_SUPPORT_OR - - #if (OPTION_MEMCTLR_DR == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR; - #define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR, - #else - #define MEM_REC_NB_SUPPORT_DR - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockRb; - #define MEM_REC_NB_SUPPORT_RB MemRecConstructNBBlockRb, - #else - #define MEM_REC_NB_SUPPORT_RB - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA; - #define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA, - #else - #define MEM_REC_NB_SUPPORT_DA - #endif - #if (OPTION_MEMCTLR_NI == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockNi; - #define MEM_REC_NB_SUPPORT_NI MemRecConstructNBBlockNi, - #else - #define MEM_REC_NB_SUPPORT_NI - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockPh; - #define MEM_REC_NB_SUPPORT_PH MemRecConstructNBBlockPh, - #else - #define MEM_REC_NB_SUPPORT_PH - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY; - #define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY, - #else - #define MEM_REC_NB_SUPPORT_HY - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32; - #define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32, - #else - #define MEM_REC_NB_SUPPORT_C32 - #endif - #if (OPTION_MEMCTLR_LN == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN; - #define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN, - #else - #define MEM_REC_NB_SUPPORT_LN - #endif - #if (OPTION_MEMCTLR_ON == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON; - #define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON, - #else - #define MEM_REC_NB_SUPPORT_ON - #endif - - MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = { - MEM_REC_NB_SUPPORT_DR - MEM_REC_NB_SUPPORT_RB - MEM_REC_NB_SUPPORT_DA - MEM_REC_NB_SUPPORT_PH - MEM_REC_NB_SUPPORT_HY - MEM_REC_NB_SUPPORT_C32 - MEM_REC_NB_SUPPORT_LN - MEM_REC_NB_SUPPORT_OR - MEM_REC_NB_SUPPORT_ON - MEM_REC_NB_SUPPORT_NI - NULL - }; - - #define MEM_REC_TECH_CONSTRUCTOR_DDR2 - #if (OPTION_DDR3 == TRUE) - extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3; - #define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3, - #else - #define MEM_REC_TECH_CONSTRUCTOR_DDR3 - #endif - - MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { - MEM_REC_TECH_CONSTRUCTOR_DDR3 - MEM_REC_TECH_CONSTRUCTOR_DDR2 - NULL - }; - - #if OPTION_MEMCTLR_DR - #define PSC_REC_DR_UDIMM_DDR2 - #define PSC_REC_DR_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, - #define PSC_REC_DR_RDIMM_DDR2 - #define PSC_REC_DR_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, - #define PSC_REC_DR_SODIMM_DDR2 - #define PSC_REC_DR_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb, - #endif - #if ((OPTION_MEMCTLR_DA == TRUE) || (OPTION_MEMCTLR_Ni == TRUE) || (OPTION_MEMCTLR_PH == TRUE) || (OPTION_MEMCTLR_RB == TRUE)) - #define PSC_REC_DA_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, - #define PSC_REC_DA_SODIMM_DDR2 - #define PSC_REC_DA_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb, - #endif - #if OPTION_MEMCTLR_HY - #define PSC_REC_HY_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, - #define PSC_REC_HY_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, - #endif - #if OPTION_MEMCTLR_C32 - #define PSC_REC_C32_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, - #define PSC_REC_C32_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, - #endif - #if OPTION_MEMCTLR_OR - #define PSC_REC_OR_UDIMM_DDR3 //MemRecNGetPsCfgUDIMM3OR, - #define PSC_REC_OR_RDIMM_DDR3 //MemRecNGetPsCfgRDIMM3OR, - #endif - - #ifndef PSC_REC_DR_UDIMM_DDR2 - #define PSC_REC_DR_UDIMM_DDR2 - #endif - #ifndef PSC_REC_DR_UDIMM_DDR3 - #define PSC_REC_DR_UDIMM_DDR3 - #endif - #ifndef PSC_REC_DR_RDIMM_DDR2 - #define PSC_REC_DR_RDIMM_DDR2 - #endif - #ifndef PSC_REC_DR_RDIMM_DDR3 - #define PSC_REC_DR_RDIMM_DDR3 - #endif - #ifndef PSC_REC_DR_SODIMM_DDR2 - #define PSC_REC_DR_SODIMM_DDR2 - #endif - #ifndef PSC_REC_DR_SODIMM_DDR3 - #define PSC_REC_DR_SODIMM_DDR3 - #endif - #ifndef PSC_REC_DA_UDIMM_DDR3 - #define PSC_REC_DA_UDIMM_DDR3 - #endif - #ifndef PSC_REC_DA_SODIMM_DDR2 - #define PSC_REC_DA_SODIMM_DDR2 - #endif - #ifndef PSC_REC_DA_SODIMM_DDR3 - #define PSC_REC_DA_SODIMM_DDR3 - #endif - #ifndef PSC_REC_HY_UDIMM_DDR3 - #define PSC_REC_HY_UDIMM_DDR3 - #endif - #ifndef PSC_REC_HY_RDIMM_DDR3 - #define PSC_REC_HY_RDIMM_DDR3 - #endif - #ifndef PSC_REC_C32_UDIMM_DDR3 - #define PSC_REC_C32_UDIMM_DDR3 - #endif - #ifndef PSC_REC_C32_RDIMM_DDR3 - #define PSC_REC_C32_RDIMM_DDR3 - #endif - #ifndef PSC_REC_OR_UDIMM_DDR3 - #define PSC_REC_OR_UDIMM_DDR3 - #endif - #ifndef PSC_REC_OR_RDIMM_DDR3 - #define PSC_REC_OR_RDIMM_DDR3 - #endif - - MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = { - PSC_REC_DR_UDIMM_DDR2 - PSC_REC_DR_RDIMM_DDR2 - PSC_REC_DR_SODIMM_DDR2 - PSC_REC_DR_UDIMM_DDR3 - PSC_REC_DR_RDIMM_DDR3 - PSC_REC_DR_SODIMM_DDR3 - PSC_REC_DA_SODIMM_DDR2 - PSC_REC_DA_UDIMM_DDR3 - PSC_REC_DA_SODIMM_DDR3 - PSC_REC_HY_UDIMM_DDR3 - PSC_REC_HY_RDIMM_DDR3 - PSC_REC_C32_UDIMM_DDR3 - PSC_REC_C32_RDIMM_DDR3 - PSC_REC_OR_UDIMM_DDR3 - PSC_REC_OR_RDIMM_DDR3 - NULL - }; - - /*--------------------------------------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #define MEM_PSC_REC_FLOW_BLOCK_END NULL - #define PSC_REC_TBL_END NULL - #define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue - - #if OPTION_MEMCTLR_OR - #if OPTION_UDIMMS - #if OPTION_AM3_SOCKET_SUPPORT - extern PSC_TBL_ENTRY RecDramTermTblEntUAM3; - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &RecDramTermTblEntUAM3, - extern PSC_TBL_ENTRY RecOdtPat1DTblEntUAM3; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &RecOdtPat1DTblEntUAM3, - extern PSC_TBL_ENTRY RecOdtPat2DTblEntUAM3; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &RecOdtPat2DTblEntUAM3, - extern PSC_TBL_ENTRY RecOdtPat3DTblEntUAM3; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &RecOdtPat3DTblEntUAM3, - extern PSC_TBL_ENTRY RecSAOTblEntUAM3; - #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3 &RecSAOTblEntUAM3, - #endif - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY RecDramTermTblEntUC32; - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 &RecDramTermTblEntUC32, - extern PSC_TBL_ENTRY RecOdtPat1DTblEntUC32; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &RecOdtPat1DTblEntUC32, - extern PSC_TBL_ENTRY RecOdtPat2DTblEntUC32; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &RecOdtPat2DTblEntUC32, - extern PSC_TBL_ENTRY RecOdtPat3DTblEntUC32; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &RecOdtPat3DTblEntUC32, - extern PSC_TBL_ENTRY RecSAOTblEntUC32; - #define PSC_REC_TBL_OR_UDIMM3_SAO_C32 &RecSAOTblEntUC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY RecDramTermTblEntUG34; - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 &RecDramTermTblEntUG34, - extern PSC_TBL_ENTRY RecOdtPat1DTblEntUG34; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &RecOdtPat1DTblEntUG34, - extern PSC_TBL_ENTRY RecOdtPat2DTblEntUG34; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &RecOdtPat2DTblEntUG34, - extern PSC_TBL_ENTRY RecOdtPat3DTblEntUG34; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &RecOdtPat3DTblEntUG34, - extern PSC_TBL_ENTRY RecSAOTblEntUG34; - #define PSC_REC_TBL_OR_UDIMM3_SAO_G34 &RecSAOTblEntUG34, - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY RecDramTermTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 &RecDramTermTblEntRC32, - extern PSC_TBL_ENTRY RecOdtPat1DTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &RecOdtPat1DTblEntRC32, - extern PSC_TBL_ENTRY RecOdtPat2DTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &RecOdtPat2DTblEntRC32, - extern PSC_TBL_ENTRY RecOdtPat3DTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &RecOdtPat3DTblEntRC32, - extern PSC_TBL_ENTRY RecSAOTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_SAO_C32 &RecSAOTblEntRC32, - extern PSC_TBL_ENTRY RecRC2IBTTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 &RecRC2IBTTblEntRC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY RecDramTermTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 &RecDramTermTblEntRG34, - extern PSC_TBL_ENTRY RecOdtPat1DTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &RecOdtPat1DTblEntRG34, - extern PSC_TBL_ENTRY RecOdtPat2DTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &RecOdtPat2DTblEntRG34, - extern PSC_TBL_ENTRY RecOdtPat3DTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &RecOdtPat3DTblEntRG34, - extern PSC_TBL_ENTRY RecSAOTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_SAO_G34 &RecSAOTblEntRG34, - extern PSC_TBL_ENTRY RecRC2IBTTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 &RecRC2IBTTblEntRG34, - #endif - #endif - //#if OPTION_SODIMMS - //#endif - //#if OPTION_LRDIMMS - //#endif - extern PSC_TBL_ENTRY RecMR0WrTblEntry; - #define PSC_REC_TBL_OR_MR0_WR &RecMR0WrTblEntry, - extern PSC_TBL_ENTRY RecMR0CLTblEntry; - #define PSC_REC_TBL_OR_MR0_CL &RecMR0CLTblEntry, - - #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_AM3 - #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_C32 - #define PSC_REC_TBL_OR_UDIMM3_SAO_C32 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_G34 - #define PSC_REC_TBL_OR_UDIMM3_SAO_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_AM3 - #define PSC_REC_TBL_OR_RDIMM3_SAO_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_C32 - #define PSC_REC_TBL_OR_RDIMM3_SAO_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_G34 - #define PSC_REC_TBL_OR_RDIMM3_SAO_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3 - #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 - #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 - #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #endif - - PSC_TBL_ENTRY* memRecPSCTblDramTermArrayOR[] = { - PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 - PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 - PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 - PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 - PSC_REC_TBL_END - }; - - PSC_TBL_ENTRY* memRecPSCTblODTPatArrayOR[] = { - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - PSC_REC_TBL_END - }; - - PSC_TBL_ENTRY* memRecPSCTblSAOArrayOR[] = { - PSC_REC_TBL_OR_UDIMM3_SAO_AM3 - PSC_REC_TBL_OR_UDIMM3_SAO_C32 - PSC_REC_TBL_OR_UDIMM3_SAO_G34 - PSC_REC_TBL_OR_RDIMM3_SAO_AM3 - PSC_REC_TBL_OR_RDIMM3_SAO_C32 - PSC_REC_TBL_OR_RDIMM3_SAO_G34 - PSC_REC_TBL_END - }; - - PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayOR[] = { - PSC_REC_TBL_OR_MR0_WR - PSC_REC_TBL_END - }; - - PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayOR[] = { - PSC_REC_TBL_OR_MR0_CL - PSC_REC_TBL_END - }; - - PSC_TBL_ENTRY* memRecPSCTblRC2IBTArrayOR[] = { - PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3 - PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 - PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 - PSC_REC_TBL_END - }; - - MEM_PSC_TABLE_BLOCK memRecPSCTblBlockOr = { - NULL, - (PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayOR, - (PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayOR, - (PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayOR, - (PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayOR, - (PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayOR, - (PSC_TBL_ENTRY **)&memRecPSCTblRC2IBTArrayOR, - NULL, - NULL, - NULL, - NULL, - NULL - }; - - extern MEM_PSC_FLOW MemPRecGetRttNomWr; - #define PSC_REC_FLOW_OR_DRAM_TERM MemPRecGetRttNomWr - extern MEM_PSC_FLOW MemPRecGetODTPattern; - #define PSC_REC_FLOW_OR_ODT_PATTERN MemPRecGetODTPattern - extern MEM_PSC_FLOW MemPRecGetSAO; - #define PSC_REC_FLOW_OR_SAO MemPRecGetSAO - extern MEM_PSC_FLOW MemPRecGetMR0WrCL; - #define PSC_REC_FLOW_OR_MR0_WRCL MemPRecGetMR0WrCL - #if OPTION_RDIMMS - extern MEM_PSC_FLOW MemPRecGetRC2IBT; - #define PSC_REC_FLOW_OR_RC2_IBT MemPRecGetRC2IBT - #endif - //#if OPTION_LRDIMMS - extern MEM_PSC_FLOW MemPRecGetLRIBT; - #define PSC_REC_FLOW_OR_LR_IBT MemPRecGetLRIBT - extern MEM_PSC_FLOW MemPRecGetLRNPR; - #define PSC_REC_FLOW_OR_LR_NPR MemPRecGetLRNPR - extern MEM_PSC_FLOW MemPRecGetLRNLR; - #define PSC_REC_FLOW_OR_LR_NLR MemPRecGetLRNLR - //#endif - #ifndef PSC_REC_FLOW_OR_DRAM_TERM - #define PSC_REC_FLOW_OR_DRAM_TERM MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_ODT_PATTERN - #define PSC_REC_FLOW_OR_ODT_PATTERN MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_SAO - #define PSC_REC_FLOW_OR_SAO MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_MR0_WRCL - #define PSC_REC_FLOW_OR_MR0_WRCL MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_RC2_IBT - #define PSC_REC_FLOW_OR_RC2_IBT MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_LR_IBT - #define PSC_REC_FLOW_OR_LR_IBT MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_LR_NPR - #define PSC_REC_FLOW_OR_LR_NPR MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_LR_NLR - #define PSC_REC_FLOW_OR_LR_NLR MEM_REC_PSC_FLOW_DEFTRUE - #endif - MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowOR = { - &memRecPSCTblBlockOr, - NULL, - PSC_REC_FLOW_OR_DRAM_TERM, - PSC_REC_FLOW_OR_ODT_PATTERN, - PSC_REC_FLOW_OR_SAO, - PSC_REC_FLOW_OR_MR0_WRCL, - PSC_REC_FLOW_OR_RC2_IBT, - NULL, - PSC_REC_FLOW_OR_LR_IBT, - PSC_REC_FLOW_OR_LR_NPR, - PSC_REC_FLOW_OR_LR_NLR - }; - #define MEM_PSC_REC_FLOW_BLOCK_OR &memRecPlatSpecFlowOR, - #else - #define MEM_PSC_REC_FLOW_BLOCK_OR - #endif - - MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = { - MEM_PSC_REC_FLOW_BLOCK_OR - MEM_PSC_REC_FLOW_BLOCK_END - }; - -#else - /*--------------------------------------------------------------------------------------------------- - * DEFAULT TECHNOLOGY BLOCK - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { // Types of technology installed - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * DEFAULT NORTHBRIDGE SUPPORT LIST - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_NB_SUPPORT* MemRecNBInstalled[] = { - NULL - }; - /*---------------------------------------------------------------------- - * DEFAULT PSCFG DEFINITIONS - * - *---------------------------------------------------------------------- - */ - MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = { - NULL - }; - /*---------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - *---------------------------------------------------------------------- - */ - MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = { - NULL - }; -#endif -#endif // _OPTION_MEMORY_RECOVERY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMsgBasedC1eInstall.h deleted file mode 100644 index 7476e16358..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionMsgBasedC1eInstall.h +++ /dev/null @@ -1,116 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Message-Based C1e - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_ -#define _OPTION_MSG_BASED_C1E_INSTALL_H_ - -#include "cpuMsgBasedC1e.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_MSG_BASED_C1E_FEAT -#define F10_MSG_BASED_C1E_SUPPORT -#define F15_MSG_BASED_C1E_SUPPORT -#if OPTION_MSG_BASED_C1E == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) - - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_HY == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e; - #undef OPTION_MSG_BASED_C1E_FEAT - #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, - #endif - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e; - #undef OPTION_MSG_BASED_C1E_FEAT - #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_HY == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) - extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e; - #undef F10_MSG_BASED_C1E_SUPPORT - #define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e}, - #endif - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) - extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e; - #undef F15_MSG_BASED_C1E_SUPPORT - #define F15_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15, &F15OrMsgBasedC1e}, - #endif - #endif - #endif - - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] = - { - F10_MSG_BASED_C1E_SUPPORT - F15_MSG_BASED_C1E_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable = - { - (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &MsgBasedC1eFamilyServiceArray[0] - }; - #endif -#endif -#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMultiSocketInstall.h deleted file mode 100644 index 3c87677fe9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionMultiSocketInstall.h +++ /dev/null @@ -1,94 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Multiple Socket Support - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_MULTISOCKET_INSTALL_H_ -#define _OPTION_MULTISOCKET_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#ifndef OPTION_MULTISOCKET - #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" -#endif - -#if OPTION_MULTISOCKET == TRUE - OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti; - #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti - OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti; - #define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti - OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti; - #define GET_SYS_NB_COF GetSystemNbCofMulti - OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti; - #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti - OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti; - #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti - OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti; - #define GET_MIN_NB_COF GetMinNbCofMulti -#else - OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle; - #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle - OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle; - #define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle - OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle; - #define GET_SYS_NB_COF GetSystemNbCofSingle - OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle; - #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle - OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle; - #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle - OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle; - #define GET_MIN_NB_COF GetMinNbCofSingle -#endif - -/* Declare the instance of the DMI option configuration structure */ -OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = { - MULTISOCKET_STRUCT_VERSION, - GET_NUM_PM_STEPS, - CORE0_PM_TASK, - GET_SYS_NB_COF, - GET_SYS_NB_COF_UPDATE, - GET_EARLY_PM_ERRORS, - GET_MIN_NB_COF -}; - -#endif // _OPTION_MULTISOCKET_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionPreserveMailboxInstall.h deleted file mode 100644 index 10ea6a74b1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionPreserveMailboxInstall.h +++ /dev/null @@ -1,122 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Preserve Mailbox - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 50096 $ @e \$Date: 2011-04-02 06:17:10 +0800 (Sat, 02 Apr 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_ -#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_ - -#include "PreserveMailbox.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_PRESERVE_MAILBOX_FEAT -#define F10_PRESERVE_MAILBOX_SUPPORT -#define F15_PRESERVE_MAILBOX_SUPPORT - -#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) - #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE)) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox; - #undef OPTION_PRESERVE_MAILBOX_FEAT - #define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox, - #endif - #if OPTION_FAMILY10H == TRUE - CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F10PreserveMailboxRegisters [] = { - { - MAKE_SBDFO (0, 0, 0, 3, 0x168), - 0x00000FFF - }, - { - MAKE_SBDFO (0, 0, 0, 3, 0x170), - 0x00000FFF - }, - { - ILLEGAL_SBDFO, - 0 - } - }; - CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = { - 0, - TRUE, - (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F10PreserveMailboxRegisters - }; - #undef F10_PRESERVE_MAILBOX_SUPPORT - #define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices}, - #endif - #if OPTION_FAMILY15H == TRUE - CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F15PreserveMailboxRegisters [] = { - { - MAKE_SBDFO (0, 0, 0, 3, 0x168), - 0x00000FFF - }, - { - MAKE_SBDFO (0, 0, 0, 3, 0x170), - 0x00000FFF - }, - { - ILLEGAL_SBDFO, - 0 - } - }; - CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = { - 0, - TRUE, - (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F15PreserveMailboxRegisters - }; - #undef F15_PRESERVE_MAILBOX_SUPPORT - #define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices}, - #endif - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] = - { - F10_PRESERVE_MAILBOX_SUPPORT - F15_PRESERVE_MAILBOX_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable = - { - (sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &PreserveMailboxFamilyServiceArray[0] - }; -#endif - -#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h deleted file mode 100644 index 7d6433db31..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h +++ /dev/null @@ -1,254 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: PState - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_PSTATE_INSTALL_H_ -#define _OPTION_PSTATE_INSTALL_H_ - -#include "cpuPstateTables.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -#define F10_PSTATE_SERVICE_SUPPORT -#define F12_PSTATE_SERVICE_SUPPORT -#define F14_PSTATE_SERVICE_SUPPORT -#define F15_OR_PSTATE_SERVICE_SUPPORT -#define F15_TN_PSTATE_SERVICE_SUPPORT - - -#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) - // - //Define Pstate CPU Family service - // - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices; - #undef F10_PSTATE_SERVICE_SUPPORT - #define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices; - #undef F12_PSTATE_SERVICE_SUPPORT - #define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices; - #undef F14_PSTATE_SERVICE_SUPPORT - #define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #ifdef OPTION_FAMILY15H_OR - #if OPTION_FAMILY15H_OR == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices; - #undef F15_OR_PSTATE_SERVICE_SUPPORT - #define F15_OR_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_OR, &F15OrPstateServices}, - #endif - #endif - #ifdef OPTION_FAMILY15H_TN - #if OPTION_FAMILY15H_TN == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices; - #undef F15_TN_PSTATE_SERVICE_SUPPORT - #define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices}, - #endif - #endif - #endif - #endif - // - //Define ACPI Pstate objects. - // - #ifndef OPTION_ACPI_PSTATES - #error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES" - #endif - #if (OPTION_ACPI_PSTATES == TRUE) -// OPTION_SSDT_FEATURE GenerateSsdt; - #define USER_SSDT_MAIN GenerateSsdt - #ifndef OPTION_MULTISOCKET - #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" - #endif - -// OPTION_ACPI_FEATURE CreatePStateAcpiTables; - OPTION_PSTATE_GATHER PStateGatherMain; - #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)) - OPTION_PSTATE_LEVELING PStateLevelingMain; - #define USER_PSTATE_OPTION_LEVEL PStateLevelingMain - #else - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #endif - #if AGESA_ENTRY_INIT_LATE == TRUE - #define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables - #else -// OPTION_ACPI_FEATURE CreateAcpiTablesStub; - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #endif - #if AGESA_ENTRY_INIT_POST == TRUE - #define USER_PSTATE_OPTION_GATHER PStateGatherMain - #else - OPTION_PSTATE_GATHER PStateGatherStub; - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #endif - #if CFG_ACPI_PSTATES_PPC == TRUE - #define USER_PSTATE_CFG_PPC TRUE - #else - #define USER_PSTATE_CFG_PPC FALSE - #endif - #if CFG_ACPI_PSTATES_PCT == TRUE - #define USER_PSTATE_CFG_PCT TRUE - #else - #define USER_PSTATE_CFG_PCT FALSE - #endif - #if CFG_ACPI_PSTATES_PSD == TRUE - #define USER_PSTATE_CFG_PSD TRUE - #else - #define USER_PSTATE_CFG_PSD FALSE - #endif - #if CFG_ACPI_PSTATES_PSS == TRUE - #define USER_PSTATE_CFG_PSS TRUE - #else - #define USER_PSTATE_CFG_PSS FALSE - #endif - #if CFG_ACPI_PSTATES_XPSS == TRUE - #define USER_PSTATE_CFG_XPSS TRUE - #else - #define USER_PSTATE_CFG_XPSS FALSE - #endif - - #if OPTION_IO_CSTATE == TRUE -// OPTION_ACPI_FEATURE CreateCStateAcpiTables; - #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables - #else - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #endif - #else - OPTION_SSDT_FEATURE GenerateSsdtStub; - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - OPTION_PSTATE_GATHER PStateGatherStub; - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_SSDT_MAIN GenerateSsdtStub - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #define USER_PSTATE_CFG_PPC FALSE - #define USER_PSTATE_CFG_PCT FALSE - #define USER_PSTATE_CFG_PSD FALSE - #define USER_PSTATE_CFG_PSS FALSE - #define USER_PSTATE_CFG_XPSS FALSE - - // If ACPI Objects are disabled for PStates, we still need to check - // whether ACPI Objects are enabled for CStates - #if OPTION_IO_CSTATE == TRUE - OPTION_SSDT_FEATURE GenerateSsdt; - OPTION_PSTATE_GATHER PStateGatherMain; - OPTION_ACPI_FEATURE CreateCStateAcpiTables; - #undef USER_SSDT_MAIN - #define USER_SSDT_MAIN GenerateSsdt - #undef USER_PSTATE_OPTION_GATHER - #define USER_PSTATE_OPTION_GATHER PStateGatherMain - #undef USER_CSTATE_OPTION_MAIN - #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables - #endif - #endif -#else - OPTION_SSDT_FEATURE GenerateSsdtStub; - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - OPTION_PSTATE_GATHER PStateGatherStub; - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_SSDT_MAIN GenerateSsdtStub - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #define USER_PSTATE_CFG_PPC FALSE - #define USER_PSTATE_CFG_PCT FALSE - #define USER_PSTATE_CFG_PSD FALSE - #define USER_PSTATE_CFG_PSS FALSE - #define USER_PSTATE_CFG_XPSS FALSE -#endif - -/* Declare the instance of the PSTATE option configuration structure */ -OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { - PSTATE_STRUCT_VERSION, - USER_PSTATE_OPTION_GATHER, - USER_PSTATE_OPTION_LEVEL -}; - -OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = { - PSTATE_STRUCT_VERSION, - USER_SSDT_MAIN, - USER_PSTATE_OPTION_MAIN, - USER_CSTATE_OPTION_MAIN, - USER_PSTATE_CFG_PPC, - USER_PSTATE_CFG_PCT, - USER_PSTATE_CFG_PSD, - USER_PSTATE_CFG_PSS, - USER_PSTATE_CFG_XPSS -}; - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] = -{ - F10_PSTATE_SERVICE_SUPPORT - F12_PSTATE_SERVICE_SUPPORT - F14_PSTATE_SERVICE_SUPPORT - F15_OR_PSTATE_SERVICE_SUPPORT - F15_TN_PSTATE_SERVICE_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable = -{ - (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &PstateCpuFamilyServiceArray[0] -}; -#endif // _OPTION_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionS3ScriptInstall.h deleted file mode 100644 index 5b62bdf6dc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionS3ScriptInstall.h +++ /dev/null @@ -1,91 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: S3SCRIPT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_S3SCRIPT_INSTALL_H_ -#define _OPTION_S3SCRIPT_INSTALL_H_ - -#include "S3SaveState.h" -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#ifndef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT FALSE //if not define assume PI not use script -#endif - -#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) - #if OPTION_S3SCRIPT == TRUE - #define P_S3_SCRIPT_INIT S3ScriptInitState - #endif -#endif - -#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - #if OPTION_S3SCRIPT == TRUE - #define P_S3_SCRIPT_RESTORE S3ScriptRestoreState - #endif -#endif - -#ifndef P_S3_SCRIPT_INIT - #define P_S3_SCRIPT_INIT S3ScriptInitStateStub -#endif - -#ifndef P_S3_SCRIPT_RESTORE - #define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub - #undef GNB_S3_DISPATCH_FUNCTION_TABLE -#endif - -#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE - #define GNB_S3_DISPATCH_FUNCTION_TABLE -#endif - -/* Declare the instance of the S3SCRIPT option configuration structure */ -S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = { - P_S3_SCRIPT_INIT, - P_S3_SCRIPT_RESTORE -}; - -S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = { - GNB_S3_DISPATCH_FUNCTION_TABLE - {0, NULL} -}; -#endif // _OPTION_S3SCRIPT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionSlitInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionSlitInstall.h deleted file mode 100644 index 915e5302c4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionSlitInstall.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SLIT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_SLIT_INSTALL_H_ -#define _OPTION_SLIT_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_SLIT - #error BLDOPT: Option not defined: "OPTION_SLIT" - #endif - #if OPTION_SLIT == TRUE - OPTION_SLIT_FEATURE GetAcpiSlitMain; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer; - #define USER_SLIT_OPTION GetAcpiSlitMain - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer - #else - OPTION_SLIT_FEATURE GetAcpiSlitStub; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; - #define USER_SLIT_OPTION GetAcpiSlitStub - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub - #endif -#else - OPTION_SLIT_FEATURE GetAcpiSlitStub; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; - #define USER_SLIT_OPTION GetAcpiSlitStub - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub -#endif -/* Declare the instance of the SLIT option configuration structure */ -OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = { - SLIT_STRUCT_VERSION, - USER_SLIT_OPTION, - USER_SLIT_RELEASE_BUFFER -}; - -#endif // _OPTION_SLIT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionSratInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionSratInstall.h deleted file mode 100644 index 273874753f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionSratInstall.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SRAT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_SRAT_INSTALL_H_ -#define _OPTION_SRAT_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_SRAT - #error BLDOPT: Option not defined: "OPTION_SRAT" - #endif - #if OPTION_SRAT == TRUE - OPTION_SRAT_FEATURE GetAcpiSratMain; - #define USER_SRAT_OPTION GetAcpiSratMain - #else - OPTION_SRAT_FEATURE GetAcpiSratStub; - #define USER_SRAT_OPTION GetAcpiSratStub - #endif -#else - OPTION_SRAT_FEATURE GetAcpiSratStub; - #define USER_SRAT_OPTION GetAcpiSratStub -#endif - -/* Declare the instance of the WHEA option configuration structure */ -OPTION_SRAT_CONFIGURATION OptionSratConfiguration = { - SRAT_STRUCT_VERSION, - USER_SRAT_OPTION -}; - -#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionSwC1eInstall.h deleted file mode 100644 index 34886eee14..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionSwC1eInstall.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SW C1e - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_SW_C1E_INSTALL_H_ -#define _OPTION_SW_C1E_INSTALL_H_ - -#include "cpuSwC1e.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_SW_C1E_FEAT -#define F10_SW_C1E_SUPPORT -#if AGESA_ENTRY_INIT_EARLY == TRUE - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e; - #undef OPTION_SW_C1E_FEAT - #define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e, - extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e; - #undef F10_SW_C1E_SUPPORT - #define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e}, - #endif - #endif - #endif - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] = - { - F10_SW_C1E_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable = - { - (sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &SwC1eFamilyServiceArray[0] - }; -#endif - -#endif // _OPTION_SW_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionWheaInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionWheaInstall.h deleted file mode 100644 index 5facece353..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/OptionWheaInstall.h +++ /dev/null @@ -1,74 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: WHEA - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_WHEA_INSTALL_H_ -#define _OPTION_WHEA_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_WHEA - #error BLDOPT: Option not defined: "OPTION_WHEA" - #endif - #if OPTION_WHEA == TRUE - OPTION_WHEA_FEATURE GetAcpiWheaMain; - #define USER_WHEA_OPTION GetAcpiWheaMain - #else - OPTION_WHEA_FEATURE GetAcpiWheaStub; - #define USER_WHEA_OPTION GetAcpiWheaStub - #endif - -#else - OPTION_WHEA_FEATURE GetAcpiWheaStub; - #define USER_WHEA_OPTION GetAcpiWheaStub -#endif - -/* Declare the instance of the WHEA option configuration structure */ -OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = { - WHEA_STRUCT_VERSION, - USER_WHEA_OPTION -}; - -#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h deleted file mode 100644 index 1fe116a6c7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h +++ /dev/null @@ -1,2588 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a combination of package type, processor, and features. - * - * This file generates the defaults tables for the all platform solution - * combinations. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef RUN_BROKEN_AGESA_TESTS - #define RUN_BROKEN_AGESA_TESTS 0 -#endif - -/***************************************************************************** - * - * Start processing the user options: First, set default settings - * - ****************************************************************************/ - - -VOLATILE AMD_MODULE_HEADER mCpuModuleID = { - //ModuleHeaderSignature - // Remove 'DOM$' as temp solution before update BinUtil.exe , - Int32FromChar ('0', '0', '0', '0'), - //ModuleIdentifier[8] - AGESA_ID, - //ModuleVersion[12] - AGESA_VERSION_STRING, - //ModuleDispatcher - NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher), - //NextBlock - NULL -}; - - -/* Process solution defined socket / family installations - * - * As part of the release package for each image, define the options below to select the - * AGESA processor support included in that image. - */ - -/* Default sockets to off */ -#define OPTION_G34_SOCKET_SUPPORT FALSE -#define OPTION_C32_SOCKET_SUPPORT FALSE -#define OPTION_S1G3_SOCKET_SUPPORT FALSE -#define OPTION_S1G4_SOCKET_SUPPORT FALSE -#define OPTION_ASB2_SOCKET_SUPPORT FALSE -#define OPTION_FS1_SOCKET_SUPPORT FALSE -#define OPTION_FM1_SOCKET_SUPPORT FALSE -#define OPTION_FP1_SOCKET_SUPPORT FALSE -#define OPTION_FT1_SOCKET_SUPPORT FALSE -#define OPTION_AM3_SOCKET_SUPPORT FALSE - -/* Default families to off */ -#define OPTION_FAMILY10H FALSE -#define OPTION_FAMILY12H FALSE -#define OPTION_FAMILY14H FALSE -#define OPTION_FAMILY15H FALSE - - -/* Enable the appropriate socket support */ -#ifdef INSTALL_G34_SOCKET_SUPPORT - #if INSTALL_G34_SOCKET_SUPPORT == TRUE - #undef OPTION_G34_SOCKET_SUPPORT - #define OPTION_G34_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_C32_SOCKET_SUPPORT - #if INSTALL_C32_SOCKET_SUPPORT == TRUE - #undef OPTION_C32_SOCKET_SUPPORT - #define OPTION_C32_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_S1G3_SOCKET_SUPPORT - #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE - #undef OPTION_S1G3_SOCKET_SUPPORT - #define OPTION_S1G3_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_S1G4_SOCKET_SUPPORT - #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE - #undef OPTION_S1G4_SOCKET_SUPPORT - #define OPTION_S1G4_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_ASB2_SOCKET_SUPPORT - #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE - #undef OPTION_ASB2_SOCKET_SUPPORT - #define OPTION_ASB2_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FS1_SOCKET_SUPPORT - #if INSTALL_FS1_SOCKET_SUPPORT == TRUE - #undef OPTION_FS1_SOCKET_SUPPORT - #define OPTION_FS1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FM1_SOCKET_SUPPORT - #if INSTALL_FM1_SOCKET_SUPPORT == TRUE - #undef OPTION_FM1_SOCKET_SUPPORT - #define OPTION_FM1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FP1_SOCKET_SUPPORT - #if INSTALL_FP1_SOCKET_SUPPORT == TRUE - #undef OPTION_FP1_SOCKET_SUPPORT - #define OPTION_FP1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FT1_SOCKET_SUPPORT - #if INSTALL_FT1_SOCKET_SUPPORT == TRUE - #undef OPTION_FT1_SOCKET_SUPPORT - #define OPTION_FT1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_AM3_SOCKET_SUPPORT - #if INSTALL_AM3_SOCKET_SUPPORT == TRUE - #undef OPTION_AM3_SOCKET_SUPPORT - #define OPTION_AM3_SOCKET_SUPPORT TRUE - #endif -#endif - - -/* Enable the appropriate family support */ -// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3 -#ifdef INSTALL_FAMILY_10_SUPPORT - #if INSTALL_FAMILY_10_SUPPORT == TRUE - #undef OPTION_FAMILY10H - #define OPTION_FAMILY10H TRUE - #endif -#endif - -// F12 is supported in FP1, FS1, & FM1 -#ifdef INSTALL_FAMILY_12_SUPPORT - #if INSTALL_FAMILY_12_SUPPORT == TRUE - #undef OPTION_FAMILY12H - #define OPTION_FAMILY12H TRUE - #endif -#endif - -// F14 is supported in FT1 -#ifdef INSTALL_FAMILY_14_SUPPORT - #if INSTALL_FAMILY_14_SUPPORT == TRUE - #undef OPTION_FAMILY14H - #define OPTION_FAMILY14H TRUE - #endif -#endif - -// F15 is supported in G34, C32, & AM3 -#ifdef INSTALL_FAMILY_15_SUPPORT - #if INSTALL_FAMILY_15_SUPPORT == TRUE - #undef OPTION_FAMILY15H - #define OPTION_FAMILY15H TRUE - #endif -#endif - - -/* Turn off families not required by socket designations */ -#if (OPTION_FAMILY10H == TRUE) - #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY10H - #define OPTION_FAMILY10H FALSE - #endif -#endif - -#if (OPTION_FAMILY12H == TRUE) - #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY12H - #define OPTION_FAMILY12H FALSE - #endif -#endif - -#if (OPTION_FAMILY14H == TRUE) - #if (OPTION_FT1_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY14H - #define OPTION_FAMILY14H FALSE - #endif -#endif - -#if (OPTION_FAMILY15H == TRUE) - #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY15H - #define OPTION_FAMILY15H FALSE - #endif -#endif - - -/* Check for invalid combinations of socket/family */ -#if (OPTION_G34_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) - #error No G34 supported families included in the build - #endif -#endif - -#if (OPTION_C32_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) - #error No C32 supported families included in the build - #endif -#endif - -#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No S1G3 supported families included in the build - #endif -#endif - -#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No S1G4 supported families included in the build - #endif -#endif - -#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No ASB2 supported families included in the build - #endif -#endif - -#if (OPTION_FS1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) - #error No FS1 supported families included in the build - #endif -#endif - -#if (OPTION_FM1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) - #error No FM1 supported families included in the build - #endif -#endif - -#if (OPTION_FP1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) - #error No FP1 supported families included in the build - #endif -#endif - -#if (OPTION_FT1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY14H == FALSE) - #error No FT1 supported families included in the build - #endif -#endif - -#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) - #error No AM3 supported families included in the build - #endif -#endif - - -/* Process AGESA private data - * - * Turn on appropriate CPU models and memory controllers, - * as well as some other memory controls. - */ - -/* Default all models to off */ -#define OPTION_FAMILY10H_BL FALSE -#define OPTION_FAMILY10H_DA FALSE -#define OPTION_FAMILY10H_HY FALSE -#define OPTION_FAMILY10H_PH FALSE -#define OPTION_FAMILY10H_RB FALSE -#define OPTION_FAMILY12H_LN FALSE -#define OPTION_FAMILY14H_ON FALSE -#define OPTION_FAMILY15H_OR FALSE - -/* Default all memory controllers to off */ -#define OPTION_MEMCTLR_DR FALSE -#define OPTION_MEMCTLR_HY FALSE -#define OPTION_MEMCTLR_OR FALSE -#define OPTION_MEMCTLR_C32 FALSE -#define OPTION_MEMCTLR_DA FALSE -#define OPTION_MEMCTLR_LN FALSE -#define OPTION_MEMCTLR_ON FALSE -#define OPTION_MEMCTLR_Ni FALSE -#define OPTION_MEMCTLR_PH FALSE -#define OPTION_MEMCTLR_RB FALSE - -/* Default all memory controls to off */ -#define OPTION_HW_WRITE_LEV_TRAINING FALSE -#define OPTION_SW_WRITE_LEV_TRAINING FALSE -#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE -#define OPTION_HW_DQS_REC_EN_TRAINING FALSE -#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE -#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE -#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE -#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE -#define OPTION_MAX_RD_LAT_TRAINING FALSE -#define OPTION_HW_DRAM_INIT FALSE -#define OPTION_SW_DRAM_INIT FALSE -#define OPTION_S3_MEM_SUPPORT FALSE -#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE -#define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE - -/* Defaults for public user options */ -#define OPTION_UDIMMS FALSE -#define OPTION_RDIMMS FALSE -#define OPTION_SODIMMS FALSE -#define OPTION_LRDIMMS FALSE -#define OPTION_DDR2 FALSE -#define OPTION_DDR3 FALSE -#define OPTION_ECC FALSE -#define OPTION_BANK_INTERLEAVE FALSE -#define OPTION_DCT_INTERLEAVE FALSE -#define OPTION_NODE_INTERLEAVE FALSE -#define OPTION_PARALLEL_TRAINING FALSE -#define OPTION_ONLINE_SPARE FALSE -#define OPTION_MEM_RESTORE FALSE -#define OPTION_DIMM_EXCLUDE FALSE - -/* Default all CPU controls to off */ -#define OPTION_MULTISOCKET FALSE -#define OPTION_SRAT FALSE -#define OPTION_SLIT FALSE -#define OPTION_HT_ASSIST FALSE -#define OPTION_ATM_MODE FALSE -#define OPTION_CPU_CORELEVLING FALSE -#define OPTION_MSG_BASED_C1E FALSE -#define OPTION_CPU_CFOH FALSE -#define OPTION_C6_STATE FALSE -#define OPTION_IO_CSTATE FALSE -#define OPTION_CPB FALSE -#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE -#define OPTION_S3SCRIPT FALSE -#define OPTION_GFX_RECOVERY FALSE - -/* Default FCH controls to off */ -#define FCH_SUPPORT FALSE - -/* Enable all private controls based on socket/family enables */ -#if (OPTION_G34_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_HY - #define OPTION_FAMILY10H_HY TRUE - #undef OPTION_MEMCTLR_HY - #define OPTION_MEMCTLR_HY TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_C32_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_HY - #define OPTION_FAMILY10H_HY TRUE - #undef OPTION_MEMCTLR_C32 - #define OPTION_MEMCTLR_C32 TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_Ni - #define OPTION_MEMCTLR_Ni TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FS1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == TRUE) - #undef OPTION_FAMILY12H_LN - #define OPTION_FAMILY12H_LN TRUE - #undef OPTION_MEMCTLR_LN - #define OPTION_MEMCTLR_LN TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FM1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == TRUE) - #undef OPTION_FAMILY12H_LN - #define OPTION_FAMILY12H_LN TRUE - #undef OPTION_MEMCTLR_LN - #define OPTION_MEMCTLR_LN TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FP1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == TRUE) - #undef OPTION_FAMILY12H_LN - #define OPTION_FAMILY12H_LN TRUE - #undef OPTION_MEMCTLR_LN - #define OPTION_MEMCTLR_LN TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FT1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY14H == TRUE) - #undef OPTION_FAMILY14H_ON - #define OPTION_FAMILY14H_ON TRUE - #undef OPTION_MEMCTLR_ON - #define OPTION_MEMCTLR_ON TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_FAMILY10H_PH - #define OPTION_FAMILY10H_PH TRUE - #undef OPTION_FAMILY10H_RB - #define OPTION_FAMILY10H_RB TRUE - #undef OPTION_MEMCTLR_RB - #define OPTION_MEMCTLR_RB TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_MEMCTLR_PH - #define OPTION_MEMCTLR_PH TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) - #undef GNB_SUPPORT - #define GNB_SUPPORT TRUE -#endif - -#define OPTION_ACPI_PSTATES TRUE -#define OPTION_WHEA TRUE -#define OPTION_DMI TRUE -#define OPTION_EARLY_SAMPLES FALSE -#define CFG_ACPI_PSTATES_PPC TRUE -#define CFG_ACPI_PSTATES_PCT TRUE -#define CFG_ACPI_PSTATES_PSD TRUE -#define CFG_ACPI_PSTATES_PSS TRUE -#define CFG_ACPI_PSTATES_XPSS TRUE -#define CFG_ACPI_PSTATE_PSD_INDPX FALSE -#define CFG_VRM_HIGH_SPEED_ENABLE FALSE -#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define OPTION_ALIB TRUE -/*--------------------------------------------------------------------------- - * Processing the options: Second, process the user's selections - *--------------------------------------------------------------------------*/ -#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT - #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ECC_SUPPORT - #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE - #undef OPTION_ECC - #define OPTION_ECC FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT - #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT - #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT - #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT - #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE - #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE - #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE - #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING - #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT - #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING - #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ACPI_PSTATES - #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE - #undef OPTION_ACPI_PSTATES - #define OPTION_ACPI_PSTATES FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SRAT - #if BLDOPT_REMOVE_SRAT == TRUE - #undef OPTION_SRAT - #define OPTION_SRAT FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SLIT - #if BLDOPT_REMOVE_SLIT == TRUE - #undef OPTION_SLIT - #define OPTION_SLIT FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_WHEA - #if BLDOPT_REMOVE_WHEA == TRUE - #undef OPTION_WHEA - #define OPTION_WHEA FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_DMI - #if BLDOPT_REMOVE_DMI == TRUE - #undef OPTION_DMI - #define OPTION_DMI FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR - #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_HT_ASSIST - #if BLDOPT_REMOVE_HT_ASSIST == TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_ATM_MODE - #if BLDOPT_REMOVE_ATM_MODE == TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_MSG_BASED_C1E - #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_C6_STATE - #if BLDOPT_REMOVE_C6_STATE == TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_GFX_RECOVERY - #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC - #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE - #undef CFG_ACPI_PSTATES_PPC - #define CFG_ACPI_PSTATES_PPC FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT - #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE - #undef CFG_ACPI_PSTATES_PCT - #define CFG_ACPI_PSTATES_PCT FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD - #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE - #undef CFG_ACPI_PSTATES_PSD - #define CFG_ACPI_PSTATES_PSD FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS - #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE - #undef CFG_ACPI_PSTATES_PSS - #define CFG_ACPI_PSTATES_PSS FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS - #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE - #undef CFG_ACPI_PSTATES_XPSS - #define CFG_ACPI_PSTATES_XPSS FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT - #if BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE - #endif -#endif - -#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT - #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE - #undef CFG_ACPI_PSTATE_PSD_INDPX - #define CFG_ACPI_PSTATE_PSD_INDPX TRUE - #endif -#endif - -#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE - #undef CFG_VRM_HIGH_SPEED_ENABLE - #define CFG_VRM_HIGH_SPEED_ENABLE TRUE - #endif -#endif - -#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE - #undef CFG_VRM_NB_HIGH_SPEED_ENABLE - #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE - #endif -#endif - -#ifdef BLDCFG_STARTING_BUSNUM - #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM) -#else - #define CFG_STARTING_BUSNUM (0) -#endif - -#ifdef BLDCFG_AMD_PLATFORM_TYPE - #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE -#else - #define CFG_AMD_PLATFORM_TYPE 0 -#endif - -CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; - -#ifdef BLDCFG_MAXIMUM_BUSNUM - #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM) -#else - #define CFG_MAXIMUM_BUSNUM (0xF8) -#endif - -#ifdef BLDCFG_ALLOCATED_BUSNUM - #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM) -#else - #define CFG_ALLOCATED_BUSNUM (0x20) -#endif - -#ifdef BLDCFG_BUID_SWAP_LIST - #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST) -#else - #define CFG_BUID_SWAP_LIST (NULL) -#endif - -#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST - #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST) -#else - #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL) -#endif - -#ifdef BLDCFG_HTFABRIC_LIMITS_LIST - #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST) -#else - #define CFG_HTFABRIC_LIMITS_LIST (NULL) -#endif - -#ifdef BLDCFG_HTCHAIN_LIMITS_LIST - #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST) -#else - #define CFG_HTCHAIN_LIMITS_LIST (NULL) -#endif - -#ifdef BLDCFG_BUS_NUMBERS_LIST - #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST) -#else - #define CFG_BUS_NUMBERS_LIST (NULL) -#endif - -#ifdef BLDCFG_IGNORE_LINK_LIST - #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST) -#else - #define CFG_IGNORE_LINK_LIST (NULL) -#endif - -#ifdef BLDCFG_LINK_SKIP_REGANG_LIST - #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST) -#else - #define CFG_LINK_SKIP_REGANG_LIST (NULL) -#endif - -#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD - #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD) -#else - #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE) -#endif - -#ifdef BLDCFG_USE_UNIT_ID_CLUMPING - #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING) -#else - #define CFG_USE_UNIT_ID_CLUMPING (FALSE) -#endif - -#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST - #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST) -#else - #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL) -#endif - -#ifdef BLDCFG_USE_HT_ASSIST - #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST) -#else - #define CFG_USE_HT_ASSIST (TRUE) -#endif - -#ifdef BLDCFG_USE_ATM_MODE - #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE) -#else - #define CFG_USE_ATM_MODE (TRUE) -#endif - -#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE - #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE) -#else - #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm) -#endif - -#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST - #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST) -#else - #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL) -#endif - -#ifdef BLDCFG_VRM_ADDITIONAL_DELAY - #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY) -#else - #define CFG_VRM_ADDITIONAL_DELAY (0) -#endif - -#ifdef BLDCFG_VRM_CURRENT_LIMIT - #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT -#else - #define CFG_VRM_CURRENT_LIMIT 0 -#endif - -#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD - #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD -#else - #define CFG_VRM_LOW_POWER_THRESHOLD 0 -#endif - -#ifdef BLDCFG_VRM_SLEW_RATE - #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#else - #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE -#endif - -#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT - #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT -#else - #define CFG_VRM_INRUSH_CURRENT_LIMIT 0 -#endif - -#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY - #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY) -#else - #define CFG_VRM_NB_ADDITIONAL_DELAY (0) -#endif - -#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT - #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT -#else - #define CFG_VRM_NB_CURRENT_LIMIT (0) -#endif - -#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD - #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD -#else - #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0) -#endif - -#ifdef BLDCFG_VRM_NB_SLEW_RATE - #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE -#else - #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE -#endif - -#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT - #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT -#else - #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0) -#endif - - -#ifdef BLDCFG_PLAT_NUM_IO_APICS - #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS -#else - #define CFG_PLAT_NUM_IO_APICS 0 -#endif - -#ifdef BLDCFG_MEM_INIT_PSTATE - #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE -#else - #define CFG_MEM_INIT_PSTATE 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_MODE - #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE -#else - #define CFG_C1E_MODE C1eModeDisabled -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA - #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA -#else - #define CFG_C1E_OPDATA 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA1 - #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1 -#else - #define CFG_C1E_OPDATA1 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA2 - #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2 -#else - #define CFG_C1E_OPDATA2 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA3 - #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3 -#else - #define CFG_C1E_OPDATA3 0 -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_MODE - #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE -#else - #define CFG_CSTATE_MODE CStateModeDisabled -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA - #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA -#else - #define CFG_CSTATE_OPDATA 0 -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS - #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS -#else - #define CFG_CSTATE_IO_BASE_ADDRESS 0 -#endif - -#ifdef BLDCFG_PLATFORM_CPB_MODE - #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE -#else - #define CFG_CPB_MODE CpbModeAuto -#endif - -#ifdef BLDCFG_CORE_LEVELING_MODE - #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE -#else - #define CFG_CORE_LEVELING_MODE 0 -#endif - -#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE - #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE -#else - #define CFG_AMD_PSTATE_CAP_VALUE 0 -#endif - -#ifdef BLDCFG_HEAP_DRAM_ADDRESS - #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS -#else - #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS -#endif - -#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT -#else - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY -#endif - -#ifdef BLDCFG_MEMORY_MODE_UNGANGED - #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED -#else - #define CFG_MEMORY_MODE_UNGANGED TRUE -#endif - -#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE - #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE -#else - #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_QUADRANK_TYPE - #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE -#else - #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE -#endif - -#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE - #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE -#else - #define CFG_MEMORY_RDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE - #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE -#else - #define CFG_MEMORY_LRDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE - #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE -#else - #define CFG_MEMORY_UDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE - #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE -#else - #define CFG_MEMORY_SODIMM_CAPABLE FALSE -#endif - -#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB - #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB -#else - #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE -#endif - -#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING - #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING -#else - #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#endif - -#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING - #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING -#else - #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#endif - -#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING - #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING -#else - #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#endif - -#ifdef BLDCFG_MEMORY_POWER_DOWN - #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN -#else - #define CFG_MEMORY_POWER_DOWN FALSE -#endif - -#ifdef BLDCFG_POWER_DOWN_MODE - #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE -#else - #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO -#endif - -#ifdef BLDCFG_ONLINE_SPARE - #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE -#else - #define CFG_ONLINE_SPARE FALSE -#endif - -#ifdef BLDCFG_MEMORY_PARITY_ENABLE - #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE -#else - #define CFG_MEMORY_PARITY_ENABLE FALSE -#endif - -#ifdef BLDCFG_BANK_SWIZZLE - #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE -#else - #define CFG_BANK_SWIZZLE TRUE -#endif - -#ifdef BLDCFG_TIMING_MODE_SELECT - #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT -#else - #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#endif - -#ifdef BLDCFG_MEMORY_CLOCK_SELECT - #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT -#else - #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY -#endif - -#ifdef BLDCFG_DQS_TRAINING_CONTROL - #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL -#else - #define CFG_DQS_TRAINING_CONTROL TRUE -#endif - -#ifdef BLDCFG_IGNORE_SPD_CHECKSUM - #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM -#else - #define CFG_IGNORE_SPD_CHECKSUM FALSE -#endif - -#ifdef BLDCFG_USE_BURST_MODE - #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE -#else - #define CFG_USE_BURST_MODE FALSE -#endif - -#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON - #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON -#else - #define CFG_MEMORY_ALL_CLOCKS_ON FALSE -#endif - -#ifdef BLDCFG_ENABLE_ECC_FEATURE - #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE -#else - #define CFG_ENABLE_ECC_FEATURE TRUE -#endif - -#ifdef BLDCFG_ECC_REDIRECTION - #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION -#else - #define CFG_ECC_REDIRECTION FALSE -#endif - -#ifdef BLDCFG_SCRUB_DRAM_RATE - #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE -#else - #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE -#endif - -#ifdef BLDCFG_SCRUB_L2_RATE - #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE -#else - #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE -#endif - -#ifdef BLDCFG_SCRUB_L3_RATE - #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE -#else - #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE -#endif - -#ifdef BLDCFG_SCRUB_IC_RATE - #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE -#else - #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE -#endif - -#ifdef BLDCFG_SCRUB_DC_RATE - #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE -#else - #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE -#endif - -#ifdef BLDCFG_ECC_SYNC_FLOOD - #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD -#else - #define CFG_ECC_SYNC_FLOOD TRUE -#endif - -#ifdef BLDCFG_ECC_SYMBOL_SIZE - #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE -#else - #define CFG_ECC_SYMBOL_SIZE 0 -#endif - -#ifdef BLDCFG_1GB_ALIGN - #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN -#else - #define CFG_1GB_ALIGN FALSE -#endif - -#ifdef BLDCFG_UMA_ALLOCATION_MODE - #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE -#else - #define CFG_UMA_MODE UMA_AUTO -#endif - -#ifdef BLDCFG_UMA_ALLOCATION_SIZE - #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE -#else - #define CFG_UMA_SIZE 0 -#endif - -#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT - #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT -#else - #define CFG_UMA_ABOVE4G FALSE -#endif - -#ifdef BLDCFG_UMA_ALIGNMENT - #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT -#else - #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB - #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB -#else - #define CFG_PROCESSOR_SCOPE_IN_SB FALSE -#endif - -#ifdef BLDCFG_S3_LATE_RESTORE - #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE -#else - #define CFG_S3_LATE_RESTORE TRUE -#endif - -#ifdef BLDCFG_USE_32_BYTE_REFRESH - #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH) -#else - #define CFG_USE_32_BYTE_REFRESH (FALSE) -#endif - -#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY - #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY) -#else - #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE) -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0 - #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0 -#else - #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1 - #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1 -#else - #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1 -#endif - -#ifdef BLDCFG_CFG_GNB_HD_AUDIO - #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO -#else - #define CFG_GNB_HD_AUDIO TRUE -#endif - -#ifdef BLDCFG_CFG_ABM_SUPPORT - #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT -#else - #define CFG_ABM_SUPPORT FALSE -#endif - -#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE - #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE -#else - #define CFG_DYNAMIC_REFRESH_RATE 0 -#endif - -#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL - #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL -#else - #define CFG_LCD_BACK_LIGHT_CONTROL 0 -#endif - -#ifdef BLDCFG_STEREO_3D_PINOUT - #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT -#else - #define CFG_GNB_STEREO_3D_PINOUT 0 -#endif - -#ifdef BLDCFG_IGPU_SUBSYSTEM_ID - #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID -#else - #define CFG_GNB_IGPU_SSID 0 -#endif - -#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID - #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID -#else - #define CFG_GNB_HDAUDIO_SSID 0 -#endif - -#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID - #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID -#else - #define CFG_GNB_PCIE_SSID 0x12341022 -#endif - -#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM - #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM -#else - #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0 -#endif - -#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE - #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE -#else - #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0 -#endif - -#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM - #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM -#else - #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0 -#endif - -#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS - #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS -#else - #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -#endif - -#ifdef BLDOPT_REMOVE_EARLY_SAMPLES - #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE - #undef OPTION_EARLY_SAMPLES - #define OPTION_EARLY_SAMPLES FALSE - #else - #undef OPTION_EARLY_SAMPLES - #define OPTION_EARLY_SAMPLES TRUE - #endif -#endif - -#ifdef BLDOPT_REMOVE_ALIB - #if BLDOPT_REMOVE_ALIB == TRUE - #undef OPTION_ALIB - #define OPTION_ALIB FALSE - #else - #undef OPTION_ALIB - #define OPTION_ALIB TRUE - #endif -#endif - -#ifdef BLDCFG_IOMMU_SUPPORT - #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT -#else - #define CFG_IOMMU_SUPPORT TRUE -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE - #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE -#else - #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL -#else - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON -#else - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0 -#endif - -#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE - #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE -#else - #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY - #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY -#else - #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON - #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON -#else - #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL - #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL -#else - #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0 -#endif - -#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ - #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ -#else - #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0 -#endif - -#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE - #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE -#else - #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0 -#endif - - -// BLDCFG_LVDS_24BBP_PANEL_MODE -// This specifies the LVDS 24 BBP mode. -// 0 - Use LDI mode (default). -// 1 - Use FPDI mode. -#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE - #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE -#else - #define CFG_LVDS_24BBP_PANEL_MODE 0 -#endif - -#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE - #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE) -#else - #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) -#endif - -#ifdef BLDCFG_PCI_MMIO_BASE - #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE) -#else - #define CFG_PCI_MMIO_BASE (0) -#endif - -#ifdef BLDCFG_PCI_MMIO_SIZE - #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE) -#else - #define CFG_PCI_MMIO_SIZE (0) -#endif - -#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST - #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) -#else - #define CFG_AP_MTRR_SETTINGS_LIST (NULL) -#endif - -/*--------------------------------------------------------------------------- - * Processing the options: Third, perform the option cross checks - *--------------------------------------------------------------------------*/ -// Assure that at least one type of memory support is included -#if OPTION_UDIMMS == FALSE - #if OPTION_RDIMMS == FALSE - #if OPTION_SODIMMS == FALSE - #if OPTION_LRDIMMS == FALSE - #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE. - #endif - #endif - #endif -#endif -// Ensure at least one dimm type is capable -#if CFG_MEMORY_RDIMM_CAPABLE == FALSE - #if CFG_MEMORY_UDIMM_CAPABLE == FALSE - #if CFG_MEMORY_SODIMM_CAPABLE == FALSE - #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE - #error BLDCFG: No dimm type is capable - #endif - #endif - #endif -#endif -// Turn off multi-socket based features if only one node... -#if OPTION_MULTISOCKET == FALSE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING FALSE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE FALSE -#endif -// Ensure that at least one write leveling option is selected -#if OPTION_DDR3 == TRUE - #if OPTION_HW_WRITE_LEV_TRAINING == FALSE - #if OPTION_SW_WRITE_LEV_TRAINING == FALSE - #error No Write leveling option selected for DDR3 - #endif - #endif - #if OPTION_SW_DRAM_INIT == FALSE - #error Software dram init must be enabled for DDR3 dimms - #endif -#endif -// Ensure at least one DQS receiver training option is selected -#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE - #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE - #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE - #error No DQS receiver training option has been slected - #endif - #endif -#endif -// Ensure at least one Rd Wr position training option has been selected -#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE - #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE - #error No Rd Wr position training option has been selected - #endif -#endif -// Ensure at least one dram init option has been selected -#if OPTION_HW_DRAM_INIT == FALSE - #if OPTION_SW_DRAM_INIT == FALSE - #error No Dram init option has been selected - #endif -#endif -/* As an ENUM, DDRXXX_FREQUENCY is not defined when the c preprocessor runs. - * Removing this test for coreboot. - */ -#if RUN_BROKEN_AGESA_TESTS -// Ensure the frequency limit is valid -#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200) - #error BLDCFG: Unsupported memory bus frequency - #endif - #endif - #endif - #endif - #endif - #endif - #endif -#endif - -#endif -/* As an ENUM, TIMING_MODE_XXX is not defined when the c preprocessor runs. - * Removing this test for coreboot. - */ -#if RUN_BROKEN_AGESA_TESTS - -// Ensure timing mode is valid -#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC - #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED - #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO - #error BLDCFG: Invalid timing mode is set - #endif - #endif -#endif - -#endif -// Ensure the scrub rate is valid -#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF)) - #error BLDCFG: Unsupported dram scrub rate set -#endif -#if CFG_SCRUB_L2_RATE > 0x16 - #error BLDCFG: Unsupported L2 scrubber rate set -#endif -#if CFG_SCRUB_L3_RATE > 0x16 - #error BLDCFG: unsupported L3 scrubber rate set -#endif -#if CFG_SCRUB_IC_RATE > 0x16 - #error BLDCFG: Unsupported Instruction cache scrub rate set -#endif -#if CFG_SCRUB_DC_RATE > 0x16 - #error BLDCFG: Unsupported Dcache scrub rate set -#endif -/* As an ENUM, QUADRANK_XXX is not defined when the c preprocessor runs. - * Removing this test for coreboot. - */ -#if RUN_BROKEN_AGESA_TESTS - -// Ensure Quad rank dimm type is valid -#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED - #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED - #error BLDCFG: Invalid quad rank dimm type set - #endif -#endif - -#endif -// Ensure ECC symbol size is valid -#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG - #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4 - #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8 - #error BLDCFG: Invalid Ecc symbol size set - #endif - #endif -#endif -/* As an ENUM, POWER_DOWN_BY_XXX is not defined when the c preprocessor runs. - * Removing this test for coreboot. - */ -#if RUN_BROKEN_AGESA_TESTS - -// Ensure power down mode is valid -#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT - #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL - #error BLDCFG: Invalid power down mode set - #endif -#endif - -#endif -/***************************************************************************** - * - * Process the option logic, setting local control variables - * - ****************************************************************************/ -#if OPTION_ACPI_PSTATES == TRUE - #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain - #define OPTFCN_GATHER_DATA PStateGatherData - #if OPTION_MULTISOCKET == TRUE - #define OPTFCN_PSTATE_LEVELING PStateLeveling - #else - #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess - #endif -#else - #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess - #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess - #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess -#endif - - -/***************************************************************************** - * - * Include the structure definitions for the defaults table structures - * - ****************************************************************************/ -#include -#include -#include "Options.h" -#include "OptionCpuFamiliesInstall.h" -#include "OptionsHt.h" -#include "OptionHtInstall.h" -#include "OptionMemory.h" -#include "OptionMemoryInstall.h" -#include "OptionMemoryRecovery.h" -#include "OptionMemoryRecoveryInstall.h" -#include "OptionCpuFeaturesInstall.h" -#include "OptionDmi.h" -#include "OptionDmiInstall.h" -#include "OptionPstate.h" -#include "OptionPstateInstall.h" -#include "OptionWhea.h" -#include "OptionWheaInstall.h" -#include "OptionSrat.h" -#include "OptionSratInstall.h" -#include "OptionSlit.h" -#include "OptionSlitInstall.h" -#include "OptionMultiSocket.h" -#include "OptionMultiSocketInstall.h" -#include "OptionIdsInstall.h" -#include "OptionGfxRecovery.h" -#include "OptionGfxRecoveryInstall.h" -#include "OptionGnb.h" -#include "OptionGnbInstall.h" -#include "OptionS3ScriptInstall.h" -#include "OptionFchInstall.h" - - -/***************************************************************************** - * - * Generate the output structures (defaults tables) - * - ****************************************************************************/ -BUILD_OPT_CFG UserOptions = { - { // AGESA version string - AGESA_CODE_SIGNATURE, // code header Signature - AGESA_PACKAGE_STRING, // 8 character ID - AGESA_VERSION_STRING, // 12 character version string - 0 // null string terminator - }, - //Build Option Area - OPTION_UDIMMS, //UDIMMS - OPTION_RDIMMS, //RDIMMS - OPTION_LRDIMMS, //LRDIMMS - OPTION_ECC, //ECC - OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE - OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE - OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE - OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING - OPTION_ONLINE_SPARE, //ONLINE_SPARE - OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE - OPTION_MULTISOCKET, //MULTISOCKET - OPTION_ACPI_PSTATES, //ACPI_PSTATES - OPTION_SRAT, //SRAT - OPTION_SLIT, //SLIT - OPTION_WHEA, //WHEA - OPTION_DMI, //DMI - OPTION_EARLY_SAMPLES, //EARLY_SAMPLES - OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR - - //Build Configuration Area - CFG_PCI_MMIO_BASE, - CFG_PCI_MMIO_SIZE, - { - // CoreVrm - { - CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit - CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold - CFG_VRM_SLEW_RATE, // VrmSlewRate - CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay - CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable - CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit - }, - // NbVrm - { - CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit - CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold - CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate - CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay - CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable - CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit - } - }, - CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber - CFG_MEM_INIT_PSTATE, //MemoryInitPstate - CFG_C1E_MODE, //C1eMode - CFG_C1E_OPDATA, //C1ePlatformData - CFG_C1E_OPDATA1, //C1ePlatformData1 - CFG_C1E_OPDATA2, //C1ePlatformData2 - CFG_C1E_OPDATA3, //C1ePlatformData3 - CFG_CSTATE_MODE, //CStateMode - CFG_CSTATE_OPDATA, //CStatePlatformData - CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress - CFG_CPB_MODE, //CpbMode - CFG_CORE_LEVELING_MODE, //CoreLevelingCofig - { - CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode. - CFG_USE_HT_ASSIST, // CfgUseHtAssist - CFG_USE_ATM_MODE, // CfgUseAtmMode - CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets. - CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority. - CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode. - }, - (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings - CFG_AMD_PLATFORM_TYPE, //AmdPlatformType - CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck - - CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit - CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged - CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable - CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType - CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable - CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable - CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable - CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable - CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb - CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving - CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving - CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving - CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown - CFG_POWER_DOWN_MODE, // CfgPowerDownMode - CFG_ONLINE_SPARE, // CfgOnlineSpare - CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable - CFG_BANK_SWIZZLE, // CfgBankSwizzle - CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect - CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect - CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl - CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum - CFG_USE_BURST_MODE, // CfgUseBurstMode - CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn - CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature - CFG_ECC_REDIRECTION, // CfgEccRedirection - CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate - CFG_SCRUB_L2_RATE, // CfgScrubL2Rate - CFG_SCRUB_L3_RATE, // CfgScrubL3Rate - CFG_SCRUB_IC_RATE, // CfgScrubIcRate - CFG_SCRUB_DC_RATE, // CfgScrubDcRate - CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood - CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize - CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress - CFG_1GB_ALIGN, // CfgNodeMem1GBAlign - CFG_S3_LATE_RESTORE, // CfgS3LateRestore - CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent - (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList - CFG_UMA_MODE, // CfgUmaMode - CFG_UMA_SIZE, // CfgUmaSize - CFG_UMA_ABOVE4G, // CfgUmaAbove4G - CFG_UMA_ALIGNMENT, // CfgUmaAlignment - CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb - CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0 - CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1 - CFG_GNB_HD_AUDIO, // CfgGnbHdAudio - CFG_ABM_SUPPORT, // CfgAbmSupport - CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate - CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl - CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex - CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress - CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID - CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID - CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID - CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum - CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate - - CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress - CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress - CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress - CFG_ACPI_PM1_EVT_BLOCK_ADDRESS, // CfgAcpiPm1EvtBlkAddr - CFG_ACPI_PM1_CNT_BLOCK_ADDRESS, // CfgAcpiPm1CntBlkAddr - CFG_ACPI_PM_TMR_BLOCK_ADDRESS, // CfgAcpiPmTmrBlkAddr - CFG_ACPI_CPU_CNT_BLOCK_ADDRESS, // CfgCpuControlBlkAddr - CFG_ACPI_GPE0_BLOCK_ADDRESS, // CfgAcpiGpe0BlkAddr - CFG_SMI_CMD_PORT_ADDRESS, // CfgSmiCmdPortAddr - CFG_ACPI_PMA_CNTBLK_ADDRESS, // CfgAcpiPmaCntBlkAddr - CFG_GEC_SHADOW_ROM_BASE, // CfgGecShadowRomBase - CFG_WATCHDOG_TIMER_BASE, // CfgWatchDogTimerBase - CFG_SPI_ROM_BASE_ADDRESS, // CfgSpiRomBaseAddress - CFG_HPET_BASE_ADDRESS, // CfgHpetBaseAddress - CFG_AZALIA_SSID, // CfgAzaliaSsid - CFG_SMBUS_SSID, // CfgSmbusSsid - CFG_IDE_SSID, // CfgIdeSsid - CFG_SATA_AHCI_SSID, // CfgSataAhciSsid - CFG_SATA_IDE_SSID, // CfgSataIdeSsid - CFG_SATA_RAID5_SSID, // CfgSataRaid5Ssid - CFG_SATA_RAID_SSID, // CfgSataRaidSsid - CFG_EHCI_SSID, // CfgEhcidSsid - CFG_OHCI_SSID, // CfgOhcidSsid - CFG_LPC_SSID, // CfgLpcSsid - CFG_FCH_GPP_LINK_CONFIG, // CfgFchGppLinkConfig - CFG_FCH_GPP_PORT0_PRESENT, // CfgFchGppPort0Present - CFG_FCH_GPP_PORT1_PRESENT, // CfgFchGppPort1Present - CFG_FCH_GPP_PORT2_PRESENT, // CfgFchGppPort2Present - CFG_FCH_GPP_PORT3_PRESENT, // CfgFchGppPort3Present - CFG_FCH_GPP_PORT0_HOTPLUG, // CfgFchGppPort0HotPlug - CFG_FCH_GPP_PORT1_HOTPLUG, // CfgFchGppPort1HotPlug - CFG_FCH_GPP_PORT2_HOTPLUG, // CfgFchGppPort2HotPlug - CFG_FCH_GPP_PORT3_HOTPLUG, // CfgFchGppPort3HotPlug - - - CFG_IOMMU_SUPPORT, // CfgIommuSupport - CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE, // CfgLvdsPowerOnSeqDigonToDe - CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL, // CfgLvdsPowerOnSeqDeToVaryBl - CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON, // CfgLvdsPowerOnSeqDeToDigon - CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe - CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay - CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon - CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl - CFG_LVDS_MAX_PIXEL_CLOCK_FREQ, // CfgLvdsMaxPixelClockFreq - CFG_LCD_BIT_DEPTH_CONTROL_VALUE, // CfgLcdBitDepthControlValue - CFG_LVDS_24BBP_PANEL_MODE, // CfgLvds24bbpPanelMode - CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum - 0, //reserved... -}; - -CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = -{ - IDS_LATE_RUN_AP_TASK - // Get DMI info - CPU_DMI_AP_GET_TYPE4_TYPE7 - // Probe filter enable - L3_FEAT_AP_DISABLE_CACHE - L3_FEAT_AP_ENABLE_CACHE - - { 0, NULL } -}; - -#if AGESA_ENTRY_INIT_EARLY == TRUE - #if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_TRACING_ENABLED == TRUE - #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y) - CONST CHAR8 *BldOptDebugOutput[] = { - #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE - //Build Option Area - MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS) - MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS) - MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS) - MAKE_DBG_STR (\nOptECC, OPTION_ECC) - MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE) - MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE) - MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE) - //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING) - MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE) - MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR) - MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE) - MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET) - MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES) - MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT) - MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT) - MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA) - MAKE_DBG_STR (\nOptDMI, OPTION_DMI) - MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES), - - //Build Configuration Area - // CoreVrm - MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT) - MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD) - MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE) - MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY) - MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE) - MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT) - // NbVrm - MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT) - MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD) - MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE) - MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY) - MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE) - MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT), - - MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS) - MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE) - MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE) - MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA) - MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1) - MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2) - MAKE_DBG_STR (\nC1eOpdata3 , CFG_C1E_OPDATA3) - MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE) - MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA) - MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS) - MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE) - MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE), - - MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE) - MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST) - MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE) - MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH) - MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY) - MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD) - - MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST) - - MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE) - MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE) - MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE) - MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE), - - MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT) - MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT) - MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT) - - MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED) - MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE) - MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE) - MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE) - MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE) - MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE) - MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE) - MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL) - MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM) - MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE) - MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON), - - MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN) - MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE) - MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE) - MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE) - MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE) - MAKE_DBG_STR (\nLimitBelow1TB , CFG_LIMIT_MEMORY_TO_BELOW_1TB) - MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING) - MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING) - MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING), - - MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE) - MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE) - MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G) - MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT) - - MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE) - MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION) - MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE) - MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE) - MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE) - MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE) - MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE) - MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD) - MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE) - MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS) - MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN), - - MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE) - MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX) - - MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST) - - MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB) - MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0) - MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1) - MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO) - MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT) - MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE) - MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL) - MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT) - MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS), - MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID) - MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID) - MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID) - MAKE_DBG_STR (\nCfgIommuSupport , CFG_IOMMU_SUPPORT) - MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM) - MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL) - MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ) - MAKE_DBG_STR (\nCfgLcdBitDepthControlValue , CFG_LCD_BIT_DEPTH_CONTROL_VALUE) - MAKE_DBG_STR (\nCfgLvds24bbpPanelMode , CFG_LVDS_24BBP_PANEL_MODE), - MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM), - #endif - NULL - }; - #endif - #endif -#endif diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index 5ed6a39c29..4da54b7d19 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -38,6 +38,8 @@ AGESA_INC += -I$(AGESA_ROOT)/../common AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += $(AGESA_AUTOINCLUDES) +BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) + CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -- cgit v1.2.3