From b2d68976c830c3b4eddf78ea788f02cfa6d25ffc Mon Sep 17 00:00:00 2001
From: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date: Thu, 15 May 2014 21:23:51 +1000
Subject: amd/agesa: Implicit assigment between enum without cast

Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5760
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
---
 src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/vendorcode/amd/agesa/f12')

diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c
index eac35b7593..3664dc59ce 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c
@@ -178,7 +178,7 @@ MemNSyncTargetSpeedNb (
 //          ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
 //            (ChnlTmgMod[1] >= DDR667_FREQUENCY) :
 //            (ChnlTmgMod[1] <= DDR1066_FREQUENCY));
-          MemClkFreq = ChnlTmgMod[1];
+          MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1];
         }
       }
 
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